arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* Forward declarations for DPLL bypass clocks */
  53 static struct clk dpll1_fck;
  54 static struct clk dpll2_fck;
  55
  56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  57 #define DPLL_LOW_POWER_STOP             0x1
  58 #define DPLL_LOW_POWER_BYPASS           0x5
  59 #define DPLL_LOCKED                     0x7
  60
  61 /* PRM CLOCKS */
  62
  63 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  64 static struct clk omap_32k_fck = {
  65         .name           = "omap_32k_fck",
  66         .rate           = 32768,
  67         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  68                                 ALWAYS_ENABLED,
  69         .clkdm          = { .name = "prm_clkdm" },
  70         .recalc         = &propagate_rate,
  71 };
  72
  73 static struct clk secure_32k_fck = {
  74         .name           = "secure_32k_fck",
  75         .rate           = 32768,
  76         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  77                                 ALWAYS_ENABLED,
  78         .clkdm          = { .name = "prm_clkdm" },
  79         .recalc         = &propagate_rate,
  80 };
  81
  82 /* Virtual source clocks for osc_sys_ck */
  83 static struct clk virt_12m_ck = {
  84         .name           = "virt_12m_ck",
  85         .rate           = 12000000,
  86         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  87                                 ALWAYS_ENABLED,
  88         .clkdm          = { .name = "prm_clkdm" },
  89         .recalc         = &propagate_rate,
  90 };
  91
  92 static struct clk virt_13m_ck = {
  93         .name           = "virt_13m_ck",
  94         .rate           = 13000000,
  95         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  96                                 ALWAYS_ENABLED,
  97         .clkdm          = { .name = "prm_clkdm" },
  98         .recalc         = &propagate_rate,
  99 };
 100
 101 static struct clk virt_16_8m_ck = {
 102         .name           = "virt_16_8m_ck",
 103         .rate           = 16800000,
 104         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 105                                 ALWAYS_ENABLED,
 106         .clkdm          = { .name = "prm_clkdm" },
 107         .recalc         = &propagate_rate,
 108 };
 109
 110 static struct clk virt_19_2m_ck = {
 111         .name           = "virt_19_2m_ck",
 112         .rate           = 19200000,
 113         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 114                                 ALWAYS_ENABLED,
 115         .clkdm          = { .name = "prm_clkdm" },
 116         .recalc         = &propagate_rate,
 117 };
 118
 119 static struct clk virt_26m_ck = {
 120         .name           = "virt_26m_ck",
 121         .rate           = 26000000,
 122         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 123                                 ALWAYS_ENABLED,
 124         .clkdm          = { .name = "prm_clkdm" },
 125         .recalc         = &propagate_rate,
 126 };
 127
 128 static struct clk virt_38_4m_ck = {
 129         .name           = "virt_38_4m_ck",
 130         .rate           = 38400000,
 131         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 132                                 ALWAYS_ENABLED,
 133         .clkdm          = { .name = "prm_clkdm" },
 134         .recalc         = &propagate_rate,
 135 };
 136
 137 static const struct clksel_rate osc_sys_12m_rates[] = {
 138         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 139         { .div = 0 }
 140 };
 141
 142 static const struct clksel_rate osc_sys_13m_rates[] = {
 143         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 144         { .div = 0 }
 145 };
 146
 147 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 148         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 149         { .div = 0 }
 150 };
 151
 152 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 153         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 154         { .div = 0 }
 155 };
 156
 157 static const struct clksel_rate osc_sys_26m_rates[] = {
 158         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 159         { .div = 0 }
 160 };
 161
 162 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 163         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 164         { .div = 0 }
 165 };
 166
 167 static const struct clksel osc_sys_clksel[] = {
 168         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 169         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 170         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 171         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 172         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 173         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 174         { .parent = NULL },
 175 };
 176
 177 /* Oscillator clock */
 178 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 179 static struct clk osc_sys_ck = {
 180         .name           = "osc_sys_ck",
 181         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 182         .init           = &omap2_init_clksel_parent,
 183         .clksel_reg     = OMAP3_PRM_CLKSEL_OFFSET,
 184         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 185         .clksel         = osc_sys_clksel,
 186         /* REVISIT: deal with autoextclkmode? */
 187         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 188                                 ALWAYS_ENABLED,
 189         .clkdm          = { .name = "prm_clkdm" },
 190         .recalc         = &omap2_clksel_recalc,
 191 };
 192
 193 static const struct clksel_rate div2_rates[] = {
 194         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 195         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 196         { .div = 0 }
 197 };
 198
 199 static const struct clksel sys_clksel[] = {
 200         { .parent = &osc_sys_ck, .rates = div2_rates },
 201         { .parent = NULL }
 202 };
 203
 204 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 205 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 206 static struct clk sys_ck = {
 207         .name           = "sys_ck",
 208         .parent         = &osc_sys_ck,
 209         .prcm_mod       = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
 210         .init           = &omap2_init_clksel_parent,
 211         .clksel_reg     = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
 212         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 213         .clksel         = sys_clksel,
 214         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 215         .clkdm          = { .name = "prm_clkdm" },
 216         .recalc         = &omap2_clksel_recalc,
 217 };
 218
 219 static struct clk sys_altclk = {
 220         .name           = "sys_altclk",
 221         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 222         .clkdm          = { .name = "cm_clkdm" },
 223         .recalc         = &propagate_rate,
 224 };
 225
 226 /*
 227  * Optional external clock input for some McBSPs
 228  * Apparently this is not really in prm_clkdm, but rather is fed into
 229  * both CORE and PER separately.
 230  */
 231 static struct clk mcbsp_clks = {
 232         .name           = "mcbsp_clks",
 233         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 234         .clkdm          = { .name = "prm_clkdm" },
 235         .recalc         = &propagate_rate,
 236 };
 237
 238 /* PRM EXTERNAL CLOCK OUTPUT */
 239
 240 static struct clk sys_clkout1 = {
 241         .name           = "sys_clkout1",
 242         .parent         = &osc_sys_ck,
 243         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 244         .enable_reg     = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
 245         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 246         .flags          = CLOCK_IN_OMAP343X,
 247         .clkdm          = { .name = "prm_clkdm" },
 248         .recalc         = &followparent_recalc,
 249 };
 250
 251 /* DPLLS */
 252
 253 /* CM CLOCKS */
 254
 255 static const struct clksel_rate div16_dpll_rates[] = {
 256         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 257         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 258         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 259         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 260         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 261         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 262         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 263         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 264         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 265         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 266         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 267         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 268         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 269         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 270         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 271         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 272         { .div = 0 }
 273 };
 274
 275 /* DPLL1 */
 276 /* MPU clock source */
 277 /* Type: DPLL */
 278 static struct dpll_data dpll1_dd = {
 279         .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
 280         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 281         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 282         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 283         .control_reg    = OMAP3430_CM_CLKEN_PLL,
 284         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 285         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 286         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 287         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 288         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 289         .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
 290         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 291         .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
 292         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 293         .bypass_clk     = &dpll1_fck,
 294         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 295         .min_divider    = 1,
 296         .max_divider    = OMAP3_MAX_DPLL_DIV,
 297         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 298 };
 299
 300 static struct clk dpll1_ck = {
 301         .name           = "dpll1_ck",
 302         .parent         = &sys_ck,
 303         .prcm_mod       = MPU_MOD,
 304         .dpll_data      = &dpll1_dd,
 305         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 306         .round_rate     = &omap2_dpll_round_rate,
 307         .set_rate       = &omap3_noncore_dpll_set_rate,
 308         .clkdm          = { .name = "dpll1_clkdm" },
 309         .recalc         = &omap3_dpll_recalc,
 310 };
 311
 312 /*
 313  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 314  * DPLL isn't bypassed.
 315  */
 316 static struct clk dpll1_x2_ck = {
 317         .name           = "dpll1_x2_ck",
 318         .parent         = &dpll1_ck,
 319         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 320                                 PARENT_CONTROLS_CLOCK,
 321         .clkdm          = { .name = "dpll1_clkdm" },
 322         .recalc         = &omap3_clkoutx2_recalc,
 323 };
 324
 325 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 326 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 327         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 328         { .parent = NULL }
 329 };
 330
 331 /*
 332  * Does not exist in the TRM - needed to separate the M2 divider from
 333  * bypass selection in mpu_ck
 334  */
 335 static struct clk dpll1_x2m2_ck = {
 336         .name           = "dpll1_x2m2_ck",
 337         .parent         = &dpll1_x2_ck,
 338         .prcm_mod       = MPU_MOD,
 339         .init           = &omap2_init_clksel_parent,
 340         .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
 341         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 342         .clksel         = div16_dpll1_x2m2_clksel,
 343         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 344                                 PARENT_CONTROLS_CLOCK,
 345         .clkdm          = { .name = "dpll1_clkdm" },
 346         .recalc         = &omap2_clksel_recalc,
 347 };
 348
 349 /* DPLL2 */
 350 /* IVA2 clock source */
 351 /* Type: DPLL */
 352
 353 static struct dpll_data dpll2_dd = {
 354         .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
 355         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 356         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 357         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 358         .control_reg    = OMAP3430_CM_CLKEN_PLL,
 359         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 360         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 361                                 (1 << DPLL_LOW_POWER_BYPASS),
 362         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 363         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 364         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 365         .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
 366         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 367         .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
 368         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 369         .bypass_clk     = &dpll2_fck,
 370         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 371         .min_divider    = 1,
 372         .max_divider    = OMAP3_MAX_DPLL_DIV,
 373         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 374 };
 375
 376 static struct clk dpll2_ck = {
 377         .name           = "dpll2_ck",
 378         .parent         = &sys_ck,
 379         .prcm_mod       = OMAP3430_IVA2_MOD,
 380         .dpll_data      = &dpll2_dd,
 381         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 382         .enable         = &omap3_noncore_dpll_enable,
 383         .disable        = &omap3_noncore_dpll_disable,
 384         .round_rate     = &omap2_dpll_round_rate,
 385         .set_rate       = &omap3_noncore_dpll_set_rate,
 386         .clkdm          = { .name = "dpll2_clkdm" },
 387         .recalc         = &omap3_dpll_recalc,
 388 };
 389
 390 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 391         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 392         { .parent = NULL }
 393 };
 394
 395 /*
 396  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 397  * or CLKOUTX2. CLKOUT seems most plausible.
 398  */
 399 static struct clk dpll2_m2_ck = {
 400         .name           = "dpll2_m2_ck",
 401         .parent         = &dpll2_ck,
 402         .prcm_mod       = OMAP3430_IVA2_MOD,
 403         .init           = &omap2_init_clksel_parent,
 404         .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
 405         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 406         .clksel         = div16_dpll2_m2x2_clksel,
 407         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 408                                 PARENT_CONTROLS_CLOCK,
 409         .clkdm          = { .name = "dpll2_clkdm" },
 410         .recalc         = &omap2_clksel_recalc,
 411 };
 412
 413 /*
 414  * DPLL3
 415  * Source clock for all interfaces and for some device fclks
 416  * REVISIT: Also supports fast relock bypass - not included below
 417  */
 418 static struct dpll_data dpll3_dd = {
 419         .mult_div1_reg  = CM_CLKSEL1,
 420         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 421         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 422         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 423         .control_reg    = CM_CLKEN,
 424         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 425         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 426         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 427         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 428         .autoidle_reg   = CM_AUTOIDLE,
 429         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 430         .idlest_reg     = CM_IDLEST,
 431         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 432         .bypass_clk     = &sys_ck,
 433         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 434         .min_divider    = 1,
 435         .max_divider    = OMAP3_MAX_DPLL_DIV,
 436         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 437 };
 438
 439 static struct clk dpll3_ck = {
 440         .name           = "dpll3_ck",
 441         .parent         = &sys_ck,
 442         .prcm_mod       = PLL_MOD,
 443         .dpll_data      = &dpll3_dd,
 444         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 445         .round_rate     = &omap2_dpll_round_rate,
 446         .clkdm          = { .name = "dpll3_clkdm" },
 447         .recalc         = &omap3_dpll_recalc,
 448 };
 449
 450 /*
 451  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 452  * DPLL isn't bypassed
 453  */
 454 static struct clk dpll3_x2_ck = {
 455         .name           = "dpll3_x2_ck",
 456         .parent         = &dpll3_ck,
 457         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 458                                 PARENT_CONTROLS_CLOCK,
 459         .clkdm          = { .name = "dpll3_clkdm" },
 460         .recalc         = &omap3_clkoutx2_recalc,
 461 };
 462
 463 static const struct clksel_rate div31_dpll3_rates[] = {
 464         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 465         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 466         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 467         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 468         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 469         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 470         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 471         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 472         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 473         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 474         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 475         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 476         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 477         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 478         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 479         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 480         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 481         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 482         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 483         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 484         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 485         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 486         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 487         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 488         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 489         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 490         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 491         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 492         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 493         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 494         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 495         { .div = 0 },
 496 };
 497
 498 static const struct clksel div31_dpll3m2_clksel[] = {
 499         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 500         { .parent = NULL }
 501 };
 502
 503 /* DPLL3 output M2 - primary control point for CORE speed */
 504 static struct clk dpll3_m2_ck = {
 505         .name           = "dpll3_m2_ck",
 506         .parent         = &dpll3_ck,
 507         .prcm_mod       = PLL_MOD,
 508         .init           = &omap2_init_clksel_parent,
 509         .clksel_reg     = CM_CLKSEL1,
 510         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 511         .clksel         = div31_dpll3m2_clksel,
 512         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 513                                 PARENT_CONTROLS_CLOCK,
 514         .clkdm          = { .name = "dpll3_clkdm" },
 515         .round_rate     = &omap2_clksel_round_rate,
 516         .set_rate       = &omap3_core_dpll_m2_set_rate,
 517         .recalc         = &omap2_clksel_recalc,
 518 };
 519
 520 static struct clk core_ck = {
 521         .name           = "core_ck",
 522         .parent         = &dpll3_m2_ck,
 523         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 524                                 PARENT_CONTROLS_CLOCK,
 525         .clkdm          = { .name = "cm_clkdm" },
 526         .recalc         = &followparent_recalc,
 527 };
 528
 529 static struct clk dpll3_m2x2_ck = {
 530         .name           = "dpll3_m2x2_ck",
 531         .parent         = &dpll3_x2_ck,
 532         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 533                                 PARENT_CONTROLS_CLOCK,
 534         .clkdm          = { .name = "dpll3_clkdm" },
 535         .recalc         = &followparent_recalc,
 536 };
 537
 538 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 539 static const struct clksel div16_dpll3_clksel[] = {
 540         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 541         { .parent = NULL }
 542 };
 543
 544 /* This virtual clock is the source for dpll3_m3x2_ck */
 545 static struct clk dpll3_m3_ck = {
 546         .name           = "dpll3_m3_ck",
 547         .parent         = &dpll3_ck,
 548         .prcm_mod       = OMAP3430_EMU_MOD,
 549         .init           = &omap2_init_clksel_parent,
 550         .clksel_reg     = CM_CLKSEL1,
 551         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 552         .clksel         = div16_dpll3_clksel,
 553         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 554                                 PARENT_CONTROLS_CLOCK,
 555         .clkdm          = { .name = "dpll3_clkdm" },
 556         .recalc         = &omap2_clksel_recalc,
 557 };
 558
 559 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 560 static struct clk dpll3_m3x2_ck = {
 561         .name           = "dpll3_m3x2_ck",
 562         .parent         = &dpll3_m3_ck,
 563         .prcm_mod       = PLL_MOD,
 564         .enable_reg     = CM_CLKEN,
 565         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 566         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 567         .clkdm          = { .name = "dpll3_clkdm" },
 568         .recalc         = &omap3_clkoutx2_recalc,
 569 };
 570
 571 static struct clk emu_core_alwon_ck = {
 572         .name           = "emu_core_alwon_ck",
 573         .parent         = &dpll3_m3x2_ck,
 574         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 575                                 PARENT_CONTROLS_CLOCK,
 576         .clkdm          = { .name = "dpll3_clkdm" },
 577         .recalc         = &followparent_recalc,
 578 };
 579
 580 /* DPLL4 */
 581 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 582 /* Type: DPLL */
 583 static struct dpll_data dpll4_dd = {
 584         .mult_div1_reg  = CM_CLKSEL2,
 585         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 586         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 587         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 588         .control_reg    = CM_CLKEN,
 589         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 590         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 591         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 592         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 593         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 594         .autoidle_reg   = CM_AUTOIDLE,
 595         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 596         .idlest_reg     = CM_IDLEST,
 597         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 598         .bypass_clk     = &sys_ck,
 599         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 600         .min_divider    = 1,
 601         .max_divider    = OMAP3_MAX_DPLL_DIV,
 602         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 603 };
 604
 605 static struct clk dpll4_ck = {
 606         .name           = "dpll4_ck",
 607         .parent         = &sys_ck,
 608         .prcm_mod       = PLL_MOD,
 609         .dpll_data      = &dpll4_dd,
 610         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 611         .enable         = &omap3_noncore_dpll_enable,
 612         .disable        = &omap3_noncore_dpll_disable,
 613         .round_rate     = &omap2_dpll_round_rate,
 614         .set_rate       = &omap3_noncore_dpll_set_rate,
 615         .clkdm          = { .name = "dpll4_clkdm" },
 616         .recalc         = &omap3_dpll_recalc,
 617 };
 618
 619 /*
 620  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 621  * DPLL isn't bypassed --
 622  * XXX does this serve any downstream clocks?
 623  */
 624 static struct clk dpll4_x2_ck = {
 625         .name           = "dpll4_x2_ck",
 626         .parent         = &dpll4_ck,
 627         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 628                                 PARENT_CONTROLS_CLOCK,
 629         .clkdm          = { .name = "dpll4_clkdm" },
 630         .recalc         = &omap3_clkoutx2_recalc,
 631 };
 632
 633 static const struct clksel div16_dpll4_clksel[] = {
 634         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 635         { .parent = NULL }
 636 };
 637
 638 /* This virtual clock is the source for dpll4_m2x2_ck */
 639 static struct clk dpll4_m2_ck = {
 640         .name           = "dpll4_m2_ck",
 641         .parent         = &dpll4_ck,
 642         .prcm_mod       = PLL_MOD,
 643         .init           = &omap2_init_clksel_parent,
 644         .clksel_reg     = OMAP3430_CM_CLKSEL3,
 645         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 646         .clksel         = div16_dpll4_clksel,
 647         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 648                                 PARENT_CONTROLS_CLOCK,
 649         .clkdm          = { .name = "dpll4_clkdm" },
 650         .recalc         = &omap2_clksel_recalc,
 651 };
 652
 653 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 654 static struct clk dpll4_m2x2_ck = {
 655         .name           = "dpll4_m2x2_ck",
 656         .parent         = &dpll4_m2_ck,
 657         .prcm_mod       = PLL_MOD,
 658         .enable_reg     = CM_CLKEN,
 659         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 660         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 661         .clkdm          = { .name = "dpll4_clkdm" },
 662         .recalc         = &omap3_clkoutx2_recalc,
 663 };
 664
 665 /*
 666  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 667  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 668  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 669  * CM_96K_(F)CLK.
 670  */
 671 static struct clk omap_96m_alwon_fck = {
 672         .name           = "omap_96m_alwon_fck",
 673         .parent         = &dpll4_m2x2_ck,
 674         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 675                                 PARENT_CONTROLS_CLOCK,
 676         .clkdm          = { .name = "prm_clkdm" },
 677         .recalc         = &followparent_recalc,
 678 };
 679
 680 static struct clk cm_96m_fck = {
 681         .name           = "cm_96m_fck",
 682         .parent         = &omap_96m_alwon_fck,
 683         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 684                                 PARENT_CONTROLS_CLOCK,
 685         .clkdm          = { .name = "cm_clkdm" },
 686         .recalc         = &followparent_recalc,
 687 };
 688
 689 static const struct clksel_rate omap_96m_dpll_rates[] = {
 690         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 691         { .div = 0 }
 692 };
 693
 694 static const struct clksel_rate omap_96m_sys_rates[] = {
 695         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 696         { .div = 0 }
 697 };
 698
 699 static const struct clksel omap_96m_fck_clksel[] = {
 700         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 701         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 702         { .parent = NULL }
 703 };
 704
 705 static struct clk omap_96m_fck = {
 706         .name           = "omap_96m_fck",
 707         .parent         = &sys_ck,
 708         .prcm_mod       = PLL_MOD,
 709         .init           = &omap2_init_clksel_parent,
 710         .clksel_reg     = CM_CLKSEL1,
 711         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 712         .clksel         = omap_96m_fck_clksel,
 713         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 714                                 PARENT_CONTROLS_CLOCK,
 715         .clkdm          = { .name = "cm_clkdm" },
 716         .recalc         = &omap2_clksel_recalc,
 717 };
 718
 719 /* This virtual clock is the source for dpll4_m3x2_ck */
 720 static struct clk dpll4_m3_ck = {
 721         .name           = "dpll4_m3_ck",
 722         .parent         = &dpll4_ck,
 723         .prcm_mod       = OMAP3430_DSS_MOD,
 724         .init           = &omap2_init_clksel_parent,
 725         .clksel_reg     = CM_CLKSEL,
 726         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 727         .clksel         = div16_dpll4_clksel,
 728         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 729                                 PARENT_CONTROLS_CLOCK,
 730         .clkdm          = { .name = "dpll4_clkdm" },
 731         .recalc         = &omap2_clksel_recalc,
 732 };
 733
 734 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 735 static struct clk dpll4_m3x2_ck = {
 736         .name           = "dpll4_m3x2_ck",
 737         .parent         = &dpll4_m3_ck,
 738         .prcm_mod       = PLL_MOD,
 739         .init           = &omap2_init_clksel_parent,
 740         .enable_reg     = CM_CLKEN,
 741         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 742         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 743         .clkdm          = { .name = "dpll4_clkdm" },
 744         .recalc         = &omap3_clkoutx2_recalc,
 745 };
 746
 747 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 748         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 749         { .div = 0 }
 750 };
 751
 752 static const struct clksel_rate omap_54m_alt_rates[] = {
 753         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 754         { .div = 0 }
 755 };
 756
 757 static const struct clksel omap_54m_clksel[] = {
 758         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 759         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 760         { .parent = NULL }
 761 };
 762
 763 static struct clk omap_54m_fck = {
 764         .name           = "omap_54m_fck",
 765         .prcm_mod       = PLL_MOD,
 766         .init           = &omap2_init_clksel_parent,
 767         .clksel_reg     = CM_CLKSEL1,
 768         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 769         .clksel         = omap_54m_clksel,
 770         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 771                                 PARENT_CONTROLS_CLOCK,
 772         .clkdm          = { .name = "cm_clkdm" },
 773         .recalc         = &omap2_clksel_recalc,
 774 };
 775
 776 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 777         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 778         { .div = 0 }
 779 };
 780
 781 static const struct clksel_rate omap_48m_alt_rates[] = {
 782         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 783         { .div = 0 }
 784 };
 785
 786 static const struct clksel omap_48m_clksel[] = {
 787         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 788         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 789         { .parent = NULL }
 790 };
 791
 792 static struct clk omap_48m_fck = {
 793         .name           = "omap_48m_fck",
 794         .prcm_mod       = PLL_MOD,
 795         .init           = &omap2_init_clksel_parent,
 796         .clksel_reg     = CM_CLKSEL1,
 797         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 798         .clksel         = omap_48m_clksel,
 799         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 800                                 PARENT_CONTROLS_CLOCK,
 801         .clkdm          = { .name = "cm_clkdm" },
 802         .recalc         = &omap2_clksel_recalc,
 803 };
 804
 805 static struct clk omap_12m_fck = {
 806         .name           = "omap_12m_fck",
 807         .parent         = &omap_48m_fck,
 808         .fixed_div      = 4,
 809         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 810                                 PARENT_CONTROLS_CLOCK,
 811         .clkdm          = { .name = "cm_clkdm" },
 812         .recalc         = &omap2_fixed_divisor_recalc,
 813 };
 814
 815 /* This virstual clock is the source for dpll4_m4x2_ck */
 816 static struct clk dpll4_m4_ck = {
 817         .name           = "dpll4_m4_ck",
 818         .parent         = &dpll4_ck,
 819         .prcm_mod       = OMAP3430_DSS_MOD,
 820         .init           = &omap2_init_clksel_parent,
 821         .clksel_reg     = CM_CLKSEL,
 822         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 823         .clksel         = div16_dpll4_clksel,
 824         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 825                                 PARENT_CONTROLS_CLOCK,
 826         .clkdm          = { .name = "dpll4_clkdm" },
 827         .recalc         = &omap2_clksel_recalc,
 828 };
 829
 830 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 831 static struct clk dpll4_m4x2_ck = {
 832         .name           = "dpll4_m4x2_ck",
 833         .parent         = &dpll4_m4_ck,
 834         .prcm_mod       = PLL_MOD,
 835         .enable_reg     = CM_CLKEN,
 836         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 837         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 838         .clkdm          = { .name = "dpll4_clkdm" },
 839         .recalc         = &omap3_clkoutx2_recalc,
 840 };
 841
 842 /* This virtual clock is the source for dpll4_m5x2_ck */
 843 static struct clk dpll4_m5_ck = {
 844         .name           = "dpll4_m5_ck",
 845         .parent         = &dpll4_ck,
 846         .prcm_mod       = OMAP3430_CAM_MOD,
 847         .init           = &omap2_init_clksel_parent,
 848         .clksel_reg     = CM_CLKSEL,
 849         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 850         .clksel         = div16_dpll4_clksel,
 851         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 852                                 PARENT_CONTROLS_CLOCK,
 853         .clkdm          = { .name = "dpll4_clkdm" },
 854         .recalc         = &omap2_clksel_recalc,
 855 };
 856
 857 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 858 static struct clk dpll4_m5x2_ck = {
 859         .name           = "dpll4_m5x2_ck",
 860         .parent         = &dpll4_m5_ck,
 861         .prcm_mod       = PLL_MOD,
 862         .enable_reg     = CM_CLKEN,
 863         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 864         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 865         .clkdm          = { .name = "dpll4_clkdm" },
 866         .recalc         = &omap3_clkoutx2_recalc,
 867 };
 868
 869 /* This virtual clock is the source for dpll4_m6x2_ck */
 870 static struct clk dpll4_m6_ck = {
 871         .name           = "dpll4_m6_ck",
 872         .parent         = &dpll4_ck,
 873         .prcm_mod       = OMAP3430_EMU_MOD,
 874         .init           = &omap2_init_clksel_parent,
 875         .clksel_reg     = CM_CLKSEL1,
 876         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 877         .clksel         = div16_dpll4_clksel,
 878         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 879                                 PARENT_CONTROLS_CLOCK,
 880         .clkdm          = { .name = "dpll4_clkdm" },
 881         .recalc         = &omap2_clksel_recalc,
 882 };
 883
 884 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 885 static struct clk dpll4_m6x2_ck = {
 886         .name           = "dpll4_m6x2_ck",
 887         .parent         = &dpll4_m6_ck,
 888         .prcm_mod       = PLL_MOD,
 889         .init           = &omap2_init_clksel_parent,
 890         .enable_reg     = CM_CLKEN,
 891         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 892         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 893         .clkdm          = { .name = "dpll4_clkdm" },
 894         .recalc         = &omap3_clkoutx2_recalc,
 895 };
 896
 897 static struct clk emu_per_alwon_ck = {
 898         .name           = "emu_per_alwon_ck",
 899         .parent         = &dpll4_m6x2_ck,
 900         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 901                                 PARENT_CONTROLS_CLOCK,
 902         .clkdm          = { .name = "dpll4_clkdm" },
 903         .recalc         = &followparent_recalc,
 904 };
 905
 906 /* DPLL5 */
 907 /* Supplies 120MHz clock, USIM source clock */
 908 /* Type: DPLL */
 909 /* 3430ES2 only */
 910 static struct dpll_data dpll5_dd = {
 911         .mult_div1_reg  = OMAP3430ES2_CM_CLKSEL4,
 912         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 913         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 914         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 915         .control_reg    = OMAP3430ES2_CM_CLKEN2,
 916         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 917         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 918         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 919         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 920         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 921         .autoidle_reg   = OMAP3430ES2_CM_AUTOIDLE2_PLL,
 922         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 923         .idlest_reg     = CM_IDLEST2,
 924         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 925         .bypass_clk     = &sys_ck,
 926         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 927         .min_divider    = 1,
 928         .max_divider    = OMAP3_MAX_DPLL_DIV,
 929         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 930 };
 931
 932 static struct clk dpll5_ck = {
 933         .name           = "dpll5_ck",
 934         .parent         = &sys_ck,
 935         .prcm_mod       = PLL_MOD,
 936         .dpll_data      = &dpll5_dd,
 937         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 938         .enable         = &omap3_noncore_dpll_enable,
 939         .disable        = &omap3_noncore_dpll_disable,
 940         .round_rate     = &omap2_dpll_round_rate,
 941         .set_rate       = &omap3_noncore_dpll_set_rate,
 942         .clkdm          = { .name = "dpll5_clkdm" },
 943         .recalc         = &omap3_dpll_recalc,
 944 };
 945
 946 static const struct clksel div16_dpll5_clksel[] = {
 947         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 948         { .parent = NULL }
 949 };
 950
 951 static struct clk dpll5_m2_ck = {
 952         .name           = "dpll5_m2_ck",
 953         .parent         = &dpll5_ck,
 954         .prcm_mod       = PLL_MOD,
 955         .init           = &omap2_init_clksel_parent,
 956         .clksel_reg     = OMAP3430ES2_CM_CLKSEL5,
 957         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 958         .clksel         = div16_dpll5_clksel,
 959         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 960                                 PARENT_CONTROLS_CLOCK,
 961         .clkdm          = { .name = "dpll5_clkdm" },
 962         .recalc         = &omap2_clksel_recalc,
 963 };
 964
 965 /* CM EXTERNAL CLOCK OUTPUTS */
 966
 967 static const struct clksel_rate clkout2_src_core_rates[] = {
 968         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 969         { .div = 0 }
 970 };
 971
 972 static const struct clksel_rate clkout2_src_sys_rates[] = {
 973         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 974         { .div = 0 }
 975 };
 976
 977 static const struct clksel_rate clkout2_src_96m_rates[] = {
 978         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 979         { .div = 0 }
 980 };
 981
 982 static const struct clksel_rate clkout2_src_54m_rates[] = {
 983         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 984         { .div = 0 }
 985 };
 986
 987 static const struct clksel clkout2_src_clksel[] = {
 988         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 989         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 990         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 991         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 992         { .parent = NULL }
 993 };
 994
 995 static struct clk clkout2_src_ck = {
 996         .name           = "clkout2_src_ck",
 997         .prcm_mod       = OMAP3430_CCR_MOD,
 998         .init           = &omap2_init_clksel_parent,
 999         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1000         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1001         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1002         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1003         .clksel         = clkout2_src_clksel,
1004         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1005         .clkdm          = { .name = "cm_clkdm" },
1006         .recalc         = &omap2_clksel_recalc,
1007 };
1008
1009 static const struct clksel_rate sys_clkout2_rates[] = {
1010         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1011         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1012         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1013         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1014         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1015         { .div = 0 },
1016 };
1017
1018 static const struct clksel sys_clkout2_clksel[] = {
1019         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1020         { .parent = NULL },
1021 };
1022
1023 static struct clk sys_clkout2 = {
1024         .name           = "sys_clkout2",
1025         .prcm_mod       = OMAP3430_CCR_MOD,
1026         .init           = &omap2_init_clksel_parent,
1027         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1028         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1029         .clksel         = sys_clkout2_clksel,
1030         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1031         .clkdm          = { .name = "cm_clkdm" },
1032         .recalc         = &omap2_clksel_recalc,
1033 };
1034
1035 /* CM OUTPUT CLOCKS */
1036
1037 static struct clk corex2_fck = {
1038         .name           = "corex2_fck",
1039         .parent         = &dpll3_m2x2_ck,
1040         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1041                                 PARENT_CONTROLS_CLOCK,
1042         .clkdm          = { .name = "cm_clkdm" },
1043         .recalc         = &followparent_recalc,
1044 };
1045
1046 /* DPLL power domain clock controls */
1047
1048 static const struct clksel_rate div4_rates[] = {
1049         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1050         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1051         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1052         { .div = 0 }
1053 };
1054
1055 static const struct clksel div4_core_clksel[] = {
1056         { .parent = &core_ck, .rates = div4_rates },
1057         { .parent = NULL }
1058 };
1059
1060 static struct clk dpll1_fck = {
1061         .name           = "dpll1_fck",
1062         .parent         = &core_ck,
1063         .prcm_mod       = MPU_MOD,
1064         .init           = &omap2_init_clksel_parent,
1065         .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
1066         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1067         .clksel         = div4_core_clksel,
1068         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1069                                 PARENT_CONTROLS_CLOCK,
1070         .clkdm          = { .name = "cm_clkdm" },
1071         .recalc         = &omap2_clksel_recalc,
1072 };
1073
1074 static struct clk mpu_ck = {
1075         .name           = "mpu_ck",
1076         .parent         = &dpll1_x2m2_ck,
1077         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1078                                 PARENT_CONTROLS_CLOCK,
1079         .clkdm          = { .name = "mpu_clkdm" },
1080         .recalc         = &followparent_recalc,
1081 };
1082
1083 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1084 static const struct clksel_rate arm_fck_rates[] = {
1085         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1086         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1087         { .div = 0 },
1088 };
1089
1090 static const struct clksel arm_fck_clksel[] = {
1091         { .parent = &mpu_ck, .rates = arm_fck_rates },
1092         { .parent = NULL }
1093 };
1094
1095 static struct clk arm_fck = {
1096         .name           = "arm_fck",
1097         .parent         = &mpu_ck,
1098         .prcm_mod       = MPU_MOD,
1099         .init           = &omap2_init_clksel_parent,
1100         .clksel_reg     = OMAP3430_CM_IDLEST_PLL,
1101         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1102         .clksel         = arm_fck_clksel,
1103         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1104                                 PARENT_CONTROLS_CLOCK,
1105         .clkdm          = { .name = "mpu_clkdm" },
1106         .recalc         = &omap2_clksel_recalc,
1107 };
1108
1109 /* XXX What about neon_clkdm ? */
1110
1111 /*
1112  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1113  * although it is referenced - so this is a guess
1114  */
1115 static struct clk emu_mpu_alwon_ck = {
1116         .name           = "emu_mpu_alwon_ck",
1117         .parent         = &mpu_ck,
1118         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1119                                 PARENT_CONTROLS_CLOCK,
1120         .clkdm          = { .name = "mpu_clkdm" },
1121         .recalc         = &followparent_recalc,
1122 };
1123
1124 static struct clk dpll2_fck = {
1125         .name           = "dpll2_fck",
1126         .parent         = &core_ck,
1127         .prcm_mod       = OMAP3430_IVA2_MOD,
1128         .init           = &omap2_init_clksel_parent,
1129         .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
1130         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1131         .clksel         = div4_core_clksel,
1132         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1133                                 PARENT_CONTROLS_CLOCK,
1134         .clkdm          = { .name = "cm_clkdm" },
1135         .recalc         = &omap2_clksel_recalc,
1136 };
1137
1138 static struct clk iva2_ck = {
1139         .name           = "iva2_ck",
1140         .parent         = &dpll2_m2_ck,
1141         .prcm_mod       = OMAP3430_IVA2_MOD,
1142         .init           = &omap2_init_clksel_parent,
1143         .enable_reg     = CM_FCLKEN,
1144         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1145         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1146         .clkdm          = { .name = "iva2_clkdm" },
1147         .recalc         = &followparent_recalc,
1148 };
1149
1150 /* Common interface clocks */
1151
1152 static const struct clksel div2_core_clksel[] = {
1153         { .parent = &core_ck, .rates = div2_rates },
1154         { .parent = NULL }
1155 };
1156
1157 static struct clk l3_ick = {
1158         .name           = "l3_ick",
1159         .parent         = &core_ck,
1160         .prcm_mod       = CORE_MOD,
1161         .init           = &omap2_init_clksel_parent,
1162         .clksel_reg     = CM_CLKSEL,
1163         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1164         .clksel         = div2_core_clksel,
1165         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1166                                 PARENT_CONTROLS_CLOCK,
1167         .clkdm          = { .name = "core_l3_clkdm" },
1168         .recalc         = &omap2_clksel_recalc,
1169 };
1170
1171 static const struct clksel div2_l3_clksel[] = {
1172         { .parent = &l3_ick, .rates = div2_rates },
1173         { .parent = NULL }
1174 };
1175
1176 static struct clk l4_ick = {
1177         .name           = "l4_ick",
1178         .parent         = &l3_ick,
1179         .prcm_mod       = CORE_MOD,
1180         .init           = &omap2_init_clksel_parent,
1181         .clksel_reg     = CM_CLKSEL,
1182         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1183         .clksel         = div2_l3_clksel,
1184         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1185                                 PARENT_CONTROLS_CLOCK,
1186         .clkdm          = { .name = "core_l4_clkdm" },
1187         .recalc         = &omap2_clksel_recalc,
1188
1189 };
1190
1191 static const struct clksel div2_l4_clksel[] = {
1192         { .parent = &l4_ick, .rates = div2_rates },
1193         { .parent = NULL }
1194 };
1195
1196 static struct clk rm_ick = {
1197         .name           = "rm_ick",
1198         .parent         = &l4_ick,
1199         .prcm_mod       = WKUP_MOD,
1200         .init           = &omap2_init_clksel_parent,
1201         .clksel_reg     = CM_CLKSEL,
1202         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1203         .clksel         = div2_l4_clksel,
1204         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1205         .clkdm          = { .name = "cm_clkdm" },
1206         .recalc         = &omap2_clksel_recalc,
1207 };
1208
1209 /* GFX power domain */
1210
1211 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1212
1213 static const struct clksel gfx_l3_clksel[] = {
1214         { .parent = &l3_ick, .rates = gfx_l3_rates },
1215         { .parent = NULL }
1216 };
1217
1218 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1219 static struct clk gfx_l3_ck = {
1220         .name           = "gfx_l3_ck",
1221         .parent         = &l3_ick,
1222         .prcm_mod       = GFX_MOD,
1223         .init           = &omap2_init_clksel_parent,
1224         .enable_reg     = CM_ICLKEN,
1225         .enable_bit     = OMAP_EN_GFX_SHIFT,
1226         .flags          = CLOCK_IN_OMAP3430ES1,
1227         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1228         .recalc         = &followparent_recalc,
1229 };
1230
1231 static struct clk gfx_l3_fck = {
1232         .name           = "gfx_l3_fck",
1233         .parent         = &gfx_l3_ck,
1234         .prcm_mod       = GFX_MOD,
1235         .init           = &omap2_init_clksel_parent,
1236         .clksel_reg     = CM_CLKSEL,
1237         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1238         .clksel         = gfx_l3_clksel,
1239         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1240                                 PARENT_CONTROLS_CLOCK,
1241         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1242         .recalc         = &omap2_clksel_recalc,
1243 };
1244
1245 static struct clk gfx_l3_ick = {
1246         .name           = "gfx_l3_ick",
1247         .parent         = &gfx_l3_ck,
1248         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1249         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1250         .recalc         = &followparent_recalc,
1251 };
1252
1253 static struct clk gfx_cg1_ck = {
1254         .name           = "gfx_cg1_ck",
1255         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1256         .prcm_mod       = GFX_MOD,
1257         .enable_reg     = CM_FCLKEN,
1258         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1259         .flags          = CLOCK_IN_OMAP3430ES1,
1260         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1261         .recalc         = &followparent_recalc,
1262 };
1263
1264 static struct clk gfx_cg2_ck = {
1265         .name           = "gfx_cg2_ck",
1266         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1267         .prcm_mod       = GFX_MOD,
1268         .enable_reg     = CM_FCLKEN,
1269         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1270         .flags          = CLOCK_IN_OMAP3430ES1,
1271         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1272         .recalc         = &followparent_recalc,
1273 };
1274
1275 /* SGX power domain - 3430ES2 only */
1276
1277 static const struct clksel_rate sgx_core_rates[] = {
1278         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1279         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1280         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1281         { .div = 0 },
1282 };
1283
1284 static const struct clksel_rate sgx_96m_rates[] = {
1285         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1286         { .div = 0 },
1287 };
1288
1289 static const struct clksel sgx_clksel[] = {
1290         { .parent = &core_ck,    .rates = sgx_core_rates },
1291         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1292         { .parent = NULL },
1293 };
1294
1295 static struct clk sgx_fck = {
1296         .name           = "sgx_fck",
1297         .init           = &omap2_init_clksel_parent,
1298         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1299         .enable_reg     = CM_FCLKEN,
1300         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1301         .clksel_reg     = CM_CLKSEL,
1302         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1303         .clksel         = sgx_clksel,
1304         .flags          = CLOCK_IN_OMAP3430ES2,
1305         .clkdm          = { .name = "sgx_clkdm" },
1306         .recalc         = &omap2_clksel_recalc,
1307 };
1308
1309 static struct clk sgx_ick = {
1310         .name           = "sgx_ick",
1311         .parent         = &l3_ick,
1312         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1313         .enable_reg     = CM_ICLKEN,
1314         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1315         .flags          = CLOCK_IN_OMAP3430ES2,
1316         .clkdm          = { .name = "sgx_clkdm" },
1317         .recalc         = &followparent_recalc,
1318 };
1319
1320 /* CORE power domain */
1321
1322 static struct clk d2d_26m_fck = {
1323         .name           = "d2d_26m_fck",
1324         .parent         = &sys_ck,
1325         .prcm_mod       = CORE_MOD,
1326         .enable_reg     = CM_FCLKEN1,
1327         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1328         .flags          = CLOCK_IN_OMAP3430ES1,
1329         .clkdm          = { .name = "d2d_clkdm" },
1330         .recalc         = &followparent_recalc,
1331 };
1332
1333 static const struct clksel omap343x_gpt_clksel[] = {
1334         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1335         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1336         { .parent = NULL}
1337 };
1338
1339 static struct clk gpt10_fck = {
1340         .name           = "gpt10_fck",
1341         .parent         = &sys_ck,
1342         .prcm_mod       = CORE_MOD,
1343         .init           = &omap2_init_clksel_parent,
1344         .enable_reg     = CM_FCLKEN1,
1345         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1346         .idlest_bit     = OMAP3430_ST_GPT10_SHIFT,
1347         .clksel_reg     = CM_CLKSEL,
1348         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1349         .clksel         = omap343x_gpt_clksel,
1350         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1351         .clkdm          = { .name = "core_l4_clkdm" },
1352         .recalc         = &omap2_clksel_recalc,
1353 };
1354
1355 static struct clk gpt11_fck = {
1356         .name           = "gpt11_fck",
1357         .parent         = &sys_ck,
1358         .prcm_mod       = CORE_MOD,
1359         .init           = &omap2_init_clksel_parent,
1360         .enable_reg     = CM_FCLKEN1,
1361         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1362         .idlest_bit     = OMAP3430_ST_GPT11_SHIFT,
1363         .clksel_reg     = CM_CLKSEL,
1364         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1365         .clksel         = omap343x_gpt_clksel,
1366         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1367         .clkdm          = { .name = "core_l4_clkdm" },
1368         .recalc         = &omap2_clksel_recalc,
1369 };
1370
1371 static struct clk cpefuse_fck = {
1372         .name           = "cpefuse_fck",
1373         .parent         = &sys_ck,
1374         .prcm_mod       = CORE_MOD,
1375         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1376         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1377         .idlest_bit     = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1378         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1379         .clkdm          = { .name = "cm_clkdm" },
1380         .recalc         = &followparent_recalc,
1381 };
1382
1383 static struct clk ts_fck = {
1384         .name           = "ts_fck",
1385         .parent         = &omap_32k_fck,
1386         .prcm_mod       = CORE_MOD,
1387         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1388         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1389         .flags          = CLOCK_IN_OMAP3430ES2,
1390         .clkdm          = { .name = "core_l4_clkdm" },
1391         .recalc         = &followparent_recalc,
1392 };
1393
1394 static struct clk usbtll_fck = {
1395         .name           = "usbtll_fck",
1396         .parent         = &dpll5_m2_ck,
1397         .prcm_mod       = CORE_MOD,
1398         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1399         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1400         .idlest_bit     = OMAP3430ES2_ST_USBTLL_SHIFT,
1401         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1402         .clkdm          = { .name = "core_l4_clkdm" },
1403         .recalc         = &followparent_recalc,
1404 };
1405
1406 /* CORE 96M FCLK-derived clocks */
1407
1408 static struct clk core_96m_fck = {
1409         .name           = "core_96m_fck",
1410         .parent         = &omap_96m_fck,
1411         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1412                                 PARENT_CONTROLS_CLOCK,
1413         .clkdm          = { .name = "core_l4_clkdm" },
1414         .recalc         = &followparent_recalc,
1415 };
1416
1417 static struct clk mmchs3_fck = {
1418         .name           = "mmchs_fck",
1419         .id             = 2,
1420         .parent         = &core_96m_fck,
1421         .prcm_mod       = CORE_MOD,
1422         .enable_reg     = CM_FCLKEN1,
1423         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1424         .idlest_bit     = OMAP3430ES2_ST_MMC3_SHIFT,
1425         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1426         .clkdm          = { .name = "core_l4_clkdm" },
1427         .recalc         = &followparent_recalc,
1428 };
1429
1430 static struct clk mmchs2_fck = {
1431         .name           = "mmchs_fck",
1432         .id             = 1,
1433         .parent         = &core_96m_fck,
1434         .prcm_mod       = CORE_MOD,
1435         .enable_reg     = CM_FCLKEN1,
1436         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1437         .idlest_bit     = OMAP3430_ST_MMC2_SHIFT,
1438         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1439         .clkdm          = { .name = "core_l4_clkdm" },
1440         .recalc         = &followparent_recalc,
1441 };
1442
1443 static struct clk mspro_fck = {
1444         .name           = "mspro_fck",
1445         .parent         = &core_96m_fck,
1446         .prcm_mod       = CORE_MOD,
1447         .enable_reg     = CM_FCLKEN1,
1448         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1449         .idlest_bit     = OMAP3430_ST_MSPRO_SHIFT,
1450         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1451         .clkdm          = { .name = "core_l4_clkdm" },
1452         .recalc         = &followparent_recalc,
1453 };
1454
1455 static struct clk mmchs1_fck = {
1456         .name           = "mmchs_fck",
1457         .parent         = &core_96m_fck,
1458         .prcm_mod       = CORE_MOD,
1459         .enable_reg     = CM_FCLKEN1,
1460         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1461         .idlest_bit     = OMAP3430_ST_MMC1_SHIFT,
1462         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1463         .clkdm          = { .name = "core_l4_clkdm" },
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk i2c3_fck = {
1468         .name           = "i2c_fck",
1469         .id             = 3,
1470         .parent         = &core_96m_fck,
1471         .prcm_mod       = CORE_MOD,
1472         .enable_reg     = CM_FCLKEN1,
1473         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1474         .idlest_bit     = OMAP3430_ST_I2C3_SHIFT,
1475         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1476         .clkdm          = { .name = "core_l4_clkdm" },
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 static struct clk i2c2_fck = {
1481         .name           = "i2c_fck",
1482         .id             = 2,
1483         .parent         = &core_96m_fck,
1484         .prcm_mod       = CORE_MOD,
1485         .enable_reg     = CM_FCLKEN1,
1486         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1487         .idlest_bit     = OMAP3430_ST_I2C2_SHIFT,
1488         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1489         .clkdm          = { .name = "core_l4_clkdm" },
1490         .recalc         = &followparent_recalc,
1491 };
1492
1493 static struct clk i2c1_fck = {
1494         .name           = "i2c_fck",
1495         .id             = 1,
1496         .parent         = &core_96m_fck,
1497         .prcm_mod       = CORE_MOD,
1498         .enable_reg     = CM_FCLKEN1,
1499         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1500         .idlest_bit     = OMAP3430_ST_I2C1_SHIFT,
1501         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1502         .clkdm          = { .name = "core_l4_clkdm" },
1503         .recalc         = &followparent_recalc,
1504 };
1505
1506 /*
1507  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1508  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1509  */
1510 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1511         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1512         { .div = 0 }
1513 };
1514
1515 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1516         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1517         { .div = 0 }
1518 };
1519
1520 static const struct clksel mcbsp_15_clksel[] = {
1521         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1522         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1523         { .parent = NULL }
1524 };
1525
1526 static struct clk mcbsp5_src_fck = {
1527         .name           = "mcbsp_src_fck",
1528         .id             = 5,
1529         .prcm_mod       = CLK_REG_IN_SCM,
1530         .init           = &omap2_init_clksel_parent,
1531         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
1532         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1533         .clksel         = mcbsp_15_clksel,
1534         .flags          = CLOCK_IN_OMAP343X,
1535         .clkdm          = { .name = "core_l4_clkdm" },
1536         .recalc         = &omap2_clksel_recalc,
1537 };
1538
1539 static struct clk mcbsp5_fck = {
1540         .name           = "mcbsp_fck",
1541         .id             = 5,
1542         .parent         = &mcbsp5_src_fck,
1543         .prcm_mod       = CORE_MOD,
1544         .enable_reg     = CM_FCLKEN1,
1545         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1546         .idlest_bit     = OMAP3430_ST_MCBSP5_SHIFT,
1547         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1548         .clkdm          = { .name = "core_l4_clkdm" },
1549         .recalc         = &followparent_recalc,
1550 };
1551
1552 static struct clk mcbsp1_src_fck = {
1553         .name           = "mcbsp_src_fck",
1554         .id             = 1,
1555         .prcm_mod       = CLK_REG_IN_SCM,
1556         .init           = &omap2_init_clksel_parent,
1557         .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
1558         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1559         .clksel         = mcbsp_15_clksel,
1560         .flags          = CLOCK_IN_OMAP343X,
1561         .clkdm          = { .name = "core_l4_clkdm" },
1562         .recalc         = &omap2_clksel_recalc,
1563 };
1564
1565 static struct clk mcbsp1_fck = {
1566         .name           = "mcbsp_fck",
1567         .id             = 1,
1568         .parent         = &mcbsp1_src_fck,
1569         .prcm_mod       = CORE_MOD,
1570         .enable_reg     = CM_FCLKEN1,
1571         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1572         .idlest_bit     = OMAP3430_ST_MCBSP1_SHIFT,
1573         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1574         .clkdm          = { .name = "core_l4_clkdm" },
1575         .recalc         = &followparent_recalc,
1576 };
1577
1578 /* CORE_48M_FCK-derived clocks */
1579
1580 static struct clk core_48m_fck = {
1581         .name           = "core_48m_fck",
1582         .parent         = &omap_48m_fck,
1583         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1584                                 PARENT_CONTROLS_CLOCK,
1585         .clkdm          = { .name = "core_l4_clkdm" },
1586         .recalc         = &followparent_recalc,
1587 };
1588
1589 static struct clk mcspi4_fck = {
1590         .name           = "mcspi_fck",
1591         .id             = 4,
1592         .parent         = &core_48m_fck,
1593         .prcm_mod       = CORE_MOD,
1594         .enable_reg     = CM_FCLKEN1,
1595         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1596         .idlest_bit     = OMAP3430_ST_MCSPI4_SHIFT,
1597         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1598         .clkdm          = { .name = "core_l4_clkdm" },
1599         .recalc         = &followparent_recalc,
1600 };
1601
1602 static struct clk mcspi3_fck = {
1603         .name           = "mcspi_fck",
1604         .id             = 3,
1605         .parent         = &core_48m_fck,
1606         .prcm_mod       = CORE_MOD,
1607         .enable_reg     = CM_FCLKEN1,
1608         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1609         .idlest_bit     = OMAP3430_ST_MCSPI3_SHIFT,
1610         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1611         .clkdm          = { .name = "core_l4_clkdm" },
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk mcspi2_fck = {
1616         .name           = "mcspi_fck",
1617         .id             = 2,
1618         .parent         = &core_48m_fck,
1619         .prcm_mod       = CORE_MOD,
1620         .enable_reg     = CM_FCLKEN1,
1621         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1622         .idlest_bit     = OMAP3430_ST_MCSPI2_SHIFT,
1623         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1624         .clkdm          = { .name = "core_l4_clkdm" },
1625         .recalc         = &followparent_recalc,
1626 };
1627
1628 static struct clk mcspi1_fck = {
1629         .name           = "mcspi_fck",
1630         .id             = 1,
1631         .parent         = &core_48m_fck,
1632         .prcm_mod       = CORE_MOD,
1633         .enable_reg     = CM_FCLKEN1,
1634         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1635         .idlest_bit     = OMAP3430_ST_MCSPI1_SHIFT,
1636         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1637         .clkdm          = { .name = "core_l4_clkdm" },
1638         .recalc         = &followparent_recalc,
1639 };
1640
1641 static struct clk uart2_fck = {
1642         .name           = "uart2_fck",
1643         .parent         = &core_48m_fck,
1644         .prcm_mod       = CORE_MOD,
1645         .enable_reg     = CM_FCLKEN1,
1646         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1647         .idlest_bit     = OMAP3430_ST_UART2_SHIFT,
1648         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1649         .clkdm          = { .name = "core_l4_clkdm" },
1650         .recalc         = &followparent_recalc,
1651 };
1652
1653 static struct clk uart1_fck = {
1654         .name           = "uart1_fck",
1655         .parent         = &core_48m_fck,
1656         .prcm_mod       = CORE_MOD,
1657         .enable_reg     = CM_FCLKEN1,
1658         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1659         .idlest_bit     = OMAP3430_ST_UART1_SHIFT,
1660         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1661         .clkdm          = { .name = "core_l4_clkdm" },
1662         .recalc         = &followparent_recalc,
1663 };
1664
1665 /* XXX doublecheck: is this idle or standby? */
1666 static struct clk fshostusb_fck = {
1667         .name           = "fshostusb_fck",
1668         .parent         = &core_48m_fck,
1669         .prcm_mod       = CORE_MOD,
1670         .enable_reg     = CM_FCLKEN1,
1671         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1672         .idlest_bit     = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1673         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1674         .clkdm          = { .name = "core_l4_clkdm" },
1675         .recalc         = &followparent_recalc,
1676 };
1677
1678 /* CORE_12M_FCK based clocks */
1679
1680 static struct clk core_12m_fck = {
1681         .name           = "core_12m_fck",
1682         .parent         = &omap_12m_fck,
1683         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1684                                 PARENT_CONTROLS_CLOCK,
1685         .clkdm          = { .name = "core_l4_clkdm" },
1686         .recalc         = &followparent_recalc,
1687 };
1688
1689 static struct clk hdq_fck = {
1690         .name           = "hdq_fck",
1691         .parent         = &core_12m_fck,
1692         .prcm_mod       = CORE_MOD,
1693         .enable_reg     = CM_FCLKEN1,
1694         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1695         .idlest_bit     = OMAP3430_ST_HDQ_SHIFT,
1696         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1697         .clkdm          = { .name = "core_l4_clkdm" },
1698         .recalc         = &followparent_recalc,
1699 };
1700
1701 /* DPLL3-derived clock */
1702
1703 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1704         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1705         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1706         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1707         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1708         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1709         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1710         { .div = 0 }
1711 };
1712
1713 static const struct clksel ssi_ssr_clksel[] = {
1714         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1715         { .parent = NULL }
1716 };
1717
1718 static struct clk ssi_ssr_fck_3430es1 = {
1719         .name           = "ssi_ssr_fck",
1720         .init           = &omap2_init_clksel_parent,
1721         .prcm_mod       = CORE_MOD,
1722         .enable_reg     = CM_FCLKEN1,
1723         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1724         .clksel_reg     = CM_CLKSEL,
1725         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1726         .clksel         = ssi_ssr_clksel,
1727         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1728         .clkdm          = { .name = "core_l4_clkdm" },
1729         .recalc         = &omap2_clksel_recalc,
1730 };
1731
1732 static struct clk ssi_ssr_fck_3430es2 = {
1733         .name           = "ssi_ssr_fck",
1734         .init           = &omap2_init_clksel_parent,
1735         .prcm_mod       = CORE_MOD,
1736         .enable_reg     = CM_FCLKEN1,
1737         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1738         .idlest_bit     = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1739         .clksel_reg     = CM_CLKSEL,
1740         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1741         .clksel         = ssi_ssr_clksel,
1742         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | WAIT_READY,
1743         .clkdm          = { .name = "core_l4_clkdm" },
1744         .recalc         = &omap2_clksel_recalc,
1745 };
1746
1747 /* It's unfortunate that we need to duplicate this clock. */
1748 static struct clk ssi_sst_fck_3430es1 = {
1749         .name           = "ssi_sst_fck",
1750         .parent         = &ssi_ssr_fck_3430es1,
1751         .fixed_div      = 2,
1752         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1753         .clkdm          = { .name = "core_l4_clkdm" },
1754         .recalc         = &omap2_fixed_divisor_recalc,
1755 };
1756
1757 static struct clk ssi_sst_fck_3430es2 = {
1758         .name           = "ssi_sst_fck",
1759         .parent         = &ssi_ssr_fck_3430es2,
1760         .fixed_div      = 2,
1761         .flags          = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1762         .clkdm          = { .name = "core_l4_clkdm" },
1763         .recalc         = &omap2_fixed_divisor_recalc,
1764 };
1765
1766
1767
1768 /* CORE_L3_ICK based clocks */
1769
1770 /*
1771  * XXX must add clk_enable/clk_disable for these if standard code won't
1772  * handle it
1773  */
1774 static struct clk core_l3_ick = {
1775         .name           = "core_l3_ick",
1776         .parent         = &l3_ick,
1777         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1778                                 PARENT_CONTROLS_CLOCK,
1779         .clkdm          = { .name = "core_l3_clkdm" },
1780         .recalc         = &followparent_recalc,
1781 };
1782
1783 static struct clk hsotgusb_ick_3430es1 = {
1784         .name           = "hsotgusb_ick",
1785         .parent         = &core_l3_ick,
1786         .prcm_mod       = CORE_MOD,
1787         .enable_reg     = CM_ICLKEN1,
1788         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1789         .flags          = CLOCK_IN_OMAP3430ES1,
1790         .clkdm          = { .name = "core_l3_clkdm" },
1791         .recalc         = &followparent_recalc,
1792 };
1793
1794 static struct clk hsotgusb_ick_3430es2 = {
1795         .name           = "hsotgusb_ick",
1796         .parent         = &core_l3_ick,
1797         .prcm_mod       = CORE_MOD,
1798         .enable_reg     = CM_ICLKEN1,
1799         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1800         .idlest_bit     = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1801         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1802         .clkdm          = { .name = "core_l3_clkdm" },
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk sdrc_ick = {
1807         .name           = "sdrc_ick",
1808         .parent         = &core_l3_ick,
1809         .prcm_mod       = CORE_MOD,
1810         .enable_reg     = CM_ICLKEN1,
1811         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1812         .idlest_bit     = OMAP3430_ST_SDRC_SHIFT,
1813         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1814         .clkdm          = { .name = "core_l3_clkdm" },
1815         .recalc         = &followparent_recalc,
1816 };
1817
1818 static struct clk gpmc_fck = {
1819         .name           = "gpmc_fck",
1820         .parent         = &core_l3_ick,
1821         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1822                                 ENABLE_ON_INIT,
1823         .clkdm          = { .name = "core_l3_clkdm" },
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 /* SECURITY_L3_ICK based clocks */
1828
1829 static struct clk security_l3_ick = {
1830         .name           = "security_l3_ick",
1831         .parent         = &l3_ick,
1832         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1833                                 PARENT_CONTROLS_CLOCK,
1834         .clkdm          = { .name = "core_l3_clkdm" },
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk pka_ick = {
1839         .name           = "pka_ick",
1840         .parent         = &security_l3_ick,
1841         .prcm_mod       = CORE_MOD,
1842         .enable_reg     = CM_ICLKEN2,
1843         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1844         .idlest_bit     = OMAP3430_ST_PKA_SHIFT,
1845         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1846         .clkdm          = { .name = "core_l3_clkdm" },
1847         .recalc         = &followparent_recalc,
1848 };
1849
1850 /* CORE_L4_ICK based clocks */
1851
1852 static struct clk core_l4_ick = {
1853         .name           = "core_l4_ick",
1854         .parent         = &l4_ick,
1855         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1856                                 PARENT_CONTROLS_CLOCK,
1857         .clkdm          = { .name = "core_l4_clkdm" },
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 static struct clk usbtll_ick = {
1862         .name           = "usbtll_ick",
1863         .parent         = &core_l4_ick,
1864         .prcm_mod       = CORE_MOD,
1865         .enable_reg     = CM_ICLKEN3,
1866         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1867         .idlest_bit     = OMAP3430ES2_ST_USBTLL_SHIFT,
1868         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1869         .clkdm          = { .name = "core_l4_clkdm" },
1870         .recalc         = &followparent_recalc,
1871 };
1872
1873 static struct clk mmchs3_ick = {
1874         .name           = "mmchs_ick",
1875         .id             = 2,
1876         .parent         = &core_l4_ick,
1877         .prcm_mod       = CORE_MOD,
1878         .enable_reg     = CM_ICLKEN1,
1879         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1880         .idlest_bit     = OMAP3430ES2_ST_MMC3_SHIFT,
1881         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1882         .clkdm          = { .name = "core_l4_clkdm" },
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 /* Intersystem Communication Registers - chassis mode only */
1887 static struct clk icr_ick = {
1888         .name           = "icr_ick",
1889         .parent         = &core_l4_ick,
1890         .prcm_mod       = CORE_MOD,
1891         .enable_reg     = CM_ICLKEN1,
1892         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1893         .idlest_bit     = OMAP3430_ST_ICR_SHIFT,
1894         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1895         .clkdm          = { .name = "core_l4_clkdm" },
1896         .recalc         = &followparent_recalc,
1897 };
1898
1899 static struct clk aes2_ick = {
1900         .name           = "aes2_ick",
1901         .parent         = &core_l4_ick,
1902         .prcm_mod       = CORE_MOD,
1903         .enable_reg     = CM_ICLKEN1,
1904         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1905         .idlest_bit     = OMAP3430_ST_AES2_SHIFT,
1906         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1907         .clkdm          = { .name = "core_l4_clkdm" },
1908         .recalc         = &followparent_recalc,
1909 };
1910
1911 static struct clk sha12_ick = {
1912         .name           = "sha12_ick",
1913         .parent         = &core_l4_ick,
1914         .prcm_mod       = CORE_MOD,
1915         .enable_reg     = CM_ICLKEN1,
1916         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1917         .idlest_bit     = OMAP3430_ST_SHA12_SHIFT,
1918         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1919         .clkdm          = { .name = "core_l4_clkdm" },
1920         .recalc         = &followparent_recalc,
1921 };
1922
1923 static struct clk des2_ick = {
1924         .name           = "des2_ick",
1925         .parent         = &core_l4_ick,
1926         .prcm_mod       = CORE_MOD,
1927         .enable_reg     = CM_ICLKEN1,
1928         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1929         .idlest_bit     = OMAP3430_ST_DES2_SHIFT,
1930         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1931         .clkdm          = { .name = "core_l4_clkdm" },
1932         .recalc         = &followparent_recalc,
1933 };
1934
1935 static struct clk mmchs2_ick = {
1936         .name           = "mmchs_ick",
1937         .id             = 1,
1938         .parent         = &core_l4_ick,
1939         .prcm_mod       = CORE_MOD,
1940         .enable_reg     = CM_ICLKEN1,
1941         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1942         .idlest_bit     = OMAP3430_ST_MMC2_SHIFT,
1943         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1944         .clkdm          = { .name = "core_l4_clkdm" },
1945         .recalc         = &followparent_recalc,
1946 };
1947
1948 static struct clk mmchs1_ick = {
1949         .name           = "mmchs_ick",
1950         .parent         = &core_l4_ick,
1951         .prcm_mod       = CORE_MOD,
1952         .enable_reg     = CM_ICLKEN1,
1953         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1954         .idlest_bit     = OMAP3430_ST_MMC1_SHIFT,
1955         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1956         .clkdm          = { .name = "core_l4_clkdm" },
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk mspro_ick = {
1961         .name           = "mspro_ick",
1962         .parent         = &core_l4_ick,
1963         .prcm_mod       = CORE_MOD,
1964         .enable_reg     = CM_ICLKEN1,
1965         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1966         .idlest_bit     = OMAP3430_ST_MSPRO_SHIFT,
1967         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1968         .clkdm          = { .name = "core_l4_clkdm" },
1969         .recalc         = &followparent_recalc,
1970 };
1971
1972 static struct clk hdq_ick = {
1973         .name           = "hdq_ick",
1974         .parent         = &core_l4_ick,
1975         .prcm_mod       = CORE_MOD,
1976         .enable_reg     = CM_ICLKEN1,
1977         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1978         .idlest_bit     = OMAP3430_ST_HDQ_SHIFT,
1979         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1980         .clkdm          = { .name = "core_l4_clkdm" },
1981         .recalc         = &followparent_recalc,
1982 };
1983
1984 static struct clk mcspi4_ick = {
1985         .name           = "mcspi_ick",
1986         .id             = 4,
1987         .parent         = &core_l4_ick,
1988         .prcm_mod       = CORE_MOD,
1989         .enable_reg     = CM_ICLKEN1,
1990         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1991         .idlest_bit     = OMAP3430_ST_MCSPI4_SHIFT,
1992         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1993         .clkdm          = { .name = "core_l4_clkdm" },
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk mcspi3_ick = {
1998         .name           = "mcspi_ick",
1999         .id             = 3,
2000         .parent         = &core_l4_ick,
2001         .prcm_mod       = CORE_MOD,
2002         .enable_reg     = CM_ICLKEN1,
2003         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2004         .idlest_bit     = OMAP3430_ST_MCSPI3_SHIFT,
2005         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2006         .clkdm          = { .name = "core_l4_clkdm" },
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 static struct clk mcspi2_ick = {
2011         .name           = "mcspi_ick",
2012         .id             = 2,
2013         .parent         = &core_l4_ick,
2014         .prcm_mod       = CORE_MOD,
2015         .enable_reg     = CM_ICLKEN1,
2016         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2017         .idlest_bit     = OMAP3430_ST_MCSPI2_SHIFT,
2018         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2019         .clkdm          = { .name = "core_l4_clkdm" },
2020         .recalc         = &followparent_recalc,
2021 };
2022
2023 static struct clk mcspi1_ick = {
2024         .name           = "mcspi_ick",
2025         .id             = 1,
2026         .parent         = &core_l4_ick,
2027         .prcm_mod       = CORE_MOD,
2028         .enable_reg     = CM_ICLKEN1,
2029         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2030         .idlest_bit     = OMAP3430_ST_MCSPI1_SHIFT,
2031         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2032         .clkdm          = { .name = "core_l4_clkdm" },
2033         .recalc         = &followparent_recalc,
2034 };
2035
2036 static struct clk i2c3_ick = {
2037         .name           = "i2c_ick",
2038         .id             = 3,
2039         .parent         = &core_l4_ick,
2040         .prcm_mod       = CORE_MOD,
2041         .enable_reg     = CM_ICLKEN1,
2042         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
2043         .idlest_bit     = OMAP3430_ST_I2C3_SHIFT,
2044         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2045         .clkdm          = { .name = "core_l4_clkdm" },
2046         .recalc         = &followparent_recalc,
2047 };
2048
2049 static struct clk i2c2_ick = {
2050         .name           = "i2c_ick",
2051         .id             = 2,
2052         .parent         = &core_l4_ick,
2053         .prcm_mod       = CORE_MOD,
2054         .enable_reg     = CM_ICLKEN1,
2055         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2056         .idlest_bit     = OMAP3430_ST_I2C2_SHIFT,
2057         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2058         .clkdm          = { .name = "core_l4_clkdm" },
2059         .recalc         = &followparent_recalc,
2060 };
2061
2062 static struct clk i2c1_ick = {
2063         .name           = "i2c_ick",
2064         .id             = 1,
2065         .parent         = &core_l4_ick,
2066         .prcm_mod       = CORE_MOD,
2067         .enable_reg     = CM_ICLKEN1,
2068         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2069         .idlest_bit     = OMAP3430_ST_I2C1_SHIFT,
2070         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2071         .clkdm          = { .name = "core_l4_clkdm" },
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 static struct clk uart2_ick = {
2076         .name           = "uart2_ick",
2077         .parent         = &core_l4_ick,
2078         .prcm_mod       = CORE_MOD,
2079         .enable_reg     = CM_ICLKEN1,
2080         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2081         .idlest_bit     = OMAP3430_ST_UART2_SHIFT,
2082         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2083         .clkdm          = { .name = "core_l4_clkdm" },
2084         .recalc         = &followparent_recalc,
2085 };
2086
2087 static struct clk uart1_ick = {
2088         .name           = "uart1_ick",
2089         .parent         = &core_l4_ick,
2090         .prcm_mod       = CORE_MOD,
2091         .enable_reg     = CM_ICLKEN1,
2092         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2093         .idlest_bit     = OMAP3430_ST_UART1_SHIFT,
2094         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2095         .clkdm          = { .name = "core_l4_clkdm" },
2096         .recalc         = &followparent_recalc,
2097 };
2098
2099 static struct clk gpt11_ick = {
2100         .name           = "gpt11_ick",
2101         .parent         = &core_l4_ick,
2102         .prcm_mod       = CORE_MOD,
2103         .enable_reg     = CM_ICLKEN1,
2104         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2105         .idlest_bit     = OMAP3430_ST_GPT11_SHIFT,
2106         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2107         .clkdm          = { .name = "core_l4_clkdm" },
2108         .recalc         = &followparent_recalc,
2109 };
2110
2111 static struct clk gpt10_ick = {
2112         .name           = "gpt10_ick",
2113         .parent         = &core_l4_ick,
2114         .prcm_mod       = CORE_MOD,
2115         .enable_reg     = CM_ICLKEN1,
2116         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2117         .idlest_bit     = OMAP3430_ST_GPT10_SHIFT,
2118         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2119         .clkdm          = { .name = "core_l4_clkdm" },
2120         .recalc         = &followparent_recalc,
2121 };
2122
2123 static struct clk mcbsp5_ick = {
2124         .name           = "mcbsp_ick",
2125         .id             = 5,
2126         .parent         = &core_l4_ick,
2127         .prcm_mod       = CORE_MOD,
2128         .enable_reg     = CM_ICLKEN1,
2129         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2130         .idlest_bit     = OMAP3430_ST_MCBSP5_SHIFT,
2131         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2132         .clkdm          = { .name = "core_l4_clkdm" },
2133         .recalc         = &followparent_recalc,
2134 };
2135
2136 static struct clk mcbsp1_ick = {
2137         .name           = "mcbsp_ick",
2138         .id             = 1,
2139         .parent         = &core_l4_ick,
2140         .prcm_mod       = CORE_MOD,
2141         .enable_reg     = CM_ICLKEN1,
2142         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2143         .idlest_bit     = OMAP3430_ST_MCBSP1_SHIFT,
2144         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2145         .clkdm          = { .name = "core_l4_clkdm" },
2146         .recalc         = &followparent_recalc,
2147 };
2148
2149 static struct clk fac_ick = {
2150         .name           = "fac_ick",
2151         .parent         = &core_l4_ick,
2152         .prcm_mod       = CORE_MOD,
2153         .enable_reg     = CM_ICLKEN1,
2154         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2155         .idlest_bit     = OMAP3430ES1_ST_FAC_SHIFT,
2156         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2157         .clkdm          = { .name = "core_l4_clkdm" },
2158         .recalc         = &followparent_recalc,
2159 };
2160
2161 static struct clk mailboxes_ick = {
2162         .name           = "mailboxes_ick",
2163         .parent         = &core_l4_ick,
2164         .prcm_mod       = CORE_MOD,
2165         .enable_reg     = CM_ICLKEN1,
2166         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2167         .idlest_bit     = OMAP3430_ST_MAILBOXES_SHIFT,
2168         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2169         .clkdm          = { .name = "core_l4_clkdm" },
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk omapctrl_ick = {
2174         .name           = "omapctrl_ick",
2175         .parent         = &core_l4_ick,
2176         .prcm_mod       = CORE_MOD,
2177         .enable_reg     = CM_ICLKEN1,
2178         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2179         .idlest_bit     = OMAP3430_ST_OMAPCTRL_SHIFT,
2180         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2181         .clkdm          = { .name = "core_l4_clkdm" },
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 /* SSI_L4_ICK based clocks */
2186
2187 static struct clk ssi_l4_ick = {
2188         .name           = "ssi_l4_ick",
2189         .parent         = &l4_ick,
2190         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2191                                 PARENT_CONTROLS_CLOCK,
2192         .clkdm          = { .name = "core_l4_clkdm" },
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk ssi_ick_3430es1 = {
2197         .name           = "ssi_ick",
2198         .parent         = &ssi_l4_ick,
2199         .prcm_mod       = CORE_MOD,
2200         .enable_reg     = CM_ICLKEN1,
2201         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2202         .flags          = CLOCK_IN_OMAP3430ES1,
2203         .clkdm          = { .name = "core_l4_clkdm" },
2204         .recalc         = &followparent_recalc,
2205 };
2206
2207 static struct clk ssi_ick_3430es2 = {
2208         .name           = "ssi_ick",
2209         .parent         = &ssi_l4_ick,
2210         .prcm_mod       = CORE_MOD,
2211         .enable_reg     = CM_ICLKEN1,
2212         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2213         .idlest_bit     = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2214         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2215         .clkdm          = { .name = "core_l4_clkdm" },
2216         .recalc         = &followparent_recalc,
2217 };
2218
2219 /*
2220  * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2221  * but l4_ick makes more sense to me
2222  */
2223 static const struct clksel usb_l4_clksel[] = {
2224         { .parent = &l4_ick, .rates = div2_rates },
2225         { .parent = NULL },
2226 };
2227
2228 static struct clk usb_l4_ick = {
2229         .name           = "usb_l4_ick",
2230         .parent         = &l4_ick,
2231         .prcm_mod       = CORE_MOD,
2232         .init           = &omap2_init_clksel_parent,
2233         .enable_reg     = CM_ICLKEN1,
2234         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2235         .idlest_bit     = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2236         .clksel_reg     = CM_CLKSEL,
2237         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2238         .clksel         = usb_l4_clksel,
2239         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2240         .clkdm          = { .name = "core_l4_clkdm" },
2241         .recalc         = &omap2_clksel_recalc,
2242 };
2243
2244 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2245
2246 /* SECURITY_L4_ICK2 based clocks */
2247
2248 static struct clk security_l4_ick2 = {
2249         .name           = "security_l4_ick2",
2250         .parent         = &l4_ick,
2251         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2252                                 PARENT_CONTROLS_CLOCK,
2253         .clkdm          = { .name = "core_l4_clkdm" },
2254         .recalc         = &followparent_recalc,
2255 };
2256
2257 static struct clk aes1_ick = {
2258         .name           = "aes1_ick",
2259         .parent         = &security_l4_ick2,
2260         .prcm_mod       = CORE_MOD,
2261         .enable_reg     = CM_ICLKEN2,
2262         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2263         .idlest_bit     = OMAP3430_ST_AES1_SHIFT,
2264         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2265         .clkdm          = { .name = "core_l4_clkdm" },
2266         .recalc         = &followparent_recalc,
2267 };
2268
2269 static struct clk rng_ick = {
2270         .name           = "rng_ick",
2271         .parent         = &security_l4_ick2,
2272         .prcm_mod       = CORE_MOD,
2273         .enable_reg     = CM_ICLKEN2,
2274         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2275         .idlest_bit     = OMAP3430_ST_RNG_SHIFT,
2276         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2277         .clkdm          = { .name = "core_l4_clkdm" },
2278         .recalc         = &followparent_recalc,
2279 };
2280
2281 static struct clk sha11_ick = {
2282         .name           = "sha11_ick",
2283         .parent         = &security_l4_ick2,
2284         .prcm_mod       = CORE_MOD,
2285         .enable_reg     = CM_ICLKEN2,
2286         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2287         .idlest_bit     = OMAP3430_ST_SHA11_SHIFT,
2288         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2289         .clkdm          = { .name = "core_l4_clkdm" },
2290         .recalc         = &followparent_recalc,
2291 };
2292
2293 static struct clk des1_ick = {
2294         .name           = "des1_ick",
2295         .parent         = &security_l4_ick2,
2296         .prcm_mod       = CORE_MOD,
2297         .enable_reg     = CM_ICLKEN2,
2298         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2299         .idlest_bit     = OMAP3430_ST_DES1_SHIFT,
2300         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2301         .clkdm          = { .name = "core_l4_clkdm" },
2302         .recalc         = &followparent_recalc,
2303 };
2304
2305 /* DSS */
2306 static struct clk dss1_alwon_fck_3430es1 = {
2307         .name           = "dss1_alwon_fck",
2308         .parent         = &dpll4_m4x2_ck,
2309         .prcm_mod       = OMAP3430_DSS_MOD,
2310         .enable_reg     = CM_FCLKEN,
2311         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2312         .flags          = CLOCK_IN_OMAP3430ES1,
2313         .clkdm          = { .name = "dss_clkdm" },
2314         .recalc         = &followparent_recalc,
2315 };
2316
2317 static struct clk dss1_alwon_fck_3430es2 = {
2318         .name           = "dss1_alwon_fck",
2319         .parent         = &dpll4_m4x2_ck,
2320         .init           = &omap2_init_clksel_parent,
2321         .prcm_mod       = OMAP3430_DSS_MOD,
2322         .enable_reg     = CM_FCLKEN,
2323         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2324         .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2325         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2326         .clkdm          = { .name = "dss_clkdm" },
2327         .recalc         = &followparent_recalc,
2328 };
2329
2330 static struct clk dss_tv_fck = {
2331         .name           = "dss_tv_fck",
2332         .parent         = &omap_54m_fck,
2333         .prcm_mod       = OMAP3430_DSS_MOD,
2334         .enable_reg     = CM_FCLKEN,
2335         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2336         .flags          = CLOCK_IN_OMAP343X,
2337         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2338         .recalc         = &followparent_recalc,
2339 };
2340
2341 static struct clk dss_96m_fck = {
2342         .name           = "dss_96m_fck",
2343         .parent         = &omap_96m_fck,
2344         .prcm_mod       = OMAP3430_DSS_MOD,
2345         .enable_reg     = CM_FCLKEN,
2346         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2347         .flags          = CLOCK_IN_OMAP343X,
2348         .clkdm          = { .name = "dss_clkdm" },
2349         .recalc         = &followparent_recalc,
2350 };
2351
2352 static struct clk dss2_alwon_fck = {
2353         .name           = "dss2_alwon_fck",
2354         .parent         = &sys_ck,
2355         .prcm_mod       = OMAP3430_DSS_MOD,
2356         .enable_reg     = CM_FCLKEN,
2357         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2358         .flags          = CLOCK_IN_OMAP343X,
2359         .clkdm          = { .name = "dss_clkdm" },
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 static struct clk dss_ick_3430es1 = {
2364         /* Handles both L3 and L4 clocks */
2365         .name           = "dss_ick",
2366         .parent         = &l4_ick,
2367         .prcm_mod       = OMAP3430_DSS_MOD,
2368         .enable_reg     = CM_ICLKEN,
2369         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2370         .flags          = CLOCK_IN_OMAP3430ES1,
2371         .clkdm          = { .name = "dss_clkdm" },
2372         .recalc         = &followparent_recalc,
2373 };
2374
2375 static struct clk dss_ick_3430es2 = {
2376         /* Handles both L3 and L4 clocks */
2377         .name           = "dss_ick",
2378         .parent         = &l4_ick,
2379         .prcm_mod       = OMAP3430_DSS_MOD,
2380         .enable_reg     = CM_ICLKEN,
2381         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2382         .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2383         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2384         .clkdm          = { .name = "dss_clkdm" },
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 /* CAM */
2389
2390 static struct clk cam_mclk = {
2391         .name           = "cam_mclk",
2392         .parent         = &dpll4_m5x2_ck,
2393         .prcm_mod       = OMAP3430_CAM_MOD,
2394         .enable_reg     = CM_FCLKEN,
2395         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2396         .flags          = CLOCK_IN_OMAP343X,
2397         .clkdm          = { .name = "cam_clkdm" },
2398         .recalc         = &followparent_recalc,
2399 };
2400
2401 static struct clk cam_ick = {
2402         /* Handles both L3 and L4 clocks */
2403         .name           = "cam_ick",
2404         .parent         = &l4_ick,
2405         .prcm_mod       = OMAP3430_CAM_MOD,
2406         .enable_reg     = CM_ICLKEN,
2407         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2408         .flags          = CLOCK_IN_OMAP343X,
2409         .clkdm          = { .name = "cam_clkdm" },
2410         .recalc         = &followparent_recalc,
2411 };
2412
2413 static struct clk csi2_96m_fck = {
2414         .name           = "csi2_96m_fck",
2415         .parent         = &core_96m_fck,
2416         .prcm_mod       = OMAP3430_CAM_MOD,
2417         .enable_reg     = CM_FCLKEN,
2418         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2419         .flags          = CLOCK_IN_OMAP343X,
2420         .clkdm          = { .name = "cam_clkdm" },
2421         .recalc         = &followparent_recalc,
2422 };
2423
2424 /* USBHOST - 3430ES2 only */
2425
2426 static struct clk usbhost_120m_fck = {
2427         .name           = "usbhost_120m_fck",
2428         .parent         = &dpll5_m2_ck,
2429         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2430         .enable_reg     = CM_FCLKEN,
2431         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2432         .flags          = CLOCK_IN_OMAP3430ES2,
2433         .clkdm          = { .name = "usbhost_clkdm" },
2434         .recalc         = &followparent_recalc,
2435 };
2436
2437 static struct clk usbhost_48m_fck = {
2438         .name           = "usbhost_48m_fck",
2439         .parent         = &omap_48m_fck,
2440         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2441         .enable_reg     = CM_FCLKEN,
2442         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2443         .idlest_bit     = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2444         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2445         .clkdm          = { .name = "usbhost_clkdm" },
2446         .recalc         = &followparent_recalc,
2447 };
2448
2449 static struct clk usbhost_ick = {
2450         /* Handles both L3 and L4 clocks */
2451         .name           = "usbhost_ick",
2452         .parent         = &l4_ick,
2453         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2454         .enable_reg     = CM_ICLKEN,
2455         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2456         .idlest_bit     = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2457         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2458         .clkdm          = { .name = "usbhost_clkdm" },
2459         .recalc         = &followparent_recalc,
2460 };
2461
2462 /* WKUP */
2463
2464 static const struct clksel_rate usim_96m_rates[] = {
2465         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2466         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2467         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2468         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2469         { .div = 0 },
2470 };
2471
2472 static const struct clksel_rate usim_120m_rates[] = {
2473         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2474         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2475         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2476         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2477         { .div = 0 },
2478 };
2479
2480 static const struct clksel usim_clksel[] = {
2481         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2482         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2483         { .parent = &sys_ck,            .rates = div2_rates },
2484         { .parent = NULL },
2485 };
2486
2487 /* 3430ES2 only */
2488 static struct clk usim_fck = {
2489         .name           = "usim_fck",
2490         .prcm_mod       = WKUP_MOD,
2491         .init           = &omap2_init_clksel_parent,
2492         .enable_reg     = CM_FCLKEN,
2493         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2494         .idlest_bit     = OMAP3430ES2_ST_USIMOCP_SHIFT,
2495         .clksel_reg     = CM_CLKSEL,
2496         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2497         .clksel         = usim_clksel,
2498         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2499         .clkdm          = { .name = "prm_clkdm" },
2500         .recalc         = &omap2_clksel_recalc,
2501 };
2502
2503 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2504 static struct clk gpt1_fck = {
2505         .name           = "gpt1_fck",
2506         .prcm_mod       = WKUP_MOD,
2507         .init           = &omap2_init_clksel_parent,
2508         .enable_reg     = CM_FCLKEN,
2509         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2510         .idlest_bit     = OMAP3430_ST_GPT1_SHIFT,
2511         .clksel_reg     = CM_CLKSEL,
2512         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2513         .clksel         = omap343x_gpt_clksel,
2514         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2515         .clkdm          = { .name = "prm_clkdm" },
2516         .recalc         = &omap2_clksel_recalc,
2517 };
2518
2519 static struct clk wkup_32k_fck = {
2520         .name           = "wkup_32k_fck",
2521         .parent         = &omap_32k_fck,
2522         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2523         .clkdm          = { .name = "prm_clkdm" },
2524         .recalc         = &followparent_recalc,
2525 };
2526
2527 static struct clk gpio1_dbck = {
2528         .name           = "gpio1_dbck",
2529         .parent         = &wkup_32k_fck,
2530         .prcm_mod       = WKUP_MOD,
2531         .enable_reg     = CM_FCLKEN,
2532         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2533         .idlest_bit     = OMAP3430_ST_GPIO1_SHIFT,
2534         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2535         .clkdm          = { .name = "prm_clkdm" },
2536         .recalc         = &followparent_recalc,
2537 };
2538
2539 static struct clk wdt2_fck = {
2540         .name           = "wdt2_fck",
2541         .parent         = &wkup_32k_fck,
2542         .prcm_mod       = WKUP_MOD,
2543         .enable_reg     = CM_FCLKEN,
2544         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2545         .idlest_bit     = OMAP3430_ST_WDT2_SHIFT,
2546         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2547         .clkdm          = { .name = "prm_clkdm" },
2548         .recalc         = &followparent_recalc,
2549 };
2550
2551 static struct clk wkup_l4_ick = {
2552         .name           = "wkup_l4_ick",
2553         .parent         = &sys_ck,
2554         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2555         .clkdm          = { .name = "prm_clkdm" },
2556         .recalc         = &followparent_recalc,
2557 };
2558
2559 static struct clk usim_ick = {
2560         .name           = "usim_ick",
2561         .parent         = &wkup_l4_ick,
2562         .prcm_mod       = WKUP_MOD,
2563         .enable_reg     = CM_ICLKEN,
2564         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2565         .idlest_bit     = OMAP3430ES2_ST_USIMOCP_SHIFT,
2566         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2567         .clkdm          = { .name = "prm_clkdm" },
2568         .recalc         = &followparent_recalc,
2569 };
2570
2571 static struct clk wdt2_ick = {
2572         .name           = "wdt2_ick",
2573         .parent         = &wkup_l4_ick,
2574         .prcm_mod       = WKUP_MOD,
2575         .enable_reg     = CM_ICLKEN,
2576         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2577         .idlest_bit     = OMAP3430_ST_WDT2_SHIFT,
2578         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2579         .clkdm          = { .name = "prm_clkdm" },
2580         .recalc         = &followparent_recalc,
2581 };
2582
2583 static struct clk wdt1_ick = {
2584         .name           = "wdt1_ick",
2585         .parent         = &wkup_l4_ick,
2586         .prcm_mod       = WKUP_MOD,
2587         .enable_reg     = CM_ICLKEN,
2588         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2589         .idlest_bit     = OMAP3430_ST_WDT1_SHIFT,
2590         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2591         .clkdm          = { .name = "prm_clkdm" },
2592         .recalc         = &followparent_recalc,
2593 };
2594
2595 static struct clk gpio1_ick = {
2596         .name           = "gpio1_ick",
2597         .parent         = &wkup_l4_ick,
2598         .prcm_mod       = WKUP_MOD,
2599         .enable_reg     = CM_ICLKEN,
2600         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2601         .idlest_bit     = OMAP3430_ST_GPIO1_SHIFT,
2602         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2603         .clkdm          = { .name = "prm_clkdm" },
2604         .recalc         = &followparent_recalc,
2605 };
2606
2607 static struct clk omap_32ksync_ick = {
2608         .name           = "omap_32ksync_ick",
2609         .parent         = &wkup_l4_ick,
2610         .prcm_mod       = WKUP_MOD,
2611         .enable_reg     = CM_ICLKEN,
2612         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2613         .idlest_bit     = OMAP3430_ST_32KSYNC_SHIFT,
2614         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2615         .clkdm          = { .name = "prm_clkdm" },
2616         .recalc         = &followparent_recalc,
2617 };
2618
2619 static struct clk gpt12_ick = {
2620         .name           = "gpt12_ick",
2621         .parent         = &wkup_l4_ick,
2622         .prcm_mod       = WKUP_MOD,
2623         .enable_reg     = CM_ICLKEN,
2624         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2625         .idlest_bit     = OMAP3430_ST_GPT12_SHIFT,
2626         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2627         .clkdm          = { .name = "prm_clkdm" },
2628         .recalc         = &followparent_recalc,
2629 };
2630
2631 static struct clk gpt1_ick = {
2632         .name           = "gpt1_ick",
2633         .parent         = &wkup_l4_ick,
2634         .prcm_mod       = WKUP_MOD,
2635         .enable_reg     = CM_ICLKEN,
2636         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2637         .idlest_bit     = OMAP3430_ST_GPT1_SHIFT,
2638         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2639         .clkdm          = { .name = "prm_clkdm" },
2640         .recalc         = &followparent_recalc,
2641 };
2642
2643
2644
2645 /* PER clock domain */
2646
2647 static struct clk per_96m_fck = {
2648         .name           = "per_96m_fck",
2649         .parent         = &omap_96m_alwon_fck,
2650         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2651                                 PARENT_CONTROLS_CLOCK,
2652         .clkdm          = { .name = "per_clkdm" },
2653         .recalc         = &followparent_recalc,
2654 };
2655
2656 static struct clk per_48m_fck = {
2657         .name           = "per_48m_fck",
2658         .parent         = &omap_48m_fck,
2659         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2660                                 PARENT_CONTROLS_CLOCK,
2661         .clkdm          = { .name = "per_clkdm" },
2662         .recalc         = &followparent_recalc,
2663 };
2664
2665 static struct clk uart3_fck = {
2666         .name           = "uart3_fck",
2667         .parent         = &per_48m_fck,
2668         .prcm_mod       = OMAP3430_PER_MOD,
2669         .enable_reg     = CM_FCLKEN,
2670         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2671         .idlest_bit     = OMAP3430_ST_UART3_SHIFT,
2672         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2673         .clkdm          = { .name = "per_clkdm" },
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static struct clk gpt2_fck = {
2678         .name           = "gpt2_fck",
2679         .prcm_mod       = OMAP3430_PER_MOD,
2680         .init           = &omap2_init_clksel_parent,
2681         .enable_reg     = CM_FCLKEN,
2682         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2683         .idlest_bit     = OMAP3430_ST_GPT2_SHIFT,
2684         .clksel_reg     = CM_CLKSEL,
2685         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2686         .clksel         = omap343x_gpt_clksel,
2687         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2688         .clkdm          = { .name = "per_clkdm" },
2689         .recalc         = &omap2_clksel_recalc,
2690 };
2691
2692 static struct clk gpt3_fck = {
2693         .name           = "gpt3_fck",
2694         .prcm_mod       = OMAP3430_PER_MOD,
2695         .init           = &omap2_init_clksel_parent,
2696         .enable_reg     = CM_FCLKEN,
2697         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2698         .idlest_bit     = OMAP3430_ST_GPT3_SHIFT,
2699         .clksel_reg     = CM_CLKSEL,
2700         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2701         .clksel         = omap343x_gpt_clksel,
2702         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2703         .clkdm          = { .name = "per_clkdm" },
2704         .recalc         = &omap2_clksel_recalc,
2705 };
2706
2707 static struct clk gpt4_fck = {
2708         .name           = "gpt4_fck",
2709         .prcm_mod       = OMAP3430_PER_MOD,
2710         .init           = &omap2_init_clksel_parent,
2711         .enable_reg     = CM_FCLKEN,
2712         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2713         .idlest_bit     = OMAP3430_ST_GPT4_SHIFT,
2714         .clksel_reg     = CM_CLKSEL,
2715         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2716         .clksel         = omap343x_gpt_clksel,
2717         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2718         .clkdm          = { .name = "per_clkdm" },
2719         .recalc         = &omap2_clksel_recalc,
2720 };
2721
2722 static struct clk gpt5_fck = {
2723         .name           = "gpt5_fck",
2724         .prcm_mod       = OMAP3430_PER_MOD,
2725         .init           = &omap2_init_clksel_parent,
2726         .enable_reg     = CM_FCLKEN,
2727         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2728         .idlest_bit     = OMAP3430_ST_GPT5_SHIFT,
2729         .clksel_reg     = CM_CLKSEL,
2730         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2731         .clksel         = omap343x_gpt_clksel,
2732         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2733         .clkdm          = { .name = "per_clkdm" },
2734         .recalc         = &omap2_clksel_recalc,
2735 };
2736
2737 static struct clk gpt6_fck = {
2738         .name           = "gpt6_fck",
2739         .prcm_mod       = OMAP3430_PER_MOD,
2740         .init           = &omap2_init_clksel_parent,
2741         .enable_reg     = CM_FCLKEN,
2742         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2743         .idlest_bit     = OMAP3430_ST_GPT6_SHIFT,
2744         .clksel_reg     = CM_CLKSEL,
2745         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2746         .clksel         = omap343x_gpt_clksel,
2747         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2748         .clkdm          = { .name = "per_clkdm" },
2749         .recalc         = &omap2_clksel_recalc,
2750 };
2751
2752 static struct clk gpt7_fck = {
2753         .name           = "gpt7_fck",
2754         .prcm_mod       = OMAP3430_PER_MOD,
2755         .init           = &omap2_init_clksel_parent,
2756         .enable_reg     = CM_FCLKEN,
2757         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2758         .idlest_bit     = OMAP3430_ST_GPT7_SHIFT,
2759         .clksel_reg     = CM_CLKSEL,
2760         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2761         .clksel         = omap343x_gpt_clksel,
2762         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2763         .clkdm          = { .name = "per_clkdm" },
2764         .recalc         = &omap2_clksel_recalc,
2765 };
2766
2767 static struct clk gpt8_fck = {
2768         .name           = "gpt8_fck",
2769         .prcm_mod       = OMAP3430_PER_MOD,
2770         .init           = &omap2_init_clksel_parent,
2771         .enable_reg     = CM_FCLKEN,
2772         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2773         .idlest_bit     = OMAP3430_ST_GPT8_SHIFT,
2774         .clksel_reg     = CM_CLKSEL,
2775         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2776         .clksel         = omap343x_gpt_clksel,
2777         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2778         .clkdm          = { .name = "per_clkdm" },
2779         .recalc         = &omap2_clksel_recalc,
2780 };
2781
2782 static struct clk gpt9_fck = {
2783         .name           = "gpt9_fck",
2784         .prcm_mod       = OMAP3430_PER_MOD,
2785         .init           = &omap2_init_clksel_parent,
2786         .enable_reg     = CM_FCLKEN,
2787         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2788         .idlest_bit     = OMAP3430_ST_GPT9_SHIFT,
2789         .clksel_reg     = CM_CLKSEL,
2790         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2791         .clksel         = omap343x_gpt_clksel,
2792         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2793         .clkdm          = { .name = "per_clkdm" },
2794         .recalc         = &omap2_clksel_recalc,
2795 };
2796
2797 static struct clk per_32k_alwon_fck = {
2798         .name           = "per_32k_alwon_fck",
2799         .parent         = &omap_32k_fck,
2800         .clkdm          = { .name = "per_clkdm" },
2801         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2802         .recalc         = &followparent_recalc,
2803 };
2804
2805 static struct clk gpio6_dbck = {
2806         .name           = "gpio6_dbck",
2807         .parent         = &per_32k_alwon_fck,
2808         .prcm_mod       = OMAP3430_PER_MOD,
2809         .enable_reg     = CM_FCLKEN,
2810         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2811         .idlest_bit     = OMAP3430_ST_GPIO6_SHIFT,
2812         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2813         .clkdm          = { .name = "per_clkdm" },
2814         .recalc         = &followparent_recalc,
2815 };
2816
2817 static struct clk gpio5_dbck = {
2818         .name           = "gpio5_dbck",
2819         .parent         = &per_32k_alwon_fck,
2820         .prcm_mod       = OMAP3430_PER_MOD,
2821         .enable_reg     = CM_FCLKEN,
2822         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2823         .idlest_bit     = OMAP3430_ST_GPIO5_SHIFT,
2824         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2825         .clkdm          = { .name = "per_clkdm" },
2826         .recalc         = &followparent_recalc,
2827 };
2828
2829 static struct clk gpio4_dbck = {
2830         .name           = "gpio4_dbck",
2831         .parent         = &per_32k_alwon_fck,
2832         .prcm_mod       = OMAP3430_PER_MOD,
2833         .enable_reg     = CM_FCLKEN,
2834         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2835         .idlest_bit     = OMAP3430_ST_GPIO4_SHIFT,
2836         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2837         .clkdm          = { .name = "per_clkdm" },
2838         .recalc         = &followparent_recalc,
2839 };
2840
2841 static struct clk gpio3_dbck = {
2842         .name           = "gpio3_dbck",
2843         .parent         = &per_32k_alwon_fck,
2844         .prcm_mod       = OMAP3430_PER_MOD,
2845         .enable_reg     = CM_FCLKEN,
2846         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2847         .idlest_bit     = OMAP3430_ST_GPIO3_SHIFT,
2848         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2849         .clkdm          = { .name = "per_clkdm" },
2850         .recalc         = &followparent_recalc,
2851 };
2852
2853 static struct clk gpio2_dbck = {
2854         .name           = "gpio2_dbck",
2855         .parent         = &per_32k_alwon_fck,
2856         .prcm_mod       = OMAP3430_PER_MOD,
2857         .enable_reg     = CM_FCLKEN,
2858         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2859         .idlest_bit     = OMAP3430_ST_GPIO2_SHIFT,
2860         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2861         .clkdm          = { .name = "per_clkdm" },
2862         .recalc         = &followparent_recalc,
2863 };
2864
2865 static struct clk wdt3_fck = {
2866         .name           = "wdt3_fck",
2867         .parent         = &per_32k_alwon_fck,
2868         .prcm_mod       = OMAP3430_PER_MOD,
2869         .enable_reg     = CM_FCLKEN,
2870         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2871         .idlest_bit     = OMAP3430_ST_WDT3_SHIFT,
2872         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2873         .clkdm          = { .name = "per_clkdm" },
2874         .recalc         = &followparent_recalc,
2875 };
2876
2877 static struct clk per_l4_ick = {
2878         .name           = "per_l4_ick",
2879         .parent         = &l4_ick,
2880         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2881                                 PARENT_CONTROLS_CLOCK,
2882         .clkdm          = { .name = "per_clkdm" },
2883         .recalc         = &followparent_recalc,
2884 };
2885
2886 static struct clk gpio6_ick = {
2887         .name           = "gpio6_ick",
2888         .parent         = &per_l4_ick,
2889         .prcm_mod       = OMAP3430_PER_MOD,
2890         .enable_reg     = CM_ICLKEN,
2891         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2892         .idlest_bit     = OMAP3430_ST_GPIO6_SHIFT,
2893         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2894         .clkdm          = { .name = "per_clkdm" },
2895         .recalc         = &followparent_recalc,
2896 };
2897
2898 static struct clk gpio5_ick = {
2899         .name           = "gpio5_ick",
2900         .parent         = &per_l4_ick,
2901         .prcm_mod       = OMAP3430_PER_MOD,
2902         .enable_reg     = CM_ICLKEN,
2903         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2904         .idlest_bit     = OMAP3430_ST_GPIO5_SHIFT,
2905         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2906         .clkdm          = { .name = "per_clkdm" },
2907         .recalc         = &followparent_recalc,
2908 };
2909
2910 static struct clk gpio4_ick = {
2911         .name           = "gpio4_ick",
2912         .parent         = &per_l4_ick,
2913         .prcm_mod       = OMAP3430_PER_MOD,
2914         .enable_reg     = CM_ICLKEN,
2915         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2916         .idlest_bit     = OMAP3430_ST_GPIO4_SHIFT,
2917         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2918         .clkdm          = { .name = "per_clkdm" },
2919         .recalc         = &followparent_recalc,
2920 };
2921
2922 static struct clk gpio3_ick = {
2923         .name           = "gpio3_ick",
2924         .parent         = &per_l4_ick,
2925         .prcm_mod       = OMAP3430_PER_MOD,
2926         .enable_reg     = CM_ICLKEN,
2927         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2928         .idlest_bit     = OMAP3430_ST_GPIO3_SHIFT,
2929         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2930         .clkdm          = { .name = "per_clkdm" },
2931         .recalc         = &followparent_recalc,
2932 };
2933
2934 static struct clk gpio2_ick = {
2935         .name           = "gpio2_ick",
2936         .parent         = &per_l4_ick,
2937         .prcm_mod       = OMAP3430_PER_MOD,
2938         .enable_reg     = CM_ICLKEN,
2939         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2940         .idlest_bit     = OMAP3430_ST_GPIO2_SHIFT,
2941         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2942         .clkdm          = { .name = "per_clkdm" },
2943         .recalc         = &followparent_recalc,
2944 };
2945
2946 static struct clk wdt3_ick = {
2947         .name           = "wdt3_ick",
2948         .parent         = &per_l4_ick,
2949         .prcm_mod       = OMAP3430_PER_MOD,
2950         .enable_reg     = CM_ICLKEN,
2951         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2952         .idlest_bit     = OMAP3430_ST_WDT3_SHIFT,
2953         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2954         .clkdm          = { .name = "per_clkdm" },
2955         .recalc         = &followparent_recalc,
2956 };
2957
2958 static struct clk uart3_ick = {
2959         .name           = "uart3_ick",
2960         .parent         = &per_l4_ick,
2961         .prcm_mod       = OMAP3430_PER_MOD,
2962         .enable_reg     = CM_ICLKEN,
2963         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2964         .idlest_bit     = OMAP3430_ST_UART3_SHIFT,
2965         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2966         .clkdm          = { .name = "per_clkdm" },
2967         .recalc         = &followparent_recalc,
2968 };
2969
2970 static struct clk gpt9_ick = {
2971         .name           = "gpt9_ick",
2972         .parent         = &per_l4_ick,
2973         .prcm_mod       = OMAP3430_PER_MOD,
2974         .enable_reg     = CM_ICLKEN,
2975         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2976         .idlest_bit     = OMAP3430_ST_GPT9_SHIFT,
2977         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2978         .clkdm          = { .name = "per_clkdm" },
2979         .recalc         = &followparent_recalc,
2980 };
2981
2982 static struct clk gpt8_ick = {
2983         .name           = "gpt8_ick",
2984         .parent         = &per_l4_ick,
2985         .prcm_mod       = OMAP3430_PER_MOD,
2986         .enable_reg     = CM_ICLKEN,
2987         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2988         .idlest_bit     = OMAP3430_ST_GPT8_SHIFT,
2989         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2990         .clkdm          = { .name = "per_clkdm" },
2991         .recalc         = &followparent_recalc,
2992 };
2993
2994 static struct clk gpt7_ick = {
2995         .name           = "gpt7_ick",
2996         .parent         = &per_l4_ick,
2997         .prcm_mod       = OMAP3430_PER_MOD,
2998         .enable_reg     = CM_ICLKEN,
2999         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
3000         .idlest_bit     = OMAP3430_ST_GPT7_SHIFT,
3001         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3002         .clkdm          = { .name = "per_clkdm" },
3003         .recalc         = &followparent_recalc,
3004 };
3005
3006 static struct clk gpt6_ick = {
3007         .name           = "gpt6_ick",
3008         .parent         = &per_l4_ick,
3009         .prcm_mod       = OMAP3430_PER_MOD,
3010         .enable_reg     = CM_ICLKEN,
3011         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
3012         .idlest_bit     = OMAP3430_ST_GPT6_SHIFT,
3013         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3014         .clkdm          = { .name = "per_clkdm" },
3015         .recalc         = &followparent_recalc,
3016 };
3017
3018 static struct clk gpt5_ick = {
3019         .name           = "gpt5_ick",
3020         .parent         = &per_l4_ick,
3021         .prcm_mod       = OMAP3430_PER_MOD,
3022         .enable_reg     = CM_ICLKEN,
3023         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
3024         .idlest_bit     = OMAP3430_ST_GPT5_SHIFT,
3025         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3026         .clkdm          = { .name = "per_clkdm" },
3027         .recalc         = &followparent_recalc,
3028 };
3029
3030 static struct clk gpt4_ick = {
3031         .name           = "gpt4_ick",
3032         .parent         = &per_l4_ick,
3033         .prcm_mod       = OMAP3430_PER_MOD,
3034         .enable_reg     = CM_ICLKEN,
3035         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
3036         .idlest_bit     = OMAP3430_ST_GPT4_SHIFT,
3037         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3038         .clkdm          = { .name = "per_clkdm" },
3039         .recalc         = &followparent_recalc,
3040 };
3041
3042 static struct clk gpt3_ick = {
3043         .name           = "gpt3_ick",
3044         .parent         = &per_l4_ick,
3045         .prcm_mod       = OMAP3430_PER_MOD,
3046         .enable_reg     = CM_ICLKEN,
3047         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
3048         .idlest_bit     = OMAP3430_ST_GPT3_SHIFT,
3049         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3050         .clkdm          = { .name = "per_clkdm" },
3051         .recalc         = &followparent_recalc,
3052 };
3053
3054 static struct clk gpt2_ick = {
3055         .name           = "gpt2_ick",
3056         .parent         = &per_l4_ick,
3057         .prcm_mod       = OMAP3430_PER_MOD,
3058         .enable_reg     = CM_ICLKEN,
3059         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
3060         .idlest_bit     = OMAP3430_ST_GPT2_SHIFT,
3061         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3062         .clkdm          = { .name = "per_clkdm" },
3063         .recalc         = &followparent_recalc,
3064 };
3065
3066 static struct clk mcbsp2_ick = {
3067         .name           = "mcbsp_ick",
3068         .id             = 2,
3069         .parent         = &per_l4_ick,
3070         .prcm_mod       = OMAP3430_PER_MOD,
3071         .enable_reg     = CM_ICLKEN,
3072         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
3073         .idlest_bit     = OMAP3430_ST_MCBSP2_SHIFT,
3074         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3075         .clkdm          = { .name = "per_clkdm" },
3076         .recalc         = &followparent_recalc,
3077 };
3078
3079 static struct clk mcbsp3_ick = {
3080         .name           = "mcbsp_ick",
3081         .id             = 3,
3082         .parent         = &per_l4_ick,
3083         .prcm_mod       = OMAP3430_PER_MOD,
3084         .enable_reg     = CM_ICLKEN,
3085         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
3086         .idlest_bit     = OMAP3430_ST_MCBSP3_SHIFT,
3087         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3088         .clkdm          = { .name = "per_clkdm" },
3089         .recalc         = &followparent_recalc,
3090 };
3091
3092 static struct clk mcbsp4_ick = {
3093         .name           = "mcbsp_ick",
3094         .id             = 4,
3095         .parent         = &per_l4_ick,
3096         .prcm_mod       = OMAP3430_PER_MOD,
3097         .enable_reg     = CM_ICLKEN,
3098         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3099         .idlest_bit     = OMAP3430_ST_MCBSP4_SHIFT,
3100         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3101         .clkdm          = { .name = "per_clkdm" },
3102         .recalc         = &followparent_recalc,
3103 };
3104
3105 static const struct clksel mcbsp_234_clksel[] = {
3106         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3107         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
3108         { .parent = NULL }
3109 };
3110
3111 static struct clk mcbsp2_src_fck = {
3112         .name           = "mcbsp_src_fck",
3113         .id             = 2,
3114         .prcm_mod       = CLK_REG_IN_SCM,
3115         .init           = &omap2_init_clksel_parent,
3116         .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
3117         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
3118         .clksel         = mcbsp_234_clksel,
3119         .flags          = CLOCK_IN_OMAP343X,
3120         .clkdm          = { .name = "per_clkdm" },
3121         .recalc         = &omap2_clksel_recalc,
3122 };
3123
3124 static struct clk mcbsp2_fck = {
3125         .name           = "mcbsp_fck",
3126         .id             = 2,
3127         .parent         = &mcbsp2_src_fck,
3128         .prcm_mod       = OMAP3430_PER_MOD,
3129         .enable_reg     = CM_FCLKEN,
3130         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
3131         .idlest_bit     = OMAP3430_ST_MCBSP2_SHIFT,
3132         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3133         .clkdm          = { .name = "per_clkdm" },
3134         .recalc         = &omap2_clksel_recalc,
3135 };
3136
3137 static struct clk mcbsp3_src_fck = {
3138         .name           = "mcbsp_src_fck",
3139         .id             = 3,
3140         .prcm_mod       = CLK_REG_IN_SCM,
3141         .init           = &omap2_init_clksel_parent,
3142         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
3143         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
3144         .clksel         = mcbsp_234_clksel,
3145         .flags          = CLOCK_IN_OMAP343X,
3146         .clkdm          = { .name = "per_clkdm" },
3147         .recalc         = &omap2_clksel_recalc,
3148 };
3149
3150 static struct clk mcbsp3_fck = {
3151         .name           = "mcbsp_fck",
3152         .id             = 3,
3153         .parent         = &mcbsp3_src_fck,
3154         .prcm_mod       = OMAP3430_PER_MOD,
3155         .enable_reg     = CM_FCLKEN,
3156         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
3157         .idlest_bit     = OMAP3430_ST_MCBSP3_SHIFT,
3158         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3159         .clkdm          = { .name = "per_clkdm" },
3160         .recalc         = &omap2_clksel_recalc,
3161 };
3162
3163 static struct clk mcbsp4_src_fck = {
3164         .name           = "mcbsp_src_fck",
3165         .id             = 4,
3166         .prcm_mod       = CLK_REG_IN_SCM,
3167         .init           = &omap2_init_clksel_parent,
3168         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
3169         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
3170         .clksel         = mcbsp_234_clksel,
3171         .flags          = CLOCK_IN_OMAP343X,
3172         .clkdm          = { .name = "per_clkdm" },
3173         .recalc         = &omap2_clksel_recalc,
3174 };
3175
3176 static struct clk mcbsp4_fck = {
3177         .name           = "mcbsp_fck",
3178         .id             = 4,
3179         .parent         = &mcbsp4_src_fck,
3180         .prcm_mod       = OMAP3430_PER_MOD,
3181         .enable_reg     = CM_FCLKEN,
3182         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3183         .idlest_bit     = OMAP3430_ST_MCBSP4_SHIFT,
3184         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3185         .clkdm          = { .name = "per_clkdm" },
3186         .recalc         = &omap2_clksel_recalc,
3187 };
3188
3189 /* EMU clocks */
3190
3191 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3192
3193 static const struct clksel_rate emu_src_sys_rates[] = {
3194         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3195         { .div = 0 },
3196 };
3197
3198 static const struct clksel_rate emu_src_core_rates[] = {
3199         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3200         { .div = 0 },
3201 };
3202
3203 static const struct clksel_rate emu_src_per_rates[] = {
3204         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3205         { .div = 0 },
3206 };
3207
3208 static const struct clksel_rate emu_src_mpu_rates[] = {
3209         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3210         { .div = 0 },
3211 };
3212
3213 static const struct clksel emu_src_clksel[] = {
3214         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
3215         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3216         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
3217         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
3218         { .parent = NULL },
3219 };
3220
3221 /*
3222  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3223  * to switch the source of some of the EMU clocks.
3224  * XXX Are there CLKEN bits for these EMU clks?
3225  */
3226 static struct clk emu_src_ck = {
3227         .name           = "emu_src_ck",
3228         .prcm_mod       = OMAP3430_EMU_MOD,
3229         .init           = &omap2_init_clksel_parent,
3230         .clksel_reg     = CM_CLKSEL1,
3231         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
3232         .clksel         = emu_src_clksel,
3233         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3234         .clkdm          = { .name = "emu_clkdm" },
3235         .recalc         = &omap2_clksel_recalc,
3236 };
3237
3238 static const struct clksel_rate pclk_emu_rates[] = {
3239         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3240         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3241         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3242         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3243         { .div = 0 },
3244 };
3245
3246 static const struct clksel pclk_emu_clksel[] = {
3247         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3248         { .parent = NULL },
3249 };
3250
3251 static struct clk pclk_fck = {
3252         .name           = "pclk_fck",
3253         .prcm_mod       = OMAP3430_EMU_MOD,
3254         .init           = &omap2_init_clksel_parent,
3255         .clksel_reg     = CM_CLKSEL1,
3256         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3257         .clksel         = pclk_emu_clksel,
3258         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3259         .clkdm          = { .name = "emu_clkdm" },
3260         .recalc         = &omap2_clksel_recalc,
3261 };
3262
3263 static const struct clksel_rate pclkx2_emu_rates[] = {
3264         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3265         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3266         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3267         { .div = 0 },
3268 };
3269
3270 static const struct clksel pclkx2_emu_clksel[] = {
3271         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3272         { .parent = NULL },
3273 };
3274
3275 static struct clk pclkx2_fck = {
3276         .name           = "pclkx2_fck",
3277         .prcm_mod       = OMAP3430_EMU_MOD,
3278         .init           = &omap2_init_clksel_parent,
3279         .clksel_reg     = CM_CLKSEL1,
3280         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3281         .clksel         = pclkx2_emu_clksel,
3282         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3283         .clkdm          = { .name = "emu_clkdm" },
3284         .recalc         = &omap2_clksel_recalc,
3285 };
3286
3287 static const struct clksel atclk_emu_clksel[] = {
3288         { .parent = &emu_src_ck, .rates = div2_rates },
3289         { .parent = NULL },
3290 };
3291
3292 static struct clk atclk_fck = {
3293         .name           = "atclk_fck",
3294         .prcm_mod       = OMAP3430_EMU_MOD,
3295         .init           = &omap2_init_clksel_parent,
3296         .clksel_reg     = CM_CLKSEL1,
3297         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3298         .clksel         = atclk_emu_clksel,
3299         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3300         .clkdm          = { .name = "emu_clkdm" },
3301         .recalc         = &omap2_clksel_recalc,
3302 };
3303
3304 static struct clk traceclk_src_fck = {
3305         .name           = "traceclk_src_fck",
3306         .prcm_mod       = OMAP3430_EMU_MOD,
3307         .init           = &omap2_init_clksel_parent,
3308         .clksel_reg     = CM_CLKSEL1,
3309         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3310         .clksel         = emu_src_clksel,
3311         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3312         .clkdm          = { .name = "emu_clkdm" },
3313         .recalc         = &omap2_clksel_recalc,
3314 };
3315
3316 static const struct clksel_rate traceclk_rates[] = {
3317         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3318         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3319         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3320         { .div = 0 },
3321 };
3322
3323 static const struct clksel traceclk_clksel[] = {
3324         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3325         { .parent = NULL },
3326 };
3327
3328 static struct clk traceclk_fck = {
3329         .name           = "traceclk_fck",
3330         .prcm_mod       = OMAP3430_EMU_MOD,
3331         .init           = &omap2_init_clksel_parent,
3332         .clksel_reg     = CM_CLKSEL1,
3333         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3334         .clksel         = traceclk_clksel,
3335         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3336         .clkdm          = { .name = "emu_clkdm" },
3337         .recalc         = &omap2_clksel_recalc,
3338 };
3339
3340 /* SR clocks */
3341
3342 /* SmartReflex fclk (VDD1) */
3343 static struct clk sr1_fck = {
3344         .name           = "sr1_fck",
3345         .parent         = &sys_ck,
3346         .prcm_mod       = WKUP_MOD,
3347         .enable_reg     = CM_FCLKEN,
3348         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3349         .idlest_bit     = OMAP3430_ST_SR1_SHIFT,
3350         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3351         .clkdm          = { .name = "prm_clkdm" },
3352         .recalc         = &followparent_recalc,
3353 };
3354
3355 /* SmartReflex fclk (VDD2) */
3356 static struct clk sr2_fck = {
3357         .name           = "sr2_fck",
3358         .parent         = &sys_ck,
3359         .prcm_mod       = WKUP_MOD,
3360         .enable_reg     = CM_FCLKEN,
3361         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3362         .idlest_bit     = OMAP3430_ST_SR2_SHIFT,
3363         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3364         .clkdm          = { .name = "prm_clkdm" },
3365         .recalc         = &followparent_recalc,
3366 };
3367
3368 static struct clk sr_l4_ick = {
3369         .name           = "sr_l4_ick",
3370         .parent         = &l4_ick,
3371         .flags          = CLOCK_IN_OMAP343X,
3372         .clkdm          = { .name = "core_l4_clkdm" },
3373         .recalc         = &followparent_recalc,
3374 };
3375
3376 /* SECURE_32K_FCK clocks */
3377
3378 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3379 static struct clk gpt12_fck = {
3380         .name           = "gpt12_fck",
3381         .parent         = &secure_32k_fck,
3382         .idlest_bit     = OMAP3430_ST_GPT12_SHIFT,
3383         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3384         .clkdm          = { .name = "prm_clkdm" },
3385         .recalc         = &followparent_recalc,
3386 };
3387
3388 static struct clk wdt1_fck = {
3389         .name           = "wdt1_fck",
3390         .parent         = &secure_32k_fck,
3391         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3392         .clkdm          = { .name = "prm_clkdm" },
3393         .recalc         = &followparent_recalc,
3394 };
3395
3396 static struct clk *onchip_34xx_clks[] __initdata = {
3397         &omap_32k_fck,
3398         &virt_12m_ck,
3399         &virt_13m_ck,
3400         &virt_16_8m_ck,
3401         &virt_19_2m_ck,
3402         &virt_26m_ck,
3403         &virt_38_4m_ck,
3404         &osc_sys_ck,
3405         &sys_ck,
3406         &sys_altclk,
3407         &mcbsp_clks,
3408         &sys_clkout1,
3409         &dpll1_ck,
3410         &dpll1_x2_ck,
3411         &dpll1_x2m2_ck,
3412         &dpll2_ck,
3413         &dpll2_m2_ck,
3414         &dpll3_ck,
3415         &core_ck,
3416         &dpll3_x2_ck,
3417         &dpll3_m2_ck,
3418         &dpll3_m2x2_ck,
3419         &dpll3_m3_ck,
3420         &dpll3_m3x2_ck,
3421         &emu_core_alwon_ck,
3422         &dpll4_ck,
3423         &dpll4_x2_ck,
3424         &omap_96m_alwon_fck,
3425         &omap_96m_fck,
3426         &cm_96m_fck,
3427         &omap_54m_fck,
3428         &omap_48m_fck,
3429         &omap_12m_fck,
3430         &dpll4_m2_ck,
3431         &dpll4_m2x2_ck,
3432         &dpll4_m3_ck,
3433         &dpll4_m3x2_ck,
3434         &dpll4_m4_ck,
3435         &dpll4_m4x2_ck,
3436         &dpll4_m5_ck,
3437         &dpll4_m5x2_ck,
3438         &dpll4_m6_ck,
3439         &dpll4_m6x2_ck,
3440         &emu_per_alwon_ck,
3441         &dpll5_ck,
3442         &dpll5_m2_ck,
3443         &clkout2_src_ck,
3444         &sys_clkout2,
3445         &corex2_fck,
3446         &dpll1_fck,
3447         &mpu_ck,
3448         &arm_fck,
3449         &emu_mpu_alwon_ck,
3450         &dpll2_fck,
3451         &iva2_ck,
3452         &l3_ick,
3453         &l4_ick,
3454         &rm_ick,
3455         &gfx_l3_ck,
3456         &gfx_l3_fck,
3457         &gfx_l3_ick,
3458         &gfx_cg1_ck,
3459         &gfx_cg2_ck,
3460         &sgx_fck,
3461         &sgx_ick,
3462         &d2d_26m_fck,
3463         &gpt10_fck,
3464         &gpt11_fck,
3465         &cpefuse_fck,
3466         &ts_fck,
3467         &usbtll_fck,
3468         &core_96m_fck,
3469         &mmchs3_fck,
3470         &mmchs2_fck,
3471         &mspro_fck,
3472         &mmchs1_fck,
3473         &i2c3_fck,
3474         &i2c2_fck,
3475         &i2c1_fck,
3476         &mcbsp5_src_fck,
3477         &mcbsp5_fck,
3478         &mcbsp1_src_fck,
3479         &mcbsp1_fck,
3480         &core_48m_fck,
3481         &mcspi4_fck,
3482         &mcspi3_fck,
3483         &mcspi2_fck,
3484         &mcspi1_fck,
3485         &uart2_fck,
3486         &uart1_fck,
3487         &fshostusb_fck,
3488         &core_12m_fck,
3489         &hdq_fck,
3490         &ssi_ssr_fck_3430es1,
3491         &ssi_ssr_fck_3430es2,
3492         &ssi_sst_fck_3430es1,
3493         &ssi_sst_fck_3430es2,
3494         &core_l3_ick,
3495         &hsotgusb_ick_3430es1,
3496         &hsotgusb_ick_3430es2,
3497         &sdrc_ick,
3498         &gpmc_fck,
3499         &security_l3_ick,
3500         &pka_ick,
3501         &core_l4_ick,
3502         &usbtll_ick,
3503         &mmchs3_ick,
3504         &icr_ick,
3505         &aes2_ick,
3506         &sha12_ick,
3507         &des2_ick,
3508         &mmchs2_ick,
3509         &mmchs1_ick,
3510         &mspro_ick,
3511         &hdq_ick,
3512         &mcspi4_ick,
3513         &mcspi3_ick,
3514         &mcspi2_ick,
3515         &mcspi1_ick,
3516         &i2c3_ick,
3517         &i2c2_ick,
3518         &i2c1_ick,
3519         &uart2_ick,
3520         &uart1_ick,
3521         &gpt11_ick,
3522         &gpt10_ick,
3523         &mcbsp5_ick,
3524         &mcbsp1_ick,
3525         &fac_ick,
3526         &mailboxes_ick,
3527         &omapctrl_ick,
3528         &ssi_l4_ick,
3529         &ssi_ick_3430es1,
3530         &ssi_ick_3430es2,
3531         &usb_l4_ick,
3532         &security_l4_ick2,
3533         &aes1_ick,
3534         &rng_ick,
3535         &sha11_ick,
3536         &des1_ick,
3537         &dss1_alwon_fck_3430es1,
3538         &dss1_alwon_fck_3430es2,
3539         &dss_tv_fck,
3540         &dss_96m_fck,
3541         &dss2_alwon_fck,
3542         &dss_ick_3430es1,
3543         &dss_ick_3430es2,
3544         &cam_mclk,
3545         &cam_ick,
3546         &csi2_96m_fck,
3547         &usbhost_120m_fck,
3548         &usbhost_48m_fck,
3549         &usbhost_ick,
3550         &usim_fck,
3551         &gpt1_fck,
3552         &wkup_32k_fck,
3553         &gpio1_dbck,
3554         &wdt2_fck,
3555         &wkup_l4_ick,
3556         &usim_ick,
3557         &wdt2_ick,
3558         &wdt1_ick,
3559         &gpio1_ick,
3560         &omap_32ksync_ick,
3561         &gpt12_ick,
3562         &gpt1_ick,
3563         &per_96m_fck,
3564         &per_48m_fck,
3565         &uart3_fck,
3566         &gpt2_fck,
3567         &gpt3_fck,
3568         &gpt4_fck,
3569         &gpt5_fck,
3570         &gpt6_fck,
3571         &gpt7_fck,
3572         &gpt8_fck,
3573         &gpt9_fck,
3574         &per_32k_alwon_fck,
3575         &gpio6_dbck,
3576         &gpio5_dbck,
3577         &gpio4_dbck,
3578         &gpio3_dbck,
3579         &gpio2_dbck,
3580         &wdt3_fck,
3581         &per_l4_ick,
3582         &gpio6_ick,
3583         &gpio5_ick,
3584         &gpio4_ick,
3585         &gpio3_ick,
3586         &gpio2_ick,
3587         &wdt3_ick,
3588         &uart3_ick,
3589         &gpt9_ick,
3590         &gpt8_ick,
3591         &gpt7_ick,
3592         &gpt6_ick,
3593         &gpt5_ick,
3594         &gpt4_ick,
3595         &gpt3_ick,
3596         &gpt2_ick,
3597         &mcbsp2_ick,
3598         &mcbsp3_ick,
3599         &mcbsp4_ick,
3600         &mcbsp2_src_fck,
3601         &mcbsp2_fck,
3602         &mcbsp3_src_fck,
3603         &mcbsp3_fck,
3604         &mcbsp4_src_fck,
3605         &mcbsp4_fck,
3606         &emu_src_ck,
3607         &pclk_fck,
3608         &pclkx2_fck,
3609         &atclk_fck,
3610         &traceclk_src_fck,
3611         &traceclk_fck,
3612         &sr1_fck,
3613         &sr2_fck,
3614         &sr_l4_ick,
3615         &secure_32k_fck,
3616         &gpt12_fck,
3617         &wdt1_fck,
3618 };
3619
3620 #endif