arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35 static int omap3_noncore_dpll_enable(struct clk *clk);
  36 static void omap3_noncore_dpll_disable(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  39
  40 /* Maximum DPLL multiplier, divider values for OMAP3 */
  41 #define OMAP3_MAX_DPLL_MULT             2048
  42 #define OMAP3_MAX_DPLL_DIV              128
  43
  44 /*
  45  * DPLL1 supplies clock to the MPU.
  46  * DPLL2 supplies clock to the IVA2.
  47  * DPLL3 supplies CORE domain clocks.
  48  * DPLL4 supplies peripheral clocks.
  49  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  50  */
  51
  52 /* Forward declarations for DPLL bypass clocks */
  53 static struct clk dpll1_fck;
  54 static struct clk dpll2_fck;
  55
  56 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  57 #define DPLL_LOW_POWER_STOP             0x1
  58 #define DPLL_LOW_POWER_BYPASS           0x5
  59 #define DPLL_LOCKED                     0x7
  60
  61 /* PRM CLOCKS */
  62
  63 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  64 static struct clk omap_32k_fck = {
  65         .name           = "omap_32k_fck",
  66         .rate           = 32768,
  67         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  68                                 ALWAYS_ENABLED,
  69         .clkdm          = { .name = "prm_clkdm" },
  70         .recalc         = &propagate_rate,
  71 };
  72
  73 static struct clk secure_32k_fck = {
  74         .name           = "secure_32k_fck",
  75         .rate           = 32768,
  76         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  77                                 ALWAYS_ENABLED,
  78         .clkdm          = { .name = "prm_clkdm" },
  79         .recalc         = &propagate_rate,
  80 };
  81
  82 /* Virtual source clocks for osc_sys_ck */
  83 static struct clk virt_12m_ck = {
  84         .name           = "virt_12m_ck",
  85         .rate           = 12000000,
  86         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  87                                 ALWAYS_ENABLED,
  88         .clkdm          = { .name = "prm_clkdm" },
  89         .recalc         = &propagate_rate,
  90 };
  91
  92 static struct clk virt_13m_ck = {
  93         .name           = "virt_13m_ck",
  94         .rate           = 13000000,
  95         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  96                                 ALWAYS_ENABLED,
  97         .clkdm          = { .name = "prm_clkdm" },
  98         .recalc         = &propagate_rate,
  99 };
 100
 101 static struct clk virt_16_8m_ck = {
 102         .name           = "virt_16_8m_ck",
 103         .rate           = 16800000,
 104         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
 105                                 ALWAYS_ENABLED,
 106         .clkdm          = { .name = "prm_clkdm" },
 107         .recalc         = &propagate_rate,
 108 };
 109
 110 static struct clk virt_19_2m_ck = {
 111         .name           = "virt_19_2m_ck",
 112         .rate           = 19200000,
 113         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 114                                 ALWAYS_ENABLED,
 115         .clkdm          = { .name = "prm_clkdm" },
 116         .recalc         = &propagate_rate,
 117 };
 118
 119 static struct clk virt_26m_ck = {
 120         .name           = "virt_26m_ck",
 121         .rate           = 26000000,
 122         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 123                                 ALWAYS_ENABLED,
 124         .clkdm          = { .name = "prm_clkdm" },
 125         .recalc         = &propagate_rate,
 126 };
 127
 128 static struct clk virt_38_4m_ck = {
 129         .name           = "virt_38_4m_ck",
 130         .rate           = 38400000,
 131         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 132                                 ALWAYS_ENABLED,
 133         .clkdm          = { .name = "prm_clkdm" },
 134         .recalc         = &propagate_rate,
 135 };
 136
 137 static const struct clksel_rate osc_sys_12m_rates[] = {
 138         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 139         { .div = 0 }
 140 };
 141
 142 static const struct clksel_rate osc_sys_13m_rates[] = {
 143         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 144         { .div = 0 }
 145 };
 146
 147 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 148         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 149         { .div = 0 }
 150 };
 151
 152 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 153         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 154         { .div = 0 }
 155 };
 156
 157 static const struct clksel_rate osc_sys_26m_rates[] = {
 158         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 159         { .div = 0 }
 160 };
 161
 162 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 163         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 164         { .div = 0 }
 165 };
 166
 167 static const struct clksel osc_sys_clksel[] = {
 168         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 169         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 170         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 171         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 172         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 173         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 174         { .parent = NULL },
 175 };
 176
 177 /* Oscillator clock */
 178 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 179 static struct clk osc_sys_ck = {
 180         .name           = "osc_sys_ck",
 181         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 182         .init           = &omap2_init_clksel_parent,
 183         .clksel_reg     = OMAP3_PRM_CLKSEL_OFFSET,
 184         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 185         .clksel         = osc_sys_clksel,
 186         /* REVISIT: deal with autoextclkmode? */
 187         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 188                                 ALWAYS_ENABLED,
 189         .clkdm          = { .name = "prm_clkdm" },
 190         .recalc         = &omap2_clksel_recalc,
 191 };
 192
 193 static const struct clksel_rate div2_rates[] = {
 194         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 195         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 196         { .div = 0 }
 197 };
 198
 199 static const struct clksel sys_clksel[] = {
 200         { .parent = &osc_sys_ck, .rates = div2_rates },
 201         { .parent = NULL }
 202 };
 203
 204 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 205 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 206 static struct clk sys_ck = {
 207         .name           = "sys_ck",
 208         .parent         = &osc_sys_ck,
 209         .prcm_mod       = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
 210         .init           = &omap2_init_clksel_parent,
 211         .clksel_reg     = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
 212         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 213         .clksel         = sys_clksel,
 214         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 215         .clkdm          = { .name = "prm_clkdm" },
 216         .recalc         = &omap2_clksel_recalc,
 217 };
 218
 219 static struct clk sys_altclk = {
 220         .name           = "sys_altclk",
 221         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 222         .clkdm          = { .name = "cm_clkdm" },
 223         .recalc         = &propagate_rate,
 224 };
 225
 226 /*
 227  * Optional external clock input for some McBSPs
 228  * Apparently this is not really in prm_clkdm, but rather is fed into
 229  * both CORE and PER separately.
 230  */
 231 static struct clk mcbsp_clks = {
 232         .name           = "mcbsp_clks",
 233         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 234         .clkdm          = { .name = "prm_clkdm" },
 235         .recalc         = &propagate_rate,
 236 };
 237
 238 /* PRM EXTERNAL CLOCK OUTPUT */
 239
 240 static struct clk sys_clkout1 = {
 241         .name           = "sys_clkout1",
 242         .parent         = &osc_sys_ck,
 243         .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
 244         .enable_reg     = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
 245         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 246         .flags          = CLOCK_IN_OMAP343X,
 247         .clkdm          = { .name = "prm_clkdm" },
 248         .recalc         = &followparent_recalc,
 249 };
 250
 251 /* DPLLS */
 252
 253 /* CM CLOCKS */
 254
 255 static const struct clksel_rate div16_dpll_rates[] = {
 256         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 257         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 258         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 259         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 260         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 261         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 262         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 263         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 264         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 265         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 266         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 267         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 268         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 269         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 270         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 271         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 272         { .div = 0 }
 273 };
 274
 275 /* DPLL1 */
 276 /* MPU clock source */
 277 /* Type: DPLL */
 278 static struct dpll_data dpll1_dd = {
 279         .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
 280         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 281         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 282         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 283         .control_reg    = OMAP3430_CM_CLKEN_PLL,
 284         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 285         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 286         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 287         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 288         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 289         .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
 290         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 291         .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
 292         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 293         .bypass_clk     = &dpll1_fck,
 294         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 295         .max_divider    = OMAP3_MAX_DPLL_DIV,
 296         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 297 };
 298
 299 static struct clk dpll1_ck = {
 300         .name           = "dpll1_ck",
 301         .parent         = &sys_ck,
 302         .prcm_mod       = MPU_MOD,
 303         .dpll_data      = &dpll1_dd,
 304         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 305         .round_rate     = &omap2_dpll_round_rate,
 306         .set_rate       = &omap3_noncore_dpll_set_rate,
 307         .clkdm          = { .name = "dpll1_clkdm" },
 308         .recalc         = &omap3_dpll_recalc,
 309 };
 310
 311 /*
 312  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 313  * DPLL isn't bypassed.
 314  */
 315 static struct clk dpll1_x2_ck = {
 316         .name           = "dpll1_x2_ck",
 317         .parent         = &dpll1_ck,
 318         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 319                                 PARENT_CONTROLS_CLOCK,
 320         .clkdm          = { .name = "dpll1_clkdm" },
 321         .recalc         = &omap3_clkoutx2_recalc,
 322 };
 323
 324 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 325 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 326         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 327         { .parent = NULL }
 328 };
 329
 330 /*
 331  * Does not exist in the TRM - needed to separate the M2 divider from
 332  * bypass selection in mpu_ck
 333  */
 334 static struct clk dpll1_x2m2_ck = {
 335         .name           = "dpll1_x2m2_ck",
 336         .parent         = &dpll1_x2_ck,
 337         .prcm_mod       = MPU_MOD,
 338         .init           = &omap2_init_clksel_parent,
 339         .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
 340         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 341         .clksel         = div16_dpll1_x2m2_clksel,
 342         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 343                                 PARENT_CONTROLS_CLOCK,
 344         .clkdm          = { .name = "dpll1_clkdm" },
 345         .recalc         = &omap2_clksel_recalc,
 346 };
 347
 348 /* DPLL2 */
 349 /* IVA2 clock source */
 350 /* Type: DPLL */
 351
 352 static struct dpll_data dpll2_dd = {
 353         .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
 354         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 355         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 356         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 357         .control_reg    = OMAP3430_CM_CLKEN_PLL,
 358         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 359         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 360                                 (1 << DPLL_LOW_POWER_BYPASS),
 361         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 362         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 363         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 364         .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
 365         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 366         .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
 367         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 368         .bypass_clk     = &dpll2_fck,
 369         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 370         .max_divider    = OMAP3_MAX_DPLL_DIV,
 371         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 372 };
 373
 374 static struct clk dpll2_ck = {
 375         .name           = "dpll2_ck",
 376         .parent         = &sys_ck,
 377         .prcm_mod       = OMAP3430_IVA2_MOD,
 378         .dpll_data      = &dpll2_dd,
 379         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 380         .enable         = &omap3_noncore_dpll_enable,
 381         .disable        = &omap3_noncore_dpll_disable,
 382         .round_rate     = &omap2_dpll_round_rate,
 383         .set_rate       = &omap3_noncore_dpll_set_rate,
 384         .clkdm          = { .name = "dpll2_clkdm" },
 385         .recalc         = &omap3_dpll_recalc,
 386 };
 387
 388 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 389         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 390         { .parent = NULL }
 391 };
 392
 393 /*
 394  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 395  * or CLKOUTX2. CLKOUT seems most plausible.
 396  */
 397 static struct clk dpll2_m2_ck = {
 398         .name           = "dpll2_m2_ck",
 399         .parent         = &dpll2_ck,
 400         .prcm_mod       = OMAP3430_IVA2_MOD,
 401         .init           = &omap2_init_clksel_parent,
 402         .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
 403         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 404         .clksel         = div16_dpll2_m2x2_clksel,
 405         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 406                                 PARENT_CONTROLS_CLOCK,
 407         .clkdm          = { .name = "dpll2_clkdm" },
 408         .recalc         = &omap2_clksel_recalc,
 409 };
 410
 411 /*
 412  * DPLL3
 413  * Source clock for all interfaces and for some device fclks
 414  * REVISIT: Also supports fast relock bypass - not included below
 415  */
 416 static struct dpll_data dpll3_dd = {
 417         .mult_div1_reg  = CM_CLKSEL1,
 418         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 419         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 420         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 421         .control_reg    = CM_CLKEN,
 422         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 423         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 424         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 425         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 426         .autoidle_reg   = CM_AUTOIDLE,
 427         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 428         .idlest_reg     = CM_IDLEST,
 429         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 430         .bypass_clk     = &sys_ck,
 431         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 432         .max_divider    = OMAP3_MAX_DPLL_DIV,
 433         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 434 };
 435
 436 static struct clk dpll3_ck = {
 437         .name           = "dpll3_ck",
 438         .parent         = &sys_ck,
 439         .prcm_mod       = PLL_MOD,
 440         .dpll_data      = &dpll3_dd,
 441         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 442         .round_rate     = &omap2_dpll_round_rate,
 443         .clkdm          = { .name = "dpll3_clkdm" },
 444         .recalc         = &omap3_dpll_recalc,
 445 };
 446
 447 /*
 448  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 449  * DPLL isn't bypassed
 450  */
 451 static struct clk dpll3_x2_ck = {
 452         .name           = "dpll3_x2_ck",
 453         .parent         = &dpll3_ck,
 454         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 455                                 PARENT_CONTROLS_CLOCK,
 456         .clkdm          = { .name = "dpll3_clkdm" },
 457         .recalc         = &omap3_clkoutx2_recalc,
 458 };
 459
 460 static const struct clksel_rate div31_dpll3_rates[] = {
 461         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 462         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 463         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 464         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 465         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 466         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 467         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 468         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 469         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 470         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 471         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 472         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 473         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 474         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 475         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 476         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 477         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 478         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 479         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 480         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 481         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 482         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 483         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 484         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 485         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 486         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 487         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 488         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 489         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 490         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 491         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 492         { .div = 0 },
 493 };
 494
 495 static const struct clksel div31_dpll3m2_clksel[] = {
 496         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 497         { .parent = NULL }
 498 };
 499
 500 /* DPLL3 output M2 - primary control point for CORE speed */
 501 static struct clk dpll3_m2_ck = {
 502         .name           = "dpll3_m2_ck",
 503         .parent         = &dpll3_ck,
 504         .prcm_mod       = PLL_MOD,
 505         .init           = &omap2_init_clksel_parent,
 506         .clksel_reg     = CM_CLKSEL1,
 507         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 508         .clksel         = div31_dpll3m2_clksel,
 509         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 510                                 PARENT_CONTROLS_CLOCK,
 511         .clkdm          = { .name = "dpll3_clkdm" },
 512         .round_rate     = &omap2_clksel_round_rate,
 513         .set_rate       = &omap3_core_dpll_m2_set_rate,
 514         .recalc         = &omap2_clksel_recalc,
 515 };
 516
 517 static struct clk core_ck = {
 518         .name           = "core_ck",
 519         .parent         = &dpll3_m2_ck,
 520         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 521                                 PARENT_CONTROLS_CLOCK,
 522         .clkdm          = { .name = "cm_clkdm" },
 523         .recalc         = &followparent_recalc,
 524 };
 525
 526 static struct clk dpll3_m2x2_ck = {
 527         .name           = "dpll3_m2x2_ck",
 528         .parent         = &dpll3_x2_ck,
 529         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 530                                 PARENT_CONTROLS_CLOCK,
 531         .clkdm          = { .name = "dpll3_clkdm" },
 532         .recalc         = &followparent_recalc,
 533 };
 534
 535 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 536 static const struct clksel div16_dpll3_clksel[] = {
 537         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 538         { .parent = NULL }
 539 };
 540
 541 /* This virtual clock is the source for dpll3_m3x2_ck */
 542 static struct clk dpll3_m3_ck = {
 543         .name           = "dpll3_m3_ck",
 544         .parent         = &dpll3_ck,
 545         .prcm_mod       = OMAP3430_EMU_MOD,
 546         .init           = &omap2_init_clksel_parent,
 547         .clksel_reg     = CM_CLKSEL1,
 548         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 549         .clksel         = div16_dpll3_clksel,
 550         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 551                                 PARENT_CONTROLS_CLOCK,
 552         .clkdm          = { .name = "dpll3_clkdm" },
 553         .recalc         = &omap2_clksel_recalc,
 554 };
 555
 556 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 557 static struct clk dpll3_m3x2_ck = {
 558         .name           = "dpll3_m3x2_ck",
 559         .parent         = &dpll3_m3_ck,
 560         .prcm_mod       = PLL_MOD,
 561         .enable_reg     = CM_CLKEN,
 562         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 563         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 564         .clkdm          = { .name = "dpll3_clkdm" },
 565         .recalc         = &omap3_clkoutx2_recalc,
 566 };
 567
 568 static struct clk emu_core_alwon_ck = {
 569         .name           = "emu_core_alwon_ck",
 570         .parent         = &dpll3_m3x2_ck,
 571         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 572                                 PARENT_CONTROLS_CLOCK,
 573         .clkdm          = { .name = "dpll3_clkdm" },
 574         .recalc         = &followparent_recalc,
 575 };
 576
 577 /* DPLL4 */
 578 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 579 /* Type: DPLL */
 580 static struct dpll_data dpll4_dd = {
 581         .mult_div1_reg  = CM_CLKSEL2,
 582         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 583         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 584         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 585         .control_reg    = CM_CLKEN,
 586         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 587         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 588         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 589         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 590         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 591         .autoidle_reg   = CM_AUTOIDLE,
 592         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 593         .idlest_reg     = CM_IDLEST,
 594         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 595         .bypass_clk     = &sys_ck,
 596         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 597         .max_divider    = OMAP3_MAX_DPLL_DIV,
 598         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 599 };
 600
 601 static struct clk dpll4_ck = {
 602         .name           = "dpll4_ck",
 603         .parent         = &sys_ck,
 604         .prcm_mod       = PLL_MOD,
 605         .dpll_data      = &dpll4_dd,
 606         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 607         .enable         = &omap3_noncore_dpll_enable,
 608         .disable        = &omap3_noncore_dpll_disable,
 609         .round_rate     = &omap2_dpll_round_rate,
 610         .set_rate       = &omap3_noncore_dpll_set_rate,
 611         .clkdm          = { .name = "dpll4_clkdm" },
 612         .recalc         = &omap3_dpll_recalc,
 613 };
 614
 615 /*
 616  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 617  * DPLL isn't bypassed --
 618  * XXX does this serve any downstream clocks?
 619  */
 620 static struct clk dpll4_x2_ck = {
 621         .name           = "dpll4_x2_ck",
 622         .parent         = &dpll4_ck,
 623         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 624                                 PARENT_CONTROLS_CLOCK,
 625         .clkdm          = { .name = "dpll4_clkdm" },
 626         .recalc         = &omap3_clkoutx2_recalc,
 627 };
 628
 629 static const struct clksel div16_dpll4_clksel[] = {
 630         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 631         { .parent = NULL }
 632 };
 633
 634 /* This virtual clock is the source for dpll4_m2x2_ck */
 635 static struct clk dpll4_m2_ck = {
 636         .name           = "dpll4_m2_ck",
 637         .parent         = &dpll4_ck,
 638         .prcm_mod       = PLL_MOD,
 639         .init           = &omap2_init_clksel_parent,
 640         .clksel_reg     = OMAP3430_CM_CLKSEL3,
 641         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 642         .clksel         = div16_dpll4_clksel,
 643         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 644                                 PARENT_CONTROLS_CLOCK,
 645         .clkdm          = { .name = "dpll4_clkdm" },
 646         .recalc         = &omap2_clksel_recalc,
 647 };
 648
 649 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 650 static struct clk dpll4_m2x2_ck = {
 651         .name           = "dpll4_m2x2_ck",
 652         .parent         = &dpll4_m2_ck,
 653         .prcm_mod       = PLL_MOD,
 654         .enable_reg     = CM_CLKEN,
 655         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 656         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 657         .clkdm          = { .name = "dpll4_clkdm" },
 658         .recalc         = &omap3_clkoutx2_recalc,
 659 };
 660
 661 /*
 662  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 663  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 664  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 665  * CM_96K_(F)CLK.
 666  */
 667 static struct clk omap_96m_alwon_fck = {
 668         .name           = "omap_96m_alwon_fck",
 669         .parent         = &dpll4_m2x2_ck,
 670         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 671                                 PARENT_CONTROLS_CLOCK,
 672         .clkdm          = { .name = "prm_clkdm" },
 673         .recalc         = &followparent_recalc,
 674 };
 675
 676 static struct clk cm_96m_fck = {
 677         .name           = "cm_96m_fck",
 678         .parent         = &omap_96m_alwon_fck,
 679         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 680                                 PARENT_CONTROLS_CLOCK,
 681         .clkdm          = { .name = "cm_clkdm" },
 682         .recalc         = &followparent_recalc,
 683 };
 684
 685 static const struct clksel_rate omap_96m_dpll_rates[] = {
 686         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 687         { .div = 0 }
 688 };
 689
 690 static const struct clksel_rate omap_96m_sys_rates[] = {
 691         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 692         { .div = 0 }
 693 };
 694
 695 static const struct clksel omap_96m_fck_clksel[] = {
 696         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 697         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 698         { .parent = NULL }
 699 };
 700
 701 static struct clk omap_96m_fck = {
 702         .name           = "omap_96m_fck",
 703         .parent         = &sys_ck,
 704         .prcm_mod       = PLL_MOD,
 705         .init           = &omap2_init_clksel_parent,
 706         .clksel_reg     = CM_CLKSEL1,
 707         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 708         .clksel         = omap_96m_fck_clksel,
 709         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 710                                 PARENT_CONTROLS_CLOCK,
 711         .clkdm          = { .name = "cm_clkdm" },
 712         .recalc         = &omap2_clksel_recalc,
 713 };
 714
 715 /* This virtual clock is the source for dpll4_m3x2_ck */
 716 static struct clk dpll4_m3_ck = {
 717         .name           = "dpll4_m3_ck",
 718         .parent         = &dpll4_ck,
 719         .prcm_mod       = OMAP3430_DSS_MOD,
 720         .init           = &omap2_init_clksel_parent,
 721         .clksel_reg     = CM_CLKSEL,
 722         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 723         .clksel         = div16_dpll4_clksel,
 724         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 725                                 PARENT_CONTROLS_CLOCK,
 726         .clkdm          = { .name = "dpll4_clkdm" },
 727         .recalc         = &omap2_clksel_recalc,
 728 };
 729
 730 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 731 static struct clk dpll4_m3x2_ck = {
 732         .name           = "dpll4_m3x2_ck",
 733         .parent         = &dpll4_m3_ck,
 734         .prcm_mod       = PLL_MOD,
 735         .init           = &omap2_init_clksel_parent,
 736         .enable_reg     = CM_CLKEN,
 737         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 738         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 739         .clkdm          = { .name = "dpll4_clkdm" },
 740         .recalc         = &omap3_clkoutx2_recalc,
 741 };
 742
 743 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 744         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 745         { .div = 0 }
 746 };
 747
 748 static const struct clksel_rate omap_54m_alt_rates[] = {
 749         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 750         { .div = 0 }
 751 };
 752
 753 static const struct clksel omap_54m_clksel[] = {
 754         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 755         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 756         { .parent = NULL }
 757 };
 758
 759 static struct clk omap_54m_fck = {
 760         .name           = "omap_54m_fck",
 761         .prcm_mod       = PLL_MOD,
 762         .init           = &omap2_init_clksel_parent,
 763         .clksel_reg     = CM_CLKSEL1,
 764         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 765         .clksel         = omap_54m_clksel,
 766         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 767                                 PARENT_CONTROLS_CLOCK,
 768         .clkdm          = { .name = "cm_clkdm" },
 769         .recalc         = &omap2_clksel_recalc,
 770 };
 771
 772 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 773         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 774         { .div = 0 }
 775 };
 776
 777 static const struct clksel_rate omap_48m_alt_rates[] = {
 778         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 779         { .div = 0 }
 780 };
 781
 782 static const struct clksel omap_48m_clksel[] = {
 783         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 784         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 785         { .parent = NULL }
 786 };
 787
 788 static struct clk omap_48m_fck = {
 789         .name           = "omap_48m_fck",
 790         .prcm_mod       = PLL_MOD,
 791         .init           = &omap2_init_clksel_parent,
 792         .clksel_reg     = CM_CLKSEL1,
 793         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 794         .clksel         = omap_48m_clksel,
 795         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 796                                 PARENT_CONTROLS_CLOCK,
 797         .clkdm          = { .name = "cm_clkdm" },
 798         .recalc         = &omap2_clksel_recalc,
 799 };
 800
 801 static struct clk omap_12m_fck = {
 802         .name           = "omap_12m_fck",
 803         .parent         = &omap_48m_fck,
 804         .fixed_div      = 4,
 805         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 806                                 PARENT_CONTROLS_CLOCK,
 807         .clkdm          = { .name = "cm_clkdm" },
 808         .recalc         = &omap2_fixed_divisor_recalc,
 809 };
 810
 811 /* This virstual clock is the source for dpll4_m4x2_ck */
 812 static struct clk dpll4_m4_ck = {
 813         .name           = "dpll4_m4_ck",
 814         .parent         = &dpll4_ck,
 815         .prcm_mod       = OMAP3430_DSS_MOD,
 816         .init           = &omap2_init_clksel_parent,
 817         .clksel_reg     = CM_CLKSEL,
 818         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 819         .clksel         = div16_dpll4_clksel,
 820         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 821                                 PARENT_CONTROLS_CLOCK,
 822         .clkdm          = { .name = "dpll4_clkdm" },
 823         .recalc         = &omap2_clksel_recalc,
 824 };
 825
 826 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 827 static struct clk dpll4_m4x2_ck = {
 828         .name           = "dpll4_m4x2_ck",
 829         .parent         = &dpll4_m4_ck,
 830         .prcm_mod       = PLL_MOD,
 831         .enable_reg     = CM_CLKEN,
 832         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 833         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 834         .clkdm          = { .name = "dpll4_clkdm" },
 835         .recalc         = &omap3_clkoutx2_recalc,
 836 };
 837
 838 /* This virtual clock is the source for dpll4_m5x2_ck */
 839 static struct clk dpll4_m5_ck = {
 840         .name           = "dpll4_m5_ck",
 841         .parent         = &dpll4_ck,
 842         .prcm_mod       = OMAP3430_CAM_MOD,
 843         .init           = &omap2_init_clksel_parent,
 844         .clksel_reg     = CM_CLKSEL,
 845         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 846         .clksel         = div16_dpll4_clksel,
 847         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 848                                 PARENT_CONTROLS_CLOCK,
 849         .clkdm          = { .name = "dpll4_clkdm" },
 850         .recalc         = &omap2_clksel_recalc,
 851 };
 852
 853 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 854 static struct clk dpll4_m5x2_ck = {
 855         .name           = "dpll4_m5x2_ck",
 856         .parent         = &dpll4_m5_ck,
 857         .prcm_mod       = PLL_MOD,
 858         .enable_reg     = CM_CLKEN,
 859         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 860         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 861         .clkdm          = { .name = "dpll4_clkdm" },
 862         .recalc         = &omap3_clkoutx2_recalc,
 863 };
 864
 865 /* This virtual clock is the source for dpll4_m6x2_ck */
 866 static struct clk dpll4_m6_ck = {
 867         .name           = "dpll4_m6_ck",
 868         .parent         = &dpll4_ck,
 869         .prcm_mod       = OMAP3430_EMU_MOD,
 870         .init           = &omap2_init_clksel_parent,
 871         .clksel_reg     = CM_CLKSEL1,
 872         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 873         .clksel         = div16_dpll4_clksel,
 874         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 875                                 PARENT_CONTROLS_CLOCK,
 876         .clkdm          = { .name = "dpll4_clkdm" },
 877         .recalc         = &omap2_clksel_recalc,
 878 };
 879
 880 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 881 static struct clk dpll4_m6x2_ck = {
 882         .name           = "dpll4_m6x2_ck",
 883         .parent         = &dpll4_m6_ck,
 884         .prcm_mod       = PLL_MOD,
 885         .init           = &omap2_init_clksel_parent,
 886         .enable_reg     = CM_CLKEN,
 887         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 888         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 889         .clkdm          = { .name = "dpll4_clkdm" },
 890         .recalc         = &omap3_clkoutx2_recalc,
 891 };
 892
 893 static struct clk emu_per_alwon_ck = {
 894         .name           = "emu_per_alwon_ck",
 895         .parent         = &dpll4_m6x2_ck,
 896         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 897                                 PARENT_CONTROLS_CLOCK,
 898         .clkdm          = { .name = "dpll4_clkdm" },
 899         .recalc         = &followparent_recalc,
 900 };
 901
 902 /* DPLL5 */
 903 /* Supplies 120MHz clock, USIM source clock */
 904 /* Type: DPLL */
 905 /* 3430ES2 only */
 906 static struct dpll_data dpll5_dd = {
 907         .mult_div1_reg  = OMAP3430ES2_CM_CLKSEL4,
 908         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 909         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 910         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 911         .control_reg    = OMAP3430ES2_CM_CLKEN2,
 912         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 913         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 914         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 915         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 916         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 917         .autoidle_reg   = OMAP3430ES2_CM_AUTOIDLE2_PLL,
 918         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 919         .idlest_reg     = CM_IDLEST2,
 920         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 921         .bypass_clk     = &sys_ck,
 922         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 923         .max_divider    = OMAP3_MAX_DPLL_DIV,
 924         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 925 };
 926
 927 static struct clk dpll5_ck = {
 928         .name           = "dpll5_ck",
 929         .parent         = &sys_ck,
 930         .prcm_mod       = PLL_MOD,
 931         .dpll_data      = &dpll5_dd,
 932         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 933         .enable         = &omap3_noncore_dpll_enable,
 934         .disable        = &omap3_noncore_dpll_disable,
 935         .round_rate     = &omap2_dpll_round_rate,
 936         .set_rate       = &omap3_noncore_dpll_set_rate,
 937         .clkdm          = { .name = "dpll5_clkdm" },
 938         .recalc         = &omap3_dpll_recalc,
 939 };
 940
 941 static const struct clksel div16_dpll5_clksel[] = {
 942         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 943         { .parent = NULL }
 944 };
 945
 946 static struct clk dpll5_m2_ck = {
 947         .name           = "dpll5_m2_ck",
 948         .parent         = &dpll5_ck,
 949         .prcm_mod       = PLL_MOD,
 950         .init           = &omap2_init_clksel_parent,
 951         .clksel_reg     = OMAP3430ES2_CM_CLKSEL5,
 952         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 953         .clksel         = div16_dpll5_clksel,
 954         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 955                                 PARENT_CONTROLS_CLOCK,
 956         .clkdm          = { .name = "dpll5_clkdm" },
 957         .recalc         = &omap2_clksel_recalc,
 958 };
 959
 960 /* CM EXTERNAL CLOCK OUTPUTS */
 961
 962 static const struct clksel_rate clkout2_src_core_rates[] = {
 963         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 964         { .div = 0 }
 965 };
 966
 967 static const struct clksel_rate clkout2_src_sys_rates[] = {
 968         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 969         { .div = 0 }
 970 };
 971
 972 static const struct clksel_rate clkout2_src_96m_rates[] = {
 973         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 974         { .div = 0 }
 975 };
 976
 977 static const struct clksel_rate clkout2_src_54m_rates[] = {
 978         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 979         { .div = 0 }
 980 };
 981
 982 static const struct clksel clkout2_src_clksel[] = {
 983         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 984         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 985         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 986         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 987         { .parent = NULL }
 988 };
 989
 990 static struct clk clkout2_src_ck = {
 991         .name           = "clkout2_src_ck",
 992         .prcm_mod       = OMAP3430_CCR_MOD,
 993         .init           = &omap2_init_clksel_parent,
 994         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
 995         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 996         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
 997         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 998         .clksel         = clkout2_src_clksel,
 999         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1000         .clkdm          = { .name = "cm_clkdm" },
1001         .recalc         = &omap2_clksel_recalc,
1002 };
1003
1004 static const struct clksel_rate sys_clkout2_rates[] = {
1005         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1006         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1007         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1008         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1009         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1010         { .div = 0 },
1011 };
1012
1013 static const struct clksel sys_clkout2_clksel[] = {
1014         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1015         { .parent = NULL },
1016 };
1017
1018 static struct clk sys_clkout2 = {
1019         .name           = "sys_clkout2",
1020         .prcm_mod       = OMAP3430_CCR_MOD,
1021         .init           = &omap2_init_clksel_parent,
1022         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
1023         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1024         .clksel         = sys_clkout2_clksel,
1025         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1026         .clkdm          = { .name = "cm_clkdm" },
1027         .recalc         = &omap2_clksel_recalc,
1028 };
1029
1030 /* CM OUTPUT CLOCKS */
1031
1032 static struct clk corex2_fck = {
1033         .name           = "corex2_fck",
1034         .parent         = &dpll3_m2x2_ck,
1035         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1036                                 PARENT_CONTROLS_CLOCK,
1037         .clkdm          = { .name = "cm_clkdm" },
1038         .recalc         = &followparent_recalc,
1039 };
1040
1041 /* DPLL power domain clock controls */
1042
1043 static const struct clksel_rate div4_rates[] = {
1044         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1045         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1046         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1047         { .div = 0 }
1048 };
1049
1050 static const struct clksel div4_core_clksel[] = {
1051         { .parent = &core_ck, .rates = div4_rates },
1052         { .parent = NULL }
1053 };
1054
1055 static struct clk dpll1_fck = {
1056         .name           = "dpll1_fck",
1057         .parent         = &core_ck,
1058         .prcm_mod       = MPU_MOD,
1059         .init           = &omap2_init_clksel_parent,
1060         .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
1061         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1062         .clksel         = div4_core_clksel,
1063         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1064                                 PARENT_CONTROLS_CLOCK,
1065         .clkdm          = { .name = "cm_clkdm" },
1066         .recalc         = &omap2_clksel_recalc,
1067 };
1068
1069 static struct clk mpu_ck = {
1070         .name           = "mpu_ck",
1071         .parent         = &dpll1_x2m2_ck,
1072         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1073                                 PARENT_CONTROLS_CLOCK,
1074         .clkdm          = { .name = "mpu_clkdm" },
1075         .recalc         = &followparent_recalc,
1076 };
1077
1078 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1079 static const struct clksel_rate arm_fck_rates[] = {
1080         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1081         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1082         { .div = 0 },
1083 };
1084
1085 static const struct clksel arm_fck_clksel[] = {
1086         { .parent = &mpu_ck, .rates = arm_fck_rates },
1087         { .parent = NULL }
1088 };
1089
1090 static struct clk arm_fck = {
1091         .name           = "arm_fck",
1092         .parent         = &mpu_ck,
1093         .prcm_mod       = MPU_MOD,
1094         .init           = &omap2_init_clksel_parent,
1095         .clksel_reg     = OMAP3430_CM_IDLEST_PLL,
1096         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1097         .clksel         = arm_fck_clksel,
1098         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1099                                 PARENT_CONTROLS_CLOCK,
1100         .clkdm          = { .name = "mpu_clkdm" },
1101         .recalc         = &omap2_clksel_recalc,
1102 };
1103
1104 /* XXX What about neon_clkdm ? */
1105
1106 /*
1107  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1108  * although it is referenced - so this is a guess
1109  */
1110 static struct clk emu_mpu_alwon_ck = {
1111         .name           = "emu_mpu_alwon_ck",
1112         .parent         = &mpu_ck,
1113         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1114                                 PARENT_CONTROLS_CLOCK,
1115         .clkdm          = { .name = "mpu_clkdm" },
1116         .recalc         = &followparent_recalc,
1117 };
1118
1119 static struct clk dpll2_fck = {
1120         .name           = "dpll2_fck",
1121         .parent         = &core_ck,
1122         .prcm_mod       = OMAP3430_IVA2_MOD,
1123         .init           = &omap2_init_clksel_parent,
1124         .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
1125         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1126         .clksel         = div4_core_clksel,
1127         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1128                                 PARENT_CONTROLS_CLOCK,
1129         .clkdm          = { .name = "cm_clkdm" },
1130         .recalc         = &omap2_clksel_recalc,
1131 };
1132
1133 static struct clk iva2_ck = {
1134         .name           = "iva2_ck",
1135         .parent         = &dpll2_m2_ck,
1136         .prcm_mod       = OMAP3430_IVA2_MOD,
1137         .init           = &omap2_init_clksel_parent,
1138         .enable_reg     = CM_FCLKEN,
1139         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1140         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1141         .clkdm          = { .name = "iva2_clkdm" },
1142         .recalc         = &followparent_recalc,
1143 };
1144
1145 /* Common interface clocks */
1146
1147 static const struct clksel div2_core_clksel[] = {
1148         { .parent = &core_ck, .rates = div2_rates },
1149         { .parent = NULL }
1150 };
1151
1152 static struct clk l3_ick = {
1153         .name           = "l3_ick",
1154         .parent         = &core_ck,
1155         .prcm_mod       = CORE_MOD,
1156         .init           = &omap2_init_clksel_parent,
1157         .clksel_reg     = CM_CLKSEL,
1158         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1159         .clksel         = div2_core_clksel,
1160         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1161                                 PARENT_CONTROLS_CLOCK,
1162         .clkdm          = { .name = "core_l3_clkdm" },
1163         .recalc         = &omap2_clksel_recalc,
1164 };
1165
1166 static const struct clksel div2_l3_clksel[] = {
1167         { .parent = &l3_ick, .rates = div2_rates },
1168         { .parent = NULL }
1169 };
1170
1171 static struct clk l4_ick = {
1172         .name           = "l4_ick",
1173         .parent         = &l3_ick,
1174         .prcm_mod       = CORE_MOD,
1175         .init           = &omap2_init_clksel_parent,
1176         .clksel_reg     = CM_CLKSEL,
1177         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1178         .clksel         = div2_l3_clksel,
1179         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1180                                 PARENT_CONTROLS_CLOCK,
1181         .clkdm          = { .name = "core_l4_clkdm" },
1182         .recalc         = &omap2_clksel_recalc,
1183
1184 };
1185
1186 static const struct clksel div2_l4_clksel[] = {
1187         { .parent = &l4_ick, .rates = div2_rates },
1188         { .parent = NULL }
1189 };
1190
1191 static struct clk rm_ick = {
1192         .name           = "rm_ick",
1193         .parent         = &l4_ick,
1194         .prcm_mod       = WKUP_MOD,
1195         .init           = &omap2_init_clksel_parent,
1196         .clksel_reg     = CM_CLKSEL,
1197         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1198         .clksel         = div2_l4_clksel,
1199         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1200         .clkdm          = { .name = "cm_clkdm" },
1201         .recalc         = &omap2_clksel_recalc,
1202 };
1203
1204 /* GFX power domain */
1205
1206 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1207
1208 static const struct clksel gfx_l3_clksel[] = {
1209         { .parent = &l3_ick, .rates = gfx_l3_rates },
1210         { .parent = NULL }
1211 };
1212
1213 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1214 static struct clk gfx_l3_ck = {
1215         .name           = "gfx_l3_ck",
1216         .parent         = &l3_ick,
1217         .prcm_mod       = GFX_MOD,
1218         .init           = &omap2_init_clksel_parent,
1219         .enable_reg     = CM_ICLKEN,
1220         .enable_bit     = OMAP_EN_GFX_SHIFT,
1221         .flags          = CLOCK_IN_OMAP3430ES1,
1222         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1223         .recalc         = &followparent_recalc,
1224 };
1225
1226 static struct clk gfx_l3_fck = {
1227         .name           = "gfx_l3_fck",
1228         .parent         = &gfx_l3_ck,
1229         .prcm_mod       = GFX_MOD,
1230         .init           = &omap2_init_clksel_parent,
1231         .clksel_reg     = CM_CLKSEL,
1232         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1233         .clksel         = gfx_l3_clksel,
1234         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1235                                 PARENT_CONTROLS_CLOCK,
1236         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1237         .recalc         = &omap2_clksel_recalc,
1238 };
1239
1240 static struct clk gfx_l3_ick = {
1241         .name           = "gfx_l3_ick",
1242         .parent         = &gfx_l3_ck,
1243         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1244         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1245         .recalc         = &followparent_recalc,
1246 };
1247
1248 static struct clk gfx_cg1_ck = {
1249         .name           = "gfx_cg1_ck",
1250         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1251         .prcm_mod       = GFX_MOD,
1252         .enable_reg     = CM_FCLKEN,
1253         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1254         .flags          = CLOCK_IN_OMAP3430ES1,
1255         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1256         .recalc         = &followparent_recalc,
1257 };
1258
1259 static struct clk gfx_cg2_ck = {
1260         .name           = "gfx_cg2_ck",
1261         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1262         .prcm_mod       = GFX_MOD,
1263         .enable_reg     = CM_FCLKEN,
1264         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1265         .flags          = CLOCK_IN_OMAP3430ES1,
1266         .clkdm          = { .name = "gfx_3430es1_clkdm" },
1267         .recalc         = &followparent_recalc,
1268 };
1269
1270 /* SGX power domain - 3430ES2 only */
1271
1272 static const struct clksel_rate sgx_core_rates[] = {
1273         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1274         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1275         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1276         { .div = 0 },
1277 };
1278
1279 static const struct clksel_rate sgx_96m_rates[] = {
1280         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1281         { .div = 0 },
1282 };
1283
1284 static const struct clksel sgx_clksel[] = {
1285         { .parent = &core_ck,    .rates = sgx_core_rates },
1286         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1287         { .parent = NULL },
1288 };
1289
1290 static struct clk sgx_fck = {
1291         .name           = "sgx_fck",
1292         .init           = &omap2_init_clksel_parent,
1293         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1294         .enable_reg     = CM_FCLKEN,
1295         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1296         .clksel_reg     = CM_CLKSEL,
1297         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1298         .clksel         = sgx_clksel,
1299         .flags          = CLOCK_IN_OMAP3430ES2,
1300         .clkdm          = { .name = "sgx_clkdm" },
1301         .recalc         = &omap2_clksel_recalc,
1302 };
1303
1304 static struct clk sgx_ick = {
1305         .name           = "sgx_ick",
1306         .parent         = &l3_ick,
1307         .prcm_mod       = OMAP3430ES2_SGX_MOD,
1308         .enable_reg     = CM_ICLKEN,
1309         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1310         .flags          = CLOCK_IN_OMAP3430ES2,
1311         .clkdm          = { .name = "sgx_clkdm" },
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315 /* CORE power domain */
1316
1317 static struct clk d2d_26m_fck = {
1318         .name           = "d2d_26m_fck",
1319         .parent         = &sys_ck,
1320         .prcm_mod       = CORE_MOD,
1321         .enable_reg     = CM_FCLKEN1,
1322         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1323         .flags          = CLOCK_IN_OMAP3430ES1,
1324         .clkdm          = { .name = "d2d_clkdm" },
1325         .recalc         = &followparent_recalc,
1326 };
1327
1328 static const struct clksel omap343x_gpt_clksel[] = {
1329         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1330         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1331         { .parent = NULL}
1332 };
1333
1334 static struct clk gpt10_fck = {
1335         .name           = "gpt10_fck",
1336         .parent         = &sys_ck,
1337         .prcm_mod       = CORE_MOD,
1338         .init           = &omap2_init_clksel_parent,
1339         .enable_reg     = CM_FCLKEN1,
1340         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1341         .idlest_bit     = OMAP3430_ST_GPT10_SHIFT,
1342         .clksel_reg     = CM_CLKSEL,
1343         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1344         .clksel         = omap343x_gpt_clksel,
1345         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1346         .clkdm          = { .name = "core_l4_clkdm" },
1347         .recalc         = &omap2_clksel_recalc,
1348 };
1349
1350 static struct clk gpt11_fck = {
1351         .name           = "gpt11_fck",
1352         .parent         = &sys_ck,
1353         .prcm_mod       = CORE_MOD,
1354         .init           = &omap2_init_clksel_parent,
1355         .enable_reg     = CM_FCLKEN1,
1356         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1357         .idlest_bit     = OMAP3430_ST_GPT11_SHIFT,
1358         .clksel_reg     = CM_CLKSEL,
1359         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1360         .clksel         = omap343x_gpt_clksel,
1361         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1362         .clkdm          = { .name = "core_l4_clkdm" },
1363         .recalc         = &omap2_clksel_recalc,
1364 };
1365
1366 static struct clk cpefuse_fck = {
1367         .name           = "cpefuse_fck",
1368         .parent         = &sys_ck,
1369         .prcm_mod       = CORE_MOD,
1370         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1371         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1372         .idlest_bit     = OMAP3430ES2_ST_CPEFUSE_SHIFT,
1373         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1374         .clkdm          = { .name = "cm_clkdm" },
1375         .recalc         = &followparent_recalc,
1376 };
1377
1378 static struct clk ts_fck = {
1379         .name           = "ts_fck",
1380         .parent         = &omap_32k_fck,
1381         .prcm_mod       = CORE_MOD,
1382         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1383         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1384         .flags          = CLOCK_IN_OMAP3430ES2,
1385         .clkdm          = { .name = "core_l4_clkdm" },
1386         .recalc         = &followparent_recalc,
1387 };
1388
1389 static struct clk usbtll_fck = {
1390         .name           = "usbtll_fck",
1391         .parent         = &dpll5_m2_ck,
1392         .prcm_mod       = CORE_MOD,
1393         .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
1394         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1395         .idlest_bit     = OMAP3430ES2_ST_USBTLL_SHIFT,
1396         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1397         .clkdm          = { .name = "core_l4_clkdm" },
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 /* CORE 96M FCLK-derived clocks */
1402
1403 static struct clk core_96m_fck = {
1404         .name           = "core_96m_fck",
1405         .parent         = &omap_96m_fck,
1406         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1407                                 PARENT_CONTROLS_CLOCK,
1408         .clkdm          = { .name = "core_l4_clkdm" },
1409         .recalc         = &followparent_recalc,
1410 };
1411
1412 static struct clk mmchs3_fck = {
1413         .name           = "mmchs_fck",
1414         .id             = 2,
1415         .parent         = &core_96m_fck,
1416         .prcm_mod       = CORE_MOD,
1417         .enable_reg     = CM_FCLKEN1,
1418         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1419         .idlest_bit     = OMAP3430ES2_ST_MMC3_SHIFT,
1420         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1421         .clkdm          = { .name = "core_l4_clkdm" },
1422         .recalc         = &followparent_recalc,
1423 };
1424
1425 static struct clk mmchs2_fck = {
1426         .name           = "mmchs_fck",
1427         .id             = 1,
1428         .parent         = &core_96m_fck,
1429         .prcm_mod       = CORE_MOD,
1430         .enable_reg     = CM_FCLKEN1,
1431         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1432         .idlest_bit     = OMAP3430_ST_MMC2_SHIFT,
1433         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1434         .clkdm          = { .name = "core_l4_clkdm" },
1435         .recalc         = &followparent_recalc,
1436 };
1437
1438 static struct clk mspro_fck = {
1439         .name           = "mspro_fck",
1440         .parent         = &core_96m_fck,
1441         .prcm_mod       = CORE_MOD,
1442         .enable_reg     = CM_FCLKEN1,
1443         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1444         .idlest_bit     = OMAP3430_ST_MSPRO_SHIFT,
1445         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1446         .clkdm          = { .name = "core_l4_clkdm" },
1447         .recalc         = &followparent_recalc,
1448 };
1449
1450 static struct clk mmchs1_fck = {
1451         .name           = "mmchs_fck",
1452         .parent         = &core_96m_fck,
1453         .prcm_mod       = CORE_MOD,
1454         .enable_reg     = CM_FCLKEN1,
1455         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1456         .idlest_bit     = OMAP3430_ST_MMC1_SHIFT,
1457         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1458         .clkdm          = { .name = "core_l4_clkdm" },
1459         .recalc         = &followparent_recalc,
1460 };
1461
1462 static struct clk i2c3_fck = {
1463         .name           = "i2c_fck",
1464         .id             = 3,
1465         .parent         = &core_96m_fck,
1466         .prcm_mod       = CORE_MOD,
1467         .enable_reg     = CM_FCLKEN1,
1468         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1469         .idlest_bit     = OMAP3430_ST_I2C3_SHIFT,
1470         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1471         .clkdm          = { .name = "core_l4_clkdm" },
1472         .recalc         = &followparent_recalc,
1473 };
1474
1475 static struct clk i2c2_fck = {
1476         .name           = "i2c_fck",
1477         .id             = 2,
1478         .parent         = &core_96m_fck,
1479         .prcm_mod       = CORE_MOD,
1480         .enable_reg     = CM_FCLKEN1,
1481         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1482         .idlest_bit     = OMAP3430_ST_I2C2_SHIFT,
1483         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1484         .clkdm          = { .name = "core_l4_clkdm" },
1485         .recalc         = &followparent_recalc,
1486 };
1487
1488 static struct clk i2c1_fck = {
1489         .name           = "i2c_fck",
1490         .id             = 1,
1491         .parent         = &core_96m_fck,
1492         .prcm_mod       = CORE_MOD,
1493         .enable_reg     = CM_FCLKEN1,
1494         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1495         .idlest_bit     = OMAP3430_ST_I2C1_SHIFT,
1496         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1497         .clkdm          = { .name = "core_l4_clkdm" },
1498         .recalc         = &followparent_recalc,
1499 };
1500
1501 /*
1502  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1503  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1504  */
1505 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1506         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1507         { .div = 0 }
1508 };
1509
1510 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1511         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1512         { .div = 0 }
1513 };
1514
1515 static const struct clksel mcbsp_15_clksel[] = {
1516         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1517         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1518         { .parent = NULL }
1519 };
1520
1521 static struct clk mcbsp5_src_fck = {
1522         .name           = "mcbsp_src_fck",
1523         .id             = 5,
1524         .prcm_mod       = CLK_REG_IN_SCM,
1525         .init           = &omap2_init_clksel_parent,
1526         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
1527         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1528         .clksel         = mcbsp_15_clksel,
1529         .flags          = CLOCK_IN_OMAP343X,
1530         .clkdm          = { .name = "core_l4_clkdm" },
1531         .recalc         = &omap2_clksel_recalc,
1532 };
1533
1534 static struct clk mcbsp5_fck = {
1535         .name           = "mcbsp_fck",
1536         .id             = 5,
1537         .parent         = &mcbsp5_src_fck,
1538         .prcm_mod       = CORE_MOD,
1539         .enable_reg     = CM_FCLKEN1,
1540         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1541         .idlest_bit     = OMAP3430_ST_MCBSP5_SHIFT,
1542         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1543         .clkdm          = { .name = "core_l4_clkdm" },
1544         .recalc         = &followparent_recalc,
1545 };
1546
1547 static struct clk mcbsp1_src_fck = {
1548         .name           = "mcbsp_src_fck",
1549         .id             = 1,
1550         .prcm_mod       = CLK_REG_IN_SCM,
1551         .init           = &omap2_init_clksel_parent,
1552         .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
1553         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1554         .clksel         = mcbsp_15_clksel,
1555         .flags          = CLOCK_IN_OMAP343X,
1556         .clkdm          = { .name = "core_l4_clkdm" },
1557         .recalc         = &omap2_clksel_recalc,
1558 };
1559
1560 static struct clk mcbsp1_fck = {
1561         .name           = "mcbsp_fck",
1562         .id             = 1,
1563         .parent         = &mcbsp1_src_fck,
1564         .prcm_mod       = CORE_MOD,
1565         .enable_reg     = CM_FCLKEN1,
1566         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1567         .idlest_bit     = OMAP3430_ST_MCBSP1_SHIFT,
1568         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1569         .clkdm          = { .name = "core_l4_clkdm" },
1570         .recalc         = &followparent_recalc,
1571 };
1572
1573 /* CORE_48M_FCK-derived clocks */
1574
1575 static struct clk core_48m_fck = {
1576         .name           = "core_48m_fck",
1577         .parent         = &omap_48m_fck,
1578         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1579                                 PARENT_CONTROLS_CLOCK,
1580         .clkdm          = { .name = "core_l4_clkdm" },
1581         .recalc         = &followparent_recalc,
1582 };
1583
1584 static struct clk mcspi4_fck = {
1585         .name           = "mcspi_fck",
1586         .id             = 4,
1587         .parent         = &core_48m_fck,
1588         .prcm_mod       = CORE_MOD,
1589         .enable_reg     = CM_FCLKEN1,
1590         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1591         .idlest_bit     = OMAP3430_ST_MCSPI4_SHIFT,
1592         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1593         .clkdm          = { .name = "core_l4_clkdm" },
1594         .recalc         = &followparent_recalc,
1595 };
1596
1597 static struct clk mcspi3_fck = {
1598         .name           = "mcspi_fck",
1599         .id             = 3,
1600         .parent         = &core_48m_fck,
1601         .prcm_mod       = CORE_MOD,
1602         .enable_reg     = CM_FCLKEN1,
1603         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1604         .idlest_bit     = OMAP3430_ST_MCSPI3_SHIFT,
1605         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1606         .clkdm          = { .name = "core_l4_clkdm" },
1607         .recalc         = &followparent_recalc,
1608 };
1609
1610 static struct clk mcspi2_fck = {
1611         .name           = "mcspi_fck",
1612         .id             = 2,
1613         .parent         = &core_48m_fck,
1614         .prcm_mod       = CORE_MOD,
1615         .enable_reg     = CM_FCLKEN1,
1616         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1617         .idlest_bit     = OMAP3430_ST_MCSPI2_SHIFT,
1618         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1619         .clkdm          = { .name = "core_l4_clkdm" },
1620         .recalc         = &followparent_recalc,
1621 };
1622
1623 static struct clk mcspi1_fck = {
1624         .name           = "mcspi_fck",
1625         .id             = 1,
1626         .parent         = &core_48m_fck,
1627         .prcm_mod       = CORE_MOD,
1628         .enable_reg     = CM_FCLKEN1,
1629         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1630         .idlest_bit     = OMAP3430_ST_MCSPI1_SHIFT,
1631         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1632         .clkdm          = { .name = "core_l4_clkdm" },
1633         .recalc         = &followparent_recalc,
1634 };
1635
1636 static struct clk uart2_fck = {
1637         .name           = "uart2_fck",
1638         .parent         = &core_48m_fck,
1639         .prcm_mod       = CORE_MOD,
1640         .enable_reg     = CM_FCLKEN1,
1641         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1642         .idlest_bit     = OMAP3430_ST_UART2_SHIFT,
1643         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1644         .clkdm          = { .name = "core_l4_clkdm" },
1645         .recalc         = &followparent_recalc,
1646 };
1647
1648 static struct clk uart1_fck = {
1649         .name           = "uart1_fck",
1650         .parent         = &core_48m_fck,
1651         .prcm_mod       = CORE_MOD,
1652         .enable_reg     = CM_FCLKEN1,
1653         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1654         .idlest_bit     = OMAP3430_ST_UART1_SHIFT,
1655         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1656         .clkdm          = { .name = "core_l4_clkdm" },
1657         .recalc         = &followparent_recalc,
1658 };
1659
1660 /* XXX doublecheck: is this idle or standby? */
1661 static struct clk fshostusb_fck = {
1662         .name           = "fshostusb_fck",
1663         .parent         = &core_48m_fck,
1664         .prcm_mod       = CORE_MOD,
1665         .enable_reg     = CM_FCLKEN1,
1666         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1667         .idlest_bit     = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
1668         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
1669         .clkdm          = { .name = "core_l4_clkdm" },
1670         .recalc         = &followparent_recalc,
1671 };
1672
1673 /* CORE_12M_FCK based clocks */
1674
1675 static struct clk core_12m_fck = {
1676         .name           = "core_12m_fck",
1677         .parent         = &omap_12m_fck,
1678         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1679                                 PARENT_CONTROLS_CLOCK,
1680         .clkdm          = { .name = "core_l4_clkdm" },
1681         .recalc         = &followparent_recalc,
1682 };
1683
1684 static struct clk hdq_fck = {
1685         .name           = "hdq_fck",
1686         .parent         = &core_12m_fck,
1687         .prcm_mod       = CORE_MOD,
1688         .enable_reg     = CM_FCLKEN1,
1689         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1690         .idlest_bit     = OMAP3430_ST_HDQ_SHIFT,
1691         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1692         .clkdm          = { .name = "core_l4_clkdm" },
1693         .recalc         = &followparent_recalc,
1694 };
1695
1696 /* DPLL3-derived clock */
1697
1698 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1699         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1700         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1701         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1702         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1703         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1704         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1705         { .div = 0 }
1706 };
1707
1708 static const struct clksel ssi_ssr_clksel[] = {
1709         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1710         { .parent = NULL }
1711 };
1712
1713 static struct clk ssi_ssr_fck_3430es1 = {
1714         .name           = "ssi_ssr_fck",
1715         .init           = &omap2_init_clksel_parent,
1716         .prcm_mod       = CORE_MOD,
1717         .enable_reg     = CM_FCLKEN1,
1718         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1719         .clksel_reg     = CM_CLKSEL,
1720         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1721         .clksel         = ssi_ssr_clksel,
1722         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1723         .clkdm          = { .name = "core_l4_clkdm" },
1724         .recalc         = &omap2_clksel_recalc,
1725 };
1726
1727 static struct clk ssi_ssr_fck_3430es2 = {
1728         .name           = "ssi_ssr_fck",
1729         .init           = &omap2_init_clksel_parent,
1730         .prcm_mod       = CORE_MOD,
1731         .enable_reg     = CM_FCLKEN1,
1732         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1733         .idlest_bit     = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
1734         .clksel_reg     = CM_CLKSEL,
1735         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1736         .clksel         = ssi_ssr_clksel,
1737         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | WAIT_READY,
1738         .clkdm          = { .name = "core_l4_clkdm" },
1739         .recalc         = &omap2_clksel_recalc,
1740 };
1741
1742 /* It's unfortunate that we need to duplicate this clock. */
1743 static struct clk ssi_sst_fck_3430es1 = {
1744         .name           = "ssi_sst_fck",
1745         .parent         = &ssi_ssr_fck_3430es1,
1746         .fixed_div      = 2,
1747         .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1748         .clkdm          = { .name = "core_l4_clkdm" },
1749         .recalc         = &omap2_fixed_divisor_recalc,
1750 };
1751
1752 static struct clk ssi_sst_fck_3430es2 = {
1753         .name           = "ssi_sst_fck",
1754         .parent         = &ssi_ssr_fck_3430es2,
1755         .fixed_div      = 2,
1756         .flags          = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
1757         .clkdm          = { .name = "core_l4_clkdm" },
1758         .recalc         = &omap2_fixed_divisor_recalc,
1759 };
1760
1761
1762
1763 /* CORE_L3_ICK based clocks */
1764
1765 /*
1766  * XXX must add clk_enable/clk_disable for these if standard code won't
1767  * handle it
1768  */
1769 static struct clk core_l3_ick = {
1770         .name           = "core_l3_ick",
1771         .parent         = &l3_ick,
1772         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1773                                 PARENT_CONTROLS_CLOCK,
1774         .clkdm          = { .name = "core_l3_clkdm" },
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 static struct clk hsotgusb_ick_3430es1 = {
1779         .name           = "hsotgusb_ick",
1780         .parent         = &core_l3_ick,
1781         .prcm_mod       = CORE_MOD,
1782         .enable_reg     = CM_ICLKEN1,
1783         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1784         .flags          = CLOCK_IN_OMAP3430ES1,
1785         .clkdm          = { .name = "core_l3_clkdm" },
1786         .recalc         = &followparent_recalc,
1787 };
1788
1789 static struct clk hsotgusb_ick_3430es2 = {
1790         .name           = "hsotgusb_ick",
1791         .parent         = &core_l3_ick,
1792         .prcm_mod       = CORE_MOD,
1793         .enable_reg     = CM_ICLKEN1,
1794         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1795         .idlest_bit     = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1796         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1797         .clkdm          = { .name = "core_l3_clkdm" },
1798         .recalc         = &followparent_recalc,
1799 };
1800
1801 static struct clk sdrc_ick = {
1802         .name           = "sdrc_ick",
1803         .parent         = &core_l3_ick,
1804         .prcm_mod       = CORE_MOD,
1805         .enable_reg     = CM_ICLKEN1,
1806         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1807         .idlest_bit     = OMAP3430_ST_SDRC_SHIFT,
1808         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
1809         .clkdm          = { .name = "core_l3_clkdm" },
1810         .recalc         = &followparent_recalc,
1811 };
1812
1813 static struct clk gpmc_fck = {
1814         .name           = "gpmc_fck",
1815         .parent         = &core_l3_ick,
1816         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1817                                 ENABLE_ON_INIT,
1818         .clkdm          = { .name = "core_l3_clkdm" },
1819         .recalc         = &followparent_recalc,
1820 };
1821
1822 /* SECURITY_L3_ICK based clocks */
1823
1824 static struct clk security_l3_ick = {
1825         .name           = "security_l3_ick",
1826         .parent         = &l3_ick,
1827         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1828                                 PARENT_CONTROLS_CLOCK,
1829         .clkdm          = { .name = "core_l3_clkdm" },
1830         .recalc         = &followparent_recalc,
1831 };
1832
1833 static struct clk pka_ick = {
1834         .name           = "pka_ick",
1835         .parent         = &security_l3_ick,
1836         .prcm_mod       = CORE_MOD,
1837         .enable_reg     = CM_ICLKEN2,
1838         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1839         .idlest_bit     = OMAP3430_ST_PKA_SHIFT,
1840         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1841         .clkdm          = { .name = "core_l3_clkdm" },
1842         .recalc         = &followparent_recalc,
1843 };
1844
1845 /* CORE_L4_ICK based clocks */
1846
1847 static struct clk core_l4_ick = {
1848         .name           = "core_l4_ick",
1849         .parent         = &l4_ick,
1850         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1851                                 PARENT_CONTROLS_CLOCK,
1852         .clkdm          = { .name = "core_l4_clkdm" },
1853         .recalc         = &followparent_recalc,
1854 };
1855
1856 static struct clk usbtll_ick = {
1857         .name           = "usbtll_ick",
1858         .parent         = &core_l4_ick,
1859         .prcm_mod       = CORE_MOD,
1860         .enable_reg     = CM_ICLKEN3,
1861         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1862         .idlest_bit     = OMAP3430ES2_ST_USBTLL_SHIFT,
1863         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1864         .clkdm          = { .name = "core_l4_clkdm" },
1865         .recalc         = &followparent_recalc,
1866 };
1867
1868 static struct clk mmchs3_ick = {
1869         .name           = "mmchs_ick",
1870         .id             = 2,
1871         .parent         = &core_l4_ick,
1872         .prcm_mod       = CORE_MOD,
1873         .enable_reg     = CM_ICLKEN1,
1874         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1875         .idlest_bit     = OMAP3430ES2_ST_MMC3_SHIFT,
1876         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
1877         .clkdm          = { .name = "core_l4_clkdm" },
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 /* Intersystem Communication Registers - chassis mode only */
1882 static struct clk icr_ick = {
1883         .name           = "icr_ick",
1884         .parent         = &core_l4_ick,
1885         .prcm_mod       = CORE_MOD,
1886         .enable_reg     = CM_ICLKEN1,
1887         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1888         .idlest_bit     = OMAP3430_ST_ICR_SHIFT,
1889         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1890         .clkdm          = { .name = "core_l4_clkdm" },
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk aes2_ick = {
1895         .name           = "aes2_ick",
1896         .parent         = &core_l4_ick,
1897         .prcm_mod       = CORE_MOD,
1898         .enable_reg     = CM_ICLKEN1,
1899         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1900         .idlest_bit     = OMAP3430_ST_AES2_SHIFT,
1901         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1902         .clkdm          = { .name = "core_l4_clkdm" },
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk sha12_ick = {
1907         .name           = "sha12_ick",
1908         .parent         = &core_l4_ick,
1909         .prcm_mod       = CORE_MOD,
1910         .enable_reg     = CM_ICLKEN1,
1911         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1912         .idlest_bit     = OMAP3430_ST_SHA12_SHIFT,
1913         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1914         .clkdm          = { .name = "core_l4_clkdm" },
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk des2_ick = {
1919         .name           = "des2_ick",
1920         .parent         = &core_l4_ick,
1921         .prcm_mod       = CORE_MOD,
1922         .enable_reg     = CM_ICLKEN1,
1923         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1924         .idlest_bit     = OMAP3430_ST_DES2_SHIFT,
1925         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1926         .clkdm          = { .name = "core_l4_clkdm" },
1927         .recalc         = &followparent_recalc,
1928 };
1929
1930 static struct clk mmchs2_ick = {
1931         .name           = "mmchs_ick",
1932         .id             = 1,
1933         .parent         = &core_l4_ick,
1934         .prcm_mod       = CORE_MOD,
1935         .enable_reg     = CM_ICLKEN1,
1936         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1937         .idlest_bit     = OMAP3430_ST_MMC2_SHIFT,
1938         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1939         .clkdm          = { .name = "core_l4_clkdm" },
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk mmchs1_ick = {
1944         .name           = "mmchs_ick",
1945         .parent         = &core_l4_ick,
1946         .prcm_mod       = CORE_MOD,
1947         .enable_reg     = CM_ICLKEN1,
1948         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1949         .idlest_bit     = OMAP3430_ST_MMC1_SHIFT,
1950         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1951         .clkdm          = { .name = "core_l4_clkdm" },
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk mspro_ick = {
1956         .name           = "mspro_ick",
1957         .parent         = &core_l4_ick,
1958         .prcm_mod       = CORE_MOD,
1959         .enable_reg     = CM_ICLKEN1,
1960         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1961         .idlest_bit     = OMAP3430_ST_MSPRO_SHIFT,
1962         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1963         .clkdm          = { .name = "core_l4_clkdm" },
1964         .recalc         = &followparent_recalc,
1965 };
1966
1967 static struct clk hdq_ick = {
1968         .name           = "hdq_ick",
1969         .parent         = &core_l4_ick,
1970         .prcm_mod       = CORE_MOD,
1971         .enable_reg     = CM_ICLKEN1,
1972         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1973         .idlest_bit     = OMAP3430_ST_HDQ_SHIFT,
1974         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1975         .clkdm          = { .name = "core_l4_clkdm" },
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk mcspi4_ick = {
1980         .name           = "mcspi_ick",
1981         .id             = 4,
1982         .parent         = &core_l4_ick,
1983         .prcm_mod       = CORE_MOD,
1984         .enable_reg     = CM_ICLKEN1,
1985         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1986         .idlest_bit     = OMAP3430_ST_MCSPI4_SHIFT,
1987         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
1988         .clkdm          = { .name = "core_l4_clkdm" },
1989         .recalc         = &followparent_recalc,
1990 };
1991
1992 static struct clk mcspi3_ick = {
1993         .name           = "mcspi_ick",
1994         .id             = 3,
1995         .parent         = &core_l4_ick,
1996         .prcm_mod       = CORE_MOD,
1997         .enable_reg     = CM_ICLKEN1,
1998         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1999         .idlest_bit     = OMAP3430_ST_MCSPI3_SHIFT,
2000         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2001         .clkdm          = { .name = "core_l4_clkdm" },
2002         .recalc         = &followparent_recalc,
2003 };
2004
2005 static struct clk mcspi2_ick = {
2006         .name           = "mcspi_ick",
2007         .id             = 2,
2008         .parent         = &core_l4_ick,
2009         .prcm_mod       = CORE_MOD,
2010         .enable_reg     = CM_ICLKEN1,
2011         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2012         .idlest_bit     = OMAP3430_ST_MCSPI2_SHIFT,
2013         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2014         .clkdm          = { .name = "core_l4_clkdm" },
2015         .recalc         = &followparent_recalc,
2016 };
2017
2018 static struct clk mcspi1_ick = {
2019         .name           = "mcspi_ick",
2020         .id             = 1,
2021         .parent         = &core_l4_ick,
2022         .prcm_mod       = CORE_MOD,
2023         .enable_reg     = CM_ICLKEN1,
2024         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2025         .idlest_bit     = OMAP3430_ST_MCSPI1_SHIFT,
2026         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2027         .clkdm          = { .name = "core_l4_clkdm" },
2028         .recalc         = &followparent_recalc,
2029 };
2030
2031 static struct clk i2c3_ick = {
2032         .name           = "i2c_ick",
2033         .id             = 3,
2034         .parent         = &core_l4_ick,
2035         .prcm_mod       = CORE_MOD,
2036         .enable_reg     = CM_ICLKEN1,
2037         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
2038         .idlest_bit     = OMAP3430_ST_I2C3_SHIFT,
2039         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2040         .clkdm          = { .name = "core_l4_clkdm" },
2041         .recalc         = &followparent_recalc,
2042 };
2043
2044 static struct clk i2c2_ick = {
2045         .name           = "i2c_ick",
2046         .id             = 2,
2047         .parent         = &core_l4_ick,
2048         .prcm_mod       = CORE_MOD,
2049         .enable_reg     = CM_ICLKEN1,
2050         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2051         .idlest_bit     = OMAP3430_ST_I2C2_SHIFT,
2052         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2053         .clkdm          = { .name = "core_l4_clkdm" },
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk i2c1_ick = {
2058         .name           = "i2c_ick",
2059         .id             = 1,
2060         .parent         = &core_l4_ick,
2061         .prcm_mod       = CORE_MOD,
2062         .enable_reg     = CM_ICLKEN1,
2063         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2064         .idlest_bit     = OMAP3430_ST_I2C1_SHIFT,
2065         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2066         .clkdm          = { .name = "core_l4_clkdm" },
2067         .recalc         = &followparent_recalc,
2068 };
2069
2070 static struct clk uart2_ick = {
2071         .name           = "uart2_ick",
2072         .parent         = &core_l4_ick,
2073         .prcm_mod       = CORE_MOD,
2074         .enable_reg     = CM_ICLKEN1,
2075         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2076         .idlest_bit     = OMAP3430_ST_UART2_SHIFT,
2077         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2078         .clkdm          = { .name = "core_l4_clkdm" },
2079         .recalc         = &followparent_recalc,
2080 };
2081
2082 static struct clk uart1_ick = {
2083         .name           = "uart1_ick",
2084         .parent         = &core_l4_ick,
2085         .prcm_mod       = CORE_MOD,
2086         .enable_reg     = CM_ICLKEN1,
2087         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2088         .idlest_bit     = OMAP3430_ST_UART1_SHIFT,
2089         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2090         .clkdm          = { .name = "core_l4_clkdm" },
2091         .recalc         = &followparent_recalc,
2092 };
2093
2094 static struct clk gpt11_ick = {
2095         .name           = "gpt11_ick",
2096         .parent         = &core_l4_ick,
2097         .prcm_mod       = CORE_MOD,
2098         .enable_reg     = CM_ICLKEN1,
2099         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2100         .idlest_bit     = OMAP3430_ST_GPT11_SHIFT,
2101         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2102         .clkdm          = { .name = "core_l4_clkdm" },
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk gpt10_ick = {
2107         .name           = "gpt10_ick",
2108         .parent         = &core_l4_ick,
2109         .prcm_mod       = CORE_MOD,
2110         .enable_reg     = CM_ICLKEN1,
2111         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2112         .idlest_bit     = OMAP3430_ST_GPT10_SHIFT,
2113         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2114         .clkdm          = { .name = "core_l4_clkdm" },
2115         .recalc         = &followparent_recalc,
2116 };
2117
2118 static struct clk mcbsp5_ick = {
2119         .name           = "mcbsp_ick",
2120         .id             = 5,
2121         .parent         = &core_l4_ick,
2122         .prcm_mod       = CORE_MOD,
2123         .enable_reg     = CM_ICLKEN1,
2124         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2125         .idlest_bit     = OMAP3430_ST_MCBSP5_SHIFT,
2126         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2127         .clkdm          = { .name = "core_l4_clkdm" },
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk mcbsp1_ick = {
2132         .name           = "mcbsp_ick",
2133         .id             = 1,
2134         .parent         = &core_l4_ick,
2135         .prcm_mod       = CORE_MOD,
2136         .enable_reg     = CM_ICLKEN1,
2137         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2138         .idlest_bit     = OMAP3430_ST_MCBSP1_SHIFT,
2139         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2140         .clkdm          = { .name = "core_l4_clkdm" },
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 static struct clk fac_ick = {
2145         .name           = "fac_ick",
2146         .parent         = &core_l4_ick,
2147         .prcm_mod       = CORE_MOD,
2148         .enable_reg     = CM_ICLKEN1,
2149         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2150         .idlest_bit     = OMAP3430ES1_ST_FAC_SHIFT,
2151         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2152         .clkdm          = { .name = "core_l4_clkdm" },
2153         .recalc         = &followparent_recalc,
2154 };
2155
2156 static struct clk mailboxes_ick = {
2157         .name           = "mailboxes_ick",
2158         .parent         = &core_l4_ick,
2159         .prcm_mod       = CORE_MOD,
2160         .enable_reg     = CM_ICLKEN1,
2161         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2162         .idlest_bit     = OMAP3430_ST_MAILBOXES_SHIFT,
2163         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2164         .clkdm          = { .name = "core_l4_clkdm" },
2165         .recalc         = &followparent_recalc,
2166 };
2167
2168 static struct clk omapctrl_ick = {
2169         .name           = "omapctrl_ick",
2170         .parent         = &core_l4_ick,
2171         .prcm_mod       = CORE_MOD,
2172         .enable_reg     = CM_ICLKEN1,
2173         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2174         .idlest_bit     = OMAP3430_ST_OMAPCTRL_SHIFT,
2175         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
2176         .clkdm          = { .name = "core_l4_clkdm" },
2177         .recalc         = &followparent_recalc,
2178 };
2179
2180 /* SSI_L4_ICK based clocks */
2181
2182 static struct clk ssi_l4_ick = {
2183         .name           = "ssi_l4_ick",
2184         .parent         = &l4_ick,
2185         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2186                                 PARENT_CONTROLS_CLOCK,
2187         .clkdm          = { .name = "core_l4_clkdm" },
2188         .recalc         = &followparent_recalc,
2189 };
2190
2191 static struct clk ssi_ick_3430es1 = {
2192         .name           = "ssi_ick",
2193         .parent         = &ssi_l4_ick,
2194         .prcm_mod       = CORE_MOD,
2195         .enable_reg     = CM_ICLKEN1,
2196         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2197         .flags          = CLOCK_IN_OMAP3430ES1,
2198         .clkdm          = { .name = "core_l4_clkdm" },
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk ssi_ick_3430es2 = {
2203         .name           = "ssi_ick",
2204         .parent         = &ssi_l4_ick,
2205         .prcm_mod       = CORE_MOD,
2206         .enable_reg     = CM_ICLKEN1,
2207         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2208         .idlest_bit     = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2209         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2210         .clkdm          = { .name = "core_l4_clkdm" },
2211         .recalc         = &followparent_recalc,
2212 };
2213
2214 /*
2215  * REVISIT: Technically the TRM claims that this is CORE_CLK based,
2216  * but l4_ick makes more sense to me
2217  */
2218 static const struct clksel usb_l4_clksel[] = {
2219         { .parent = &l4_ick, .rates = div2_rates },
2220         { .parent = NULL },
2221 };
2222
2223 static struct clk usb_l4_ick = {
2224         .name           = "usb_l4_ick",
2225         .parent         = &l4_ick,
2226         .prcm_mod       = CORE_MOD,
2227         .init           = &omap2_init_clksel_parent,
2228         .enable_reg     = CM_ICLKEN1,
2229         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2230         .idlest_bit     = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
2231         .clksel_reg     = CM_CLKSEL,
2232         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2233         .clksel         = usb_l4_clksel,
2234         .flags          = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
2235         .clkdm          = { .name = "core_l4_clkdm" },
2236         .recalc         = &omap2_clksel_recalc,
2237 };
2238
2239 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2240
2241 /* SECURITY_L4_ICK2 based clocks */
2242
2243 static struct clk security_l4_ick2 = {
2244         .name           = "security_l4_ick2",
2245         .parent         = &l4_ick,
2246         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2247                                 PARENT_CONTROLS_CLOCK,
2248         .clkdm          = { .name = "core_l4_clkdm" },
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk aes1_ick = {
2253         .name           = "aes1_ick",
2254         .parent         = &security_l4_ick2,
2255         .prcm_mod       = CORE_MOD,
2256         .enable_reg     = CM_ICLKEN2,
2257         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2258         .idlest_bit     = OMAP3430_ST_AES1_SHIFT,
2259         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2260         .clkdm          = { .name = "core_l4_clkdm" },
2261         .recalc         = &followparent_recalc,
2262 };
2263
2264 static struct clk rng_ick = {
2265         .name           = "rng_ick",
2266         .parent         = &security_l4_ick2,
2267         .prcm_mod       = CORE_MOD,
2268         .enable_reg     = CM_ICLKEN2,
2269         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2270         .idlest_bit     = OMAP3430_ST_RNG_SHIFT,
2271         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2272         .clkdm          = { .name = "core_l4_clkdm" },
2273         .recalc         = &followparent_recalc,
2274 };
2275
2276 static struct clk sha11_ick = {
2277         .name           = "sha11_ick",
2278         .parent         = &security_l4_ick2,
2279         .prcm_mod       = CORE_MOD,
2280         .enable_reg     = CM_ICLKEN2,
2281         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2282         .idlest_bit     = OMAP3430_ST_SHA11_SHIFT,
2283         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2284         .clkdm          = { .name = "core_l4_clkdm" },
2285         .recalc         = &followparent_recalc,
2286 };
2287
2288 static struct clk des1_ick = {
2289         .name           = "des1_ick",
2290         .parent         = &security_l4_ick2,
2291         .prcm_mod       = CORE_MOD,
2292         .enable_reg     = CM_ICLKEN2,
2293         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2294         .idlest_bit     = OMAP3430_ST_DES1_SHIFT,
2295         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2296         .clkdm          = { .name = "core_l4_clkdm" },
2297         .recalc         = &followparent_recalc,
2298 };
2299
2300 /* DSS */
2301 static struct clk dss1_alwon_fck_3430es1 = {
2302         .name           = "dss1_alwon_fck",
2303         .parent         = &dpll4_m4x2_ck,
2304         .prcm_mod       = OMAP3430_DSS_MOD,
2305         .enable_reg     = CM_FCLKEN,
2306         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2307         .flags          = CLOCK_IN_OMAP3430ES1,
2308         .clkdm          = { .name = "dss_clkdm" },
2309         .recalc         = &followparent_recalc,
2310 };
2311
2312 static struct clk dss1_alwon_fck_3430es2 = {
2313         .name           = "dss1_alwon_fck",
2314         .parent         = &dpll4_m4x2_ck,
2315         .init           = &omap2_init_clksel_parent,
2316         .prcm_mod       = OMAP3430_DSS_MOD,
2317         .enable_reg     = CM_FCLKEN,
2318         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2319         .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2320         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2321         .clkdm          = { .name = "dss_clkdm" },
2322         .recalc         = &followparent_recalc,
2323 };
2324
2325 static struct clk dss_tv_fck = {
2326         .name           = "dss_tv_fck",
2327         .parent         = &omap_54m_fck,
2328         .prcm_mod       = OMAP3430_DSS_MOD,
2329         .enable_reg     = CM_FCLKEN,
2330         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2331         .flags          = CLOCK_IN_OMAP343X,
2332         .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
2333         .recalc         = &followparent_recalc,
2334 };
2335
2336 static struct clk dss_96m_fck = {
2337         .name           = "dss_96m_fck",
2338         .parent         = &omap_96m_fck,
2339         .prcm_mod       = OMAP3430_DSS_MOD,
2340         .enable_reg     = CM_FCLKEN,
2341         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2342         .flags          = CLOCK_IN_OMAP343X,
2343         .clkdm          = { .name = "dss_clkdm" },
2344         .recalc         = &followparent_recalc,
2345 };
2346
2347 static struct clk dss2_alwon_fck = {
2348         .name           = "dss2_alwon_fck",
2349         .parent         = &sys_ck,
2350         .prcm_mod       = OMAP3430_DSS_MOD,
2351         .enable_reg     = CM_FCLKEN,
2352         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2353         .flags          = CLOCK_IN_OMAP343X,
2354         .clkdm          = { .name = "dss_clkdm" },
2355         .recalc         = &followparent_recalc,
2356 };
2357
2358 static struct clk dss_ick_3430es1 = {
2359         /* Handles both L3 and L4 clocks */
2360         .name           = "dss_ick",
2361         .parent         = &l4_ick,
2362         .prcm_mod       = OMAP3430_DSS_MOD,
2363         .enable_reg     = CM_ICLKEN,
2364         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2365         .flags          = CLOCK_IN_OMAP3430ES1,
2366         .clkdm          = { .name = "dss_clkdm" },
2367         .recalc         = &followparent_recalc,
2368 };
2369
2370 static struct clk dss_ick_3430es2 = {
2371         /* Handles both L3 and L4 clocks */
2372         .name           = "dss_ick",
2373         .parent         = &l4_ick,
2374         .prcm_mod       = OMAP3430_DSS_MOD,
2375         .enable_reg     = CM_ICLKEN,
2376         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2377         .idlest_bit     = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
2378         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2379         .clkdm          = { .name = "dss_clkdm" },
2380         .recalc         = &followparent_recalc,
2381 };
2382
2383 /* CAM */
2384
2385 static struct clk cam_mclk = {
2386         .name           = "cam_mclk",
2387         .parent         = &dpll4_m5x2_ck,
2388         .prcm_mod       = OMAP3430_CAM_MOD,
2389         .enable_reg     = CM_FCLKEN,
2390         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2391         .flags          = CLOCK_IN_OMAP343X,
2392         .clkdm          = { .name = "cam_clkdm" },
2393         .recalc         = &followparent_recalc,
2394 };
2395
2396 static struct clk cam_ick = {
2397         /* Handles both L3 and L4 clocks */
2398         .name           = "cam_ick",
2399         .parent         = &l4_ick,
2400         .prcm_mod       = OMAP3430_CAM_MOD,
2401         .enable_reg     = CM_ICLKEN,
2402         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2403         .flags          = CLOCK_IN_OMAP343X,
2404         .clkdm          = { .name = "cam_clkdm" },
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk csi2_96m_fck = {
2409         .name           = "csi2_96m_fck",
2410         .parent         = &core_96m_fck,
2411         .prcm_mod       = OMAP3430_CAM_MOD,
2412         .enable_reg     = CM_FCLKEN,
2413         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2414         .flags          = CLOCK_IN_OMAP343X,
2415         .clkdm          = { .name = "cam_clkdm" },
2416         .recalc         = &followparent_recalc,
2417 };
2418
2419 /* USBHOST - 3430ES2 only */
2420
2421 static struct clk usbhost_120m_fck = {
2422         .name           = "usbhost_120m_fck",
2423         .parent         = &dpll5_m2_ck,
2424         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2425         .enable_reg     = CM_FCLKEN,
2426         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2427         .flags          = CLOCK_IN_OMAP3430ES2,
2428         .clkdm          = { .name = "usbhost_clkdm" },
2429         .recalc         = &followparent_recalc,
2430 };
2431
2432 static struct clk usbhost_48m_fck = {
2433         .name           = "usbhost_48m_fck",
2434         .parent         = &omap_48m_fck,
2435         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2436         .enable_reg     = CM_FCLKEN,
2437         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2438         .idlest_bit     = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2439         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2440         .clkdm          = { .name = "usbhost_clkdm" },
2441         .recalc         = &followparent_recalc,
2442 };
2443
2444 static struct clk usbhost_ick = {
2445         /* Handles both L3 and L4 clocks */
2446         .name           = "usbhost_ick",
2447         .parent         = &l4_ick,
2448         .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
2449         .enable_reg     = CM_ICLKEN,
2450         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2451         .idlest_bit     = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
2452         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2453         .clkdm          = { .name = "usbhost_clkdm" },
2454         .recalc         = &followparent_recalc,
2455 };
2456
2457 /* WKUP */
2458
2459 static const struct clksel_rate usim_96m_rates[] = {
2460         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2461         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2462         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2463         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2464         { .div = 0 },
2465 };
2466
2467 static const struct clksel_rate usim_120m_rates[] = {
2468         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2469         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2470         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2471         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2472         { .div = 0 },
2473 };
2474
2475 static const struct clksel usim_clksel[] = {
2476         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2477         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2478         { .parent = &sys_ck,            .rates = div2_rates },
2479         { .parent = NULL },
2480 };
2481
2482 /* 3430ES2 only */
2483 static struct clk usim_fck = {
2484         .name           = "usim_fck",
2485         .prcm_mod       = WKUP_MOD,
2486         .init           = &omap2_init_clksel_parent,
2487         .enable_reg     = CM_FCLKEN,
2488         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2489         .idlest_bit     = OMAP3430ES2_ST_USIMOCP_SHIFT,
2490         .clksel_reg     = CM_CLKSEL,
2491         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2492         .clksel         = usim_clksel,
2493         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2494         .clkdm          = { .name = "prm_clkdm" },
2495         .recalc         = &omap2_clksel_recalc,
2496 };
2497
2498 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2499 static struct clk gpt1_fck = {
2500         .name           = "gpt1_fck",
2501         .prcm_mod       = WKUP_MOD,
2502         .init           = &omap2_init_clksel_parent,
2503         .enable_reg     = CM_FCLKEN,
2504         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2505         .idlest_bit     = OMAP3430_ST_GPT1_SHIFT,
2506         .clksel_reg     = CM_CLKSEL,
2507         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2508         .clksel         = omap343x_gpt_clksel,
2509         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2510         .clkdm          = { .name = "prm_clkdm" },
2511         .recalc         = &omap2_clksel_recalc,
2512 };
2513
2514 static struct clk wkup_32k_fck = {
2515         .name           = "wkup_32k_fck",
2516         .parent         = &omap_32k_fck,
2517         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2518         .clkdm          = { .name = "prm_clkdm" },
2519         .recalc         = &followparent_recalc,
2520 };
2521
2522 static struct clk gpio1_dbck = {
2523         .name           = "gpio1_dbck",
2524         .parent         = &wkup_32k_fck,
2525         .prcm_mod       = WKUP_MOD,
2526         .enable_reg     = CM_FCLKEN,
2527         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2528         .idlest_bit     = OMAP3430_ST_GPIO1_SHIFT,
2529         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2530         .clkdm          = { .name = "prm_clkdm" },
2531         .recalc         = &followparent_recalc,
2532 };
2533
2534 static struct clk wdt2_fck = {
2535         .name           = "wdt2_fck",
2536         .parent         = &wkup_32k_fck,
2537         .prcm_mod       = WKUP_MOD,
2538         .enable_reg     = CM_FCLKEN,
2539         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2540         .idlest_bit     = OMAP3430_ST_WDT2_SHIFT,
2541         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2542         .clkdm          = { .name = "prm_clkdm" },
2543         .recalc         = &followparent_recalc,
2544 };
2545
2546 static struct clk wkup_l4_ick = {
2547         .name           = "wkup_l4_ick",
2548         .parent         = &sys_ck,
2549         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2550         .clkdm          = { .name = "prm_clkdm" },
2551         .recalc         = &followparent_recalc,
2552 };
2553
2554 static struct clk usim_ick = {
2555         .name           = "usim_ick",
2556         .parent         = &wkup_l4_ick,
2557         .prcm_mod       = WKUP_MOD,
2558         .enable_reg     = CM_ICLKEN,
2559         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2560         .idlest_bit     = OMAP3430ES2_ST_USIMOCP_SHIFT,
2561         .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
2562         .clkdm          = { .name = "prm_clkdm" },
2563         .recalc         = &followparent_recalc,
2564 };
2565
2566 static struct clk wdt2_ick = {
2567         .name           = "wdt2_ick",
2568         .parent         = &wkup_l4_ick,
2569         .prcm_mod       = WKUP_MOD,
2570         .enable_reg     = CM_ICLKEN,
2571         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2572         .idlest_bit     = OMAP3430_ST_WDT2_SHIFT,
2573         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2574         .clkdm          = { .name = "prm_clkdm" },
2575         .recalc         = &followparent_recalc,
2576 };
2577
2578 static struct clk wdt1_ick = {
2579         .name           = "wdt1_ick",
2580         .parent         = &wkup_l4_ick,
2581         .prcm_mod       = WKUP_MOD,
2582         .enable_reg     = CM_ICLKEN,
2583         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2584         .idlest_bit     = OMAP3430_ST_WDT1_SHIFT,
2585         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2586         .clkdm          = { .name = "prm_clkdm" },
2587         .recalc         = &followparent_recalc,
2588 };
2589
2590 static struct clk gpio1_ick = {
2591         .name           = "gpio1_ick",
2592         .parent         = &wkup_l4_ick,
2593         .prcm_mod       = WKUP_MOD,
2594         .enable_reg     = CM_ICLKEN,
2595         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2596         .idlest_bit     = OMAP3430_ST_GPIO1_SHIFT,
2597         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2598         .clkdm          = { .name = "prm_clkdm" },
2599         .recalc         = &followparent_recalc,
2600 };
2601
2602 static struct clk omap_32ksync_ick = {
2603         .name           = "omap_32ksync_ick",
2604         .parent         = &wkup_l4_ick,
2605         .prcm_mod       = WKUP_MOD,
2606         .enable_reg     = CM_ICLKEN,
2607         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2608         .idlest_bit     = OMAP3430_ST_32KSYNC_SHIFT,
2609         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2610         .clkdm          = { .name = "prm_clkdm" },
2611         .recalc         = &followparent_recalc,
2612 };
2613
2614 static struct clk gpt12_ick = {
2615         .name           = "gpt12_ick",
2616         .parent         = &wkup_l4_ick,
2617         .prcm_mod       = WKUP_MOD,
2618         .enable_reg     = CM_ICLKEN,
2619         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2620         .idlest_bit     = OMAP3430_ST_GPT12_SHIFT,
2621         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2622         .clkdm          = { .name = "prm_clkdm" },
2623         .recalc         = &followparent_recalc,
2624 };
2625
2626 static struct clk gpt1_ick = {
2627         .name           = "gpt1_ick",
2628         .parent         = &wkup_l4_ick,
2629         .prcm_mod       = WKUP_MOD,
2630         .enable_reg     = CM_ICLKEN,
2631         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2632         .idlest_bit     = OMAP3430_ST_GPT1_SHIFT,
2633         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2634         .clkdm          = { .name = "prm_clkdm" },
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638
2639
2640 /* PER clock domain */
2641
2642 static struct clk per_96m_fck = {
2643         .name           = "per_96m_fck",
2644         .parent         = &omap_96m_alwon_fck,
2645         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2646                                 PARENT_CONTROLS_CLOCK,
2647         .clkdm          = { .name = "per_clkdm" },
2648         .recalc         = &followparent_recalc,
2649 };
2650
2651 static struct clk per_48m_fck = {
2652         .name           = "per_48m_fck",
2653         .parent         = &omap_48m_fck,
2654         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2655                                 PARENT_CONTROLS_CLOCK,
2656         .clkdm          = { .name = "per_clkdm" },
2657         .recalc         = &followparent_recalc,
2658 };
2659
2660 static struct clk uart3_fck = {
2661         .name           = "uart3_fck",
2662         .parent         = &per_48m_fck,
2663         .prcm_mod       = OMAP3430_PER_MOD,
2664         .enable_reg     = CM_FCLKEN,
2665         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2666         .idlest_bit     = OMAP3430_ST_UART3_SHIFT,
2667         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2668         .clkdm          = { .name = "per_clkdm" },
2669         .recalc         = &followparent_recalc,
2670 };
2671
2672 static struct clk gpt2_fck = {
2673         .name           = "gpt2_fck",
2674         .prcm_mod       = OMAP3430_PER_MOD,
2675         .init           = &omap2_init_clksel_parent,
2676         .enable_reg     = CM_FCLKEN,
2677         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2678         .idlest_bit     = OMAP3430_ST_GPT2_SHIFT,
2679         .clksel_reg     = CM_CLKSEL,
2680         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2681         .clksel         = omap343x_gpt_clksel,
2682         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2683         .clkdm          = { .name = "per_clkdm" },
2684         .recalc         = &omap2_clksel_recalc,
2685 };
2686
2687 static struct clk gpt3_fck = {
2688         .name           = "gpt3_fck",
2689         .prcm_mod       = OMAP3430_PER_MOD,
2690         .init           = &omap2_init_clksel_parent,
2691         .enable_reg     = CM_FCLKEN,
2692         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2693         .idlest_bit     = OMAP3430_ST_GPT3_SHIFT,
2694         .clksel_reg     = CM_CLKSEL,
2695         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2696         .clksel         = omap343x_gpt_clksel,
2697         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2698         .clkdm          = { .name = "per_clkdm" },
2699         .recalc         = &omap2_clksel_recalc,
2700 };
2701
2702 static struct clk gpt4_fck = {
2703         .name           = "gpt4_fck",
2704         .prcm_mod       = OMAP3430_PER_MOD,
2705         .init           = &omap2_init_clksel_parent,
2706         .enable_reg     = CM_FCLKEN,
2707         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2708         .idlest_bit     = OMAP3430_ST_GPT4_SHIFT,
2709         .clksel_reg     = CM_CLKSEL,
2710         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2711         .clksel         = omap343x_gpt_clksel,
2712         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2713         .clkdm          = { .name = "per_clkdm" },
2714         .recalc         = &omap2_clksel_recalc,
2715 };
2716
2717 static struct clk gpt5_fck = {
2718         .name           = "gpt5_fck",
2719         .prcm_mod       = OMAP3430_PER_MOD,
2720         .init           = &omap2_init_clksel_parent,
2721         .enable_reg     = CM_FCLKEN,
2722         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2723         .idlest_bit     = OMAP3430_ST_GPT5_SHIFT,
2724         .clksel_reg     = CM_CLKSEL,
2725         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2726         .clksel         = omap343x_gpt_clksel,
2727         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2728         .clkdm          = { .name = "per_clkdm" },
2729         .recalc         = &omap2_clksel_recalc,
2730 };
2731
2732 static struct clk gpt6_fck = {
2733         .name           = "gpt6_fck",
2734         .prcm_mod       = OMAP3430_PER_MOD,
2735         .init           = &omap2_init_clksel_parent,
2736         .enable_reg     = CM_FCLKEN,
2737         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2738         .idlest_bit     = OMAP3430_ST_GPT6_SHIFT,
2739         .clksel_reg     = CM_CLKSEL,
2740         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2741         .clksel         = omap343x_gpt_clksel,
2742         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2743         .clkdm          = { .name = "per_clkdm" },
2744         .recalc         = &omap2_clksel_recalc,
2745 };
2746
2747 static struct clk gpt7_fck = {
2748         .name           = "gpt7_fck",
2749         .prcm_mod       = OMAP3430_PER_MOD,
2750         .init           = &omap2_init_clksel_parent,
2751         .enable_reg     = CM_FCLKEN,
2752         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2753         .idlest_bit     = OMAP3430_ST_GPT7_SHIFT,
2754         .clksel_reg     = CM_CLKSEL,
2755         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2756         .clksel         = omap343x_gpt_clksel,
2757         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2758         .clkdm          = { .name = "per_clkdm" },
2759         .recalc         = &omap2_clksel_recalc,
2760 };
2761
2762 static struct clk gpt8_fck = {
2763         .name           = "gpt8_fck",
2764         .prcm_mod       = OMAP3430_PER_MOD,
2765         .init           = &omap2_init_clksel_parent,
2766         .enable_reg     = CM_FCLKEN,
2767         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2768         .idlest_bit     = OMAP3430_ST_GPT8_SHIFT,
2769         .clksel_reg     = CM_CLKSEL,
2770         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2771         .clksel         = omap343x_gpt_clksel,
2772         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2773         .clkdm          = { .name = "per_clkdm" },
2774         .recalc         = &omap2_clksel_recalc,
2775 };
2776
2777 static struct clk gpt9_fck = {
2778         .name           = "gpt9_fck",
2779         .prcm_mod       = OMAP3430_PER_MOD,
2780         .init           = &omap2_init_clksel_parent,
2781         .enable_reg     = CM_FCLKEN,
2782         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2783         .idlest_bit     = OMAP3430_ST_GPT9_SHIFT,
2784         .clksel_reg     = CM_CLKSEL,
2785         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2786         .clksel         = omap343x_gpt_clksel,
2787         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2788         .clkdm          = { .name = "per_clkdm" },
2789         .recalc         = &omap2_clksel_recalc,
2790 };
2791
2792 static struct clk per_32k_alwon_fck = {
2793         .name           = "per_32k_alwon_fck",
2794         .parent         = &omap_32k_fck,
2795         .clkdm          = { .name = "per_clkdm" },
2796         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2797         .recalc         = &followparent_recalc,
2798 };
2799
2800 static struct clk gpio6_dbck = {
2801         .name           = "gpio6_dbck",
2802         .parent         = &per_32k_alwon_fck,
2803         .prcm_mod       = OMAP3430_PER_MOD,
2804         .enable_reg     = CM_FCLKEN,
2805         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2806         .idlest_bit     = OMAP3430_ST_GPIO6_SHIFT,
2807         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2808         .clkdm          = { .name = "per_clkdm" },
2809         .recalc         = &followparent_recalc,
2810 };
2811
2812 static struct clk gpio5_dbck = {
2813         .name           = "gpio5_dbck",
2814         .parent         = &per_32k_alwon_fck,
2815         .prcm_mod       = OMAP3430_PER_MOD,
2816         .enable_reg     = CM_FCLKEN,
2817         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2818         .idlest_bit     = OMAP3430_ST_GPIO5_SHIFT,
2819         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2820         .clkdm          = { .name = "per_clkdm" },
2821         .recalc         = &followparent_recalc,
2822 };
2823
2824 static struct clk gpio4_dbck = {
2825         .name           = "gpio4_dbck",
2826         .parent         = &per_32k_alwon_fck,
2827         .prcm_mod       = OMAP3430_PER_MOD,
2828         .enable_reg     = CM_FCLKEN,
2829         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2830         .idlest_bit     = OMAP3430_ST_GPIO4_SHIFT,
2831         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2832         .clkdm          = { .name = "per_clkdm" },
2833         .recalc         = &followparent_recalc,
2834 };
2835
2836 static struct clk gpio3_dbck = {
2837         .name           = "gpio3_dbck",
2838         .parent         = &per_32k_alwon_fck,
2839         .prcm_mod       = OMAP3430_PER_MOD,
2840         .enable_reg     = CM_FCLKEN,
2841         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2842         .idlest_bit     = OMAP3430_ST_GPIO3_SHIFT,
2843         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2844         .clkdm          = { .name = "per_clkdm" },
2845         .recalc         = &followparent_recalc,
2846 };
2847
2848 static struct clk gpio2_dbck = {
2849         .name           = "gpio2_dbck",
2850         .parent         = &per_32k_alwon_fck,
2851         .prcm_mod       = OMAP3430_PER_MOD,
2852         .enable_reg     = CM_FCLKEN,
2853         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2854         .idlest_bit     = OMAP3430_ST_GPIO2_SHIFT,
2855         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2856         .clkdm          = { .name = "per_clkdm" },
2857         .recalc         = &followparent_recalc,
2858 };
2859
2860 static struct clk wdt3_fck = {
2861         .name           = "wdt3_fck",
2862         .parent         = &per_32k_alwon_fck,
2863         .prcm_mod       = OMAP3430_PER_MOD,
2864         .enable_reg     = CM_FCLKEN,
2865         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2866         .idlest_bit     = OMAP3430_ST_WDT3_SHIFT,
2867         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2868         .clkdm          = { .name = "per_clkdm" },
2869         .recalc         = &followparent_recalc,
2870 };
2871
2872 static struct clk per_l4_ick = {
2873         .name           = "per_l4_ick",
2874         .parent         = &l4_ick,
2875         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2876                                 PARENT_CONTROLS_CLOCK,
2877         .clkdm          = { .name = "per_clkdm" },
2878         .recalc         = &followparent_recalc,
2879 };
2880
2881 static struct clk gpio6_ick = {
2882         .name           = "gpio6_ick",
2883         .parent         = &per_l4_ick,
2884         .prcm_mod       = OMAP3430_PER_MOD,
2885         .enable_reg     = CM_ICLKEN,
2886         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2887         .idlest_bit     = OMAP3430_ST_GPIO6_SHIFT,
2888         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2889         .clkdm          = { .name = "per_clkdm" },
2890         .recalc         = &followparent_recalc,
2891 };
2892
2893 static struct clk gpio5_ick = {
2894         .name           = "gpio5_ick",
2895         .parent         = &per_l4_ick,
2896         .prcm_mod       = OMAP3430_PER_MOD,
2897         .enable_reg     = CM_ICLKEN,
2898         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2899         .idlest_bit     = OMAP3430_ST_GPIO5_SHIFT,
2900         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2901         .clkdm          = { .name = "per_clkdm" },
2902         .recalc         = &followparent_recalc,
2903 };
2904
2905 static struct clk gpio4_ick = {
2906         .name           = "gpio4_ick",
2907         .parent         = &per_l4_ick,
2908         .prcm_mod       = OMAP3430_PER_MOD,
2909         .enable_reg     = CM_ICLKEN,
2910         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2911         .idlest_bit     = OMAP3430_ST_GPIO4_SHIFT,
2912         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2913         .clkdm          = { .name = "per_clkdm" },
2914         .recalc         = &followparent_recalc,
2915 };
2916
2917 static struct clk gpio3_ick = {
2918         .name           = "gpio3_ick",
2919         .parent         = &per_l4_ick,
2920         .prcm_mod       = OMAP3430_PER_MOD,
2921         .enable_reg     = CM_ICLKEN,
2922         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2923         .idlest_bit     = OMAP3430_ST_GPIO3_SHIFT,
2924         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2925         .clkdm          = { .name = "per_clkdm" },
2926         .recalc         = &followparent_recalc,
2927 };
2928
2929 static struct clk gpio2_ick = {
2930         .name           = "gpio2_ick",
2931         .parent         = &per_l4_ick,
2932         .prcm_mod       = OMAP3430_PER_MOD,
2933         .enable_reg     = CM_ICLKEN,
2934         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2935         .idlest_bit     = OMAP3430_ST_GPIO2_SHIFT,
2936         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2937         .clkdm          = { .name = "per_clkdm" },
2938         .recalc         = &followparent_recalc,
2939 };
2940
2941 static struct clk wdt3_ick = {
2942         .name           = "wdt3_ick",
2943         .parent         = &per_l4_ick,
2944         .prcm_mod       = OMAP3430_PER_MOD,
2945         .enable_reg     = CM_ICLKEN,
2946         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2947         .idlest_bit     = OMAP3430_ST_WDT3_SHIFT,
2948         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2949         .clkdm          = { .name = "per_clkdm" },
2950         .recalc         = &followparent_recalc,
2951 };
2952
2953 static struct clk uart3_ick = {
2954         .name           = "uart3_ick",
2955         .parent         = &per_l4_ick,
2956         .prcm_mod       = OMAP3430_PER_MOD,
2957         .enable_reg     = CM_ICLKEN,
2958         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2959         .idlest_bit     = OMAP3430_ST_UART3_SHIFT,
2960         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2961         .clkdm          = { .name = "per_clkdm" },
2962         .recalc         = &followparent_recalc,
2963 };
2964
2965 static struct clk gpt9_ick = {
2966         .name           = "gpt9_ick",
2967         .parent         = &per_l4_ick,
2968         .prcm_mod       = OMAP3430_PER_MOD,
2969         .enable_reg     = CM_ICLKEN,
2970         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2971         .idlest_bit     = OMAP3430_ST_GPT9_SHIFT,
2972         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2973         .clkdm          = { .name = "per_clkdm" },
2974         .recalc         = &followparent_recalc,
2975 };
2976
2977 static struct clk gpt8_ick = {
2978         .name           = "gpt8_ick",
2979         .parent         = &per_l4_ick,
2980         .prcm_mod       = OMAP3430_PER_MOD,
2981         .enable_reg     = CM_ICLKEN,
2982         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2983         .idlest_bit     = OMAP3430_ST_GPT8_SHIFT,
2984         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2985         .clkdm          = { .name = "per_clkdm" },
2986         .recalc         = &followparent_recalc,
2987 };
2988
2989 static struct clk gpt7_ick = {
2990         .name           = "gpt7_ick",
2991         .parent         = &per_l4_ick,
2992         .prcm_mod       = OMAP3430_PER_MOD,
2993         .enable_reg     = CM_ICLKEN,
2994         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2995         .idlest_bit     = OMAP3430_ST_GPT7_SHIFT,
2996         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
2997         .clkdm          = { .name = "per_clkdm" },
2998         .recalc         = &followparent_recalc,
2999 };
3000
3001 static struct clk gpt6_ick = {
3002         .name           = "gpt6_ick",
3003         .parent         = &per_l4_ick,
3004         .prcm_mod       = OMAP3430_PER_MOD,
3005         .enable_reg     = CM_ICLKEN,
3006         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
3007         .idlest_bit     = OMAP3430_ST_GPT6_SHIFT,
3008         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3009         .clkdm          = { .name = "per_clkdm" },
3010         .recalc         = &followparent_recalc,
3011 };
3012
3013 static struct clk gpt5_ick = {
3014         .name           = "gpt5_ick",
3015         .parent         = &per_l4_ick,
3016         .prcm_mod       = OMAP3430_PER_MOD,
3017         .enable_reg     = CM_ICLKEN,
3018         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
3019         .idlest_bit     = OMAP3430_ST_GPT5_SHIFT,
3020         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3021         .clkdm          = { .name = "per_clkdm" },
3022         .recalc         = &followparent_recalc,
3023 };
3024
3025 static struct clk gpt4_ick = {
3026         .name           = "gpt4_ick",
3027         .parent         = &per_l4_ick,
3028         .prcm_mod       = OMAP3430_PER_MOD,
3029         .enable_reg     = CM_ICLKEN,
3030         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
3031         .idlest_bit     = OMAP3430_ST_GPT4_SHIFT,
3032         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3033         .clkdm          = { .name = "per_clkdm" },
3034         .recalc         = &followparent_recalc,
3035 };
3036
3037 static struct clk gpt3_ick = {
3038         .name           = "gpt3_ick",
3039         .parent         = &per_l4_ick,
3040         .prcm_mod       = OMAP3430_PER_MOD,
3041         .enable_reg     = CM_ICLKEN,
3042         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
3043         .idlest_bit     = OMAP3430_ST_GPT3_SHIFT,
3044         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3045         .clkdm          = { .name = "per_clkdm" },
3046         .recalc         = &followparent_recalc,
3047 };
3048
3049 static struct clk gpt2_ick = {
3050         .name           = "gpt2_ick",
3051         .parent         = &per_l4_ick,
3052         .prcm_mod       = OMAP3430_PER_MOD,
3053         .enable_reg     = CM_ICLKEN,
3054         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
3055         .idlest_bit     = OMAP3430_ST_GPT2_SHIFT,
3056         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3057         .clkdm          = { .name = "per_clkdm" },
3058         .recalc         = &followparent_recalc,
3059 };
3060
3061 static struct clk mcbsp2_ick = {
3062         .name           = "mcbsp_ick",
3063         .id             = 2,
3064         .parent         = &per_l4_ick,
3065         .prcm_mod       = OMAP3430_PER_MOD,
3066         .enable_reg     = CM_ICLKEN,
3067         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
3068         .idlest_bit     = OMAP3430_ST_MCBSP2_SHIFT,
3069         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3070         .clkdm          = { .name = "per_clkdm" },
3071         .recalc         = &followparent_recalc,
3072 };
3073
3074 static struct clk mcbsp3_ick = {
3075         .name           = "mcbsp_ick",
3076         .id             = 3,
3077         .parent         = &per_l4_ick,
3078         .prcm_mod       = OMAP3430_PER_MOD,
3079         .enable_reg     = CM_ICLKEN,
3080         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
3081         .idlest_bit     = OMAP3430_ST_MCBSP3_SHIFT,
3082         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3083         .clkdm          = { .name = "per_clkdm" },
3084         .recalc         = &followparent_recalc,
3085 };
3086
3087 static struct clk mcbsp4_ick = {
3088         .name           = "mcbsp_ick",
3089         .id             = 4,
3090         .parent         = &per_l4_ick,
3091         .prcm_mod       = OMAP3430_PER_MOD,
3092         .enable_reg     = CM_ICLKEN,
3093         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3094         .idlest_bit     = OMAP3430_ST_MCBSP4_SHIFT,
3095         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3096         .clkdm          = { .name = "per_clkdm" },
3097         .recalc         = &followparent_recalc,
3098 };
3099
3100 static const struct clksel mcbsp_234_clksel[] = {
3101         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
3102         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
3103         { .parent = NULL }
3104 };
3105
3106 static struct clk mcbsp2_src_fck = {
3107         .name           = "mcbsp_src_fck",
3108         .id             = 2,
3109         .prcm_mod       = CLK_REG_IN_SCM,
3110         .init           = &omap2_init_clksel_parent,
3111         .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
3112         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
3113         .clksel         = mcbsp_234_clksel,
3114         .flags          = CLOCK_IN_OMAP343X,
3115         .clkdm          = { .name = "per_clkdm" },
3116         .recalc         = &omap2_clksel_recalc,
3117 };
3118
3119 static struct clk mcbsp2_fck = {
3120         .name           = "mcbsp_fck",
3121         .id             = 2,
3122         .parent         = &mcbsp2_src_fck,
3123         .prcm_mod       = OMAP3430_PER_MOD,
3124         .enable_reg     = CM_FCLKEN,
3125         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
3126         .idlest_bit     = OMAP3430_ST_MCBSP2_SHIFT,
3127         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3128         .clkdm          = { .name = "per_clkdm" },
3129         .recalc         = &omap2_clksel_recalc,
3130 };
3131
3132 static struct clk mcbsp3_src_fck = {
3133         .name           = "mcbsp_src_fck",
3134         .id             = 3,
3135         .prcm_mod       = CLK_REG_IN_SCM,
3136         .init           = &omap2_init_clksel_parent,
3137         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
3138         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
3139         .clksel         = mcbsp_234_clksel,
3140         .flags          = CLOCK_IN_OMAP343X,
3141         .clkdm          = { .name = "per_clkdm" },
3142         .recalc         = &omap2_clksel_recalc,
3143 };
3144
3145 static struct clk mcbsp3_fck = {
3146         .name           = "mcbsp_fck",
3147         .id             = 3,
3148         .parent         = &mcbsp3_src_fck,
3149         .prcm_mod       = OMAP3430_PER_MOD,
3150         .enable_reg     = CM_FCLKEN,
3151         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
3152         .idlest_bit     = OMAP3430_ST_MCBSP3_SHIFT,
3153         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3154         .clkdm          = { .name = "per_clkdm" },
3155         .recalc         = &omap2_clksel_recalc,
3156 };
3157
3158 static struct clk mcbsp4_src_fck = {
3159         .name           = "mcbsp_src_fck",
3160         .id             = 4,
3161         .prcm_mod       = CLK_REG_IN_SCM,
3162         .init           = &omap2_init_clksel_parent,
3163         .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
3164         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
3165         .clksel         = mcbsp_234_clksel,
3166         .flags          = CLOCK_IN_OMAP343X,
3167         .clkdm          = { .name = "per_clkdm" },
3168         .recalc         = &omap2_clksel_recalc,
3169 };
3170
3171 static struct clk mcbsp4_fck = {
3172         .name           = "mcbsp_fck",
3173         .id             = 4,
3174         .parent         = &mcbsp4_src_fck,
3175         .prcm_mod       = OMAP3430_PER_MOD,
3176         .enable_reg     = CM_FCLKEN,
3177         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
3178         .idlest_bit     = OMAP3430_ST_MCBSP4_SHIFT,
3179         .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
3180         .clkdm          = { .name = "per_clkdm" },
3181         .recalc         = &omap2_clksel_recalc,
3182 };
3183
3184 /* EMU clocks */
3185
3186 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
3187
3188 static const struct clksel_rate emu_src_sys_rates[] = {
3189         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
3190         { .div = 0 },
3191 };
3192
3193 static const struct clksel_rate emu_src_core_rates[] = {
3194         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3195         { .div = 0 },
3196 };
3197
3198 static const struct clksel_rate emu_src_per_rates[] = {
3199         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3200         { .div = 0 },
3201 };
3202
3203 static const struct clksel_rate emu_src_mpu_rates[] = {
3204         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
3205         { .div = 0 },
3206 };
3207
3208 static const struct clksel emu_src_clksel[] = {
3209         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
3210         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
3211         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
3212         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
3213         { .parent = NULL },
3214 };
3215
3216 /*
3217  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
3218  * to switch the source of some of the EMU clocks.
3219  * XXX Are there CLKEN bits for these EMU clks?
3220  */
3221 static struct clk emu_src_ck = {
3222         .name           = "emu_src_ck",
3223         .prcm_mod       = OMAP3430_EMU_MOD,
3224         .init           = &omap2_init_clksel_parent,
3225         .clksel_reg     = CM_CLKSEL1,
3226         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
3227         .clksel         = emu_src_clksel,
3228         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3229         .clkdm          = { .name = "emu_clkdm" },
3230         .recalc         = &omap2_clksel_recalc,
3231 };
3232
3233 static const struct clksel_rate pclk_emu_rates[] = {
3234         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3235         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3236         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3237         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3238         { .div = 0 },
3239 };
3240
3241 static const struct clksel pclk_emu_clksel[] = {
3242         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3243         { .parent = NULL },
3244 };
3245
3246 static struct clk pclk_fck = {
3247         .name           = "pclk_fck",
3248         .prcm_mod       = OMAP3430_EMU_MOD,
3249         .init           = &omap2_init_clksel_parent,
3250         .clksel_reg     = CM_CLKSEL1,
3251         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3252         .clksel         = pclk_emu_clksel,
3253         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3254         .clkdm          = { .name = "emu_clkdm" },
3255         .recalc         = &omap2_clksel_recalc,
3256 };
3257
3258 static const struct clksel_rate pclkx2_emu_rates[] = {
3259         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3260         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3261         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3262         { .div = 0 },
3263 };
3264
3265 static const struct clksel pclkx2_emu_clksel[] = {
3266         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3267         { .parent = NULL },
3268 };
3269
3270 static struct clk pclkx2_fck = {
3271         .name           = "pclkx2_fck",
3272         .prcm_mod       = OMAP3430_EMU_MOD,
3273         .init           = &omap2_init_clksel_parent,
3274         .clksel_reg     = CM_CLKSEL1,
3275         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3276         .clksel         = pclkx2_emu_clksel,
3277         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3278         .clkdm          = { .name = "emu_clkdm" },
3279         .recalc         = &omap2_clksel_recalc,
3280 };
3281
3282 static const struct clksel atclk_emu_clksel[] = {
3283         { .parent = &emu_src_ck, .rates = div2_rates },
3284         { .parent = NULL },
3285 };
3286
3287 static struct clk atclk_fck = {
3288         .name           = "atclk_fck",
3289         .prcm_mod       = OMAP3430_EMU_MOD,
3290         .init           = &omap2_init_clksel_parent,
3291         .clksel_reg     = CM_CLKSEL1,
3292         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3293         .clksel         = atclk_emu_clksel,
3294         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3295         .clkdm          = { .name = "emu_clkdm" },
3296         .recalc         = &omap2_clksel_recalc,
3297 };
3298
3299 static struct clk traceclk_src_fck = {
3300         .name           = "traceclk_src_fck",
3301         .prcm_mod       = OMAP3430_EMU_MOD,
3302         .init           = &omap2_init_clksel_parent,
3303         .clksel_reg     = CM_CLKSEL1,
3304         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3305         .clksel         = emu_src_clksel,
3306         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
3307         .clkdm          = { .name = "emu_clkdm" },
3308         .recalc         = &omap2_clksel_recalc,
3309 };
3310
3311 static const struct clksel_rate traceclk_rates[] = {
3312         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3313         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3314         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3315         { .div = 0 },
3316 };
3317
3318 static const struct clksel traceclk_clksel[] = {
3319         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3320         { .parent = NULL },
3321 };
3322
3323 static struct clk traceclk_fck = {
3324         .name           = "traceclk_fck",
3325         .prcm_mod       = OMAP3430_EMU_MOD,
3326         .init           = &omap2_init_clksel_parent,
3327         .clksel_reg     = CM_CLKSEL1,
3328         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3329         .clksel         = traceclk_clksel,
3330         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3331         .clkdm          = { .name = "emu_clkdm" },
3332         .recalc         = &omap2_clksel_recalc,
3333 };
3334
3335 /* SR clocks */
3336
3337 /* SmartReflex fclk (VDD1) */
3338 static struct clk sr1_fck = {
3339         .name           = "sr1_fck",
3340         .parent         = &sys_ck,
3341         .prcm_mod       = WKUP_MOD,
3342         .enable_reg     = CM_FCLKEN,
3343         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3344         .idlest_bit     = OMAP3430_ST_SR1_SHIFT,
3345         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3346         .clkdm          = { .name = "prm_clkdm" },
3347         .recalc         = &followparent_recalc,
3348 };
3349
3350 /* SmartReflex fclk (VDD2) */
3351 static struct clk sr2_fck = {
3352         .name           = "sr2_fck",
3353         .parent         = &sys_ck,
3354         .prcm_mod       = WKUP_MOD,
3355         .enable_reg     = CM_FCLKEN,
3356         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3357         .idlest_bit     = OMAP3430_ST_SR2_SHIFT,
3358         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
3359         .clkdm          = { .name = "prm_clkdm" },
3360         .recalc         = &followparent_recalc,
3361 };
3362
3363 static struct clk sr_l4_ick = {
3364         .name           = "sr_l4_ick",
3365         .parent         = &l4_ick,
3366         .flags          = CLOCK_IN_OMAP343X,
3367         .clkdm          = { .name = "core_l4_clkdm" },
3368         .recalc         = &followparent_recalc,
3369 };
3370
3371 /* SECURE_32K_FCK clocks */
3372
3373 /* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
3374 static struct clk gpt12_fck = {
3375         .name           = "gpt12_fck",
3376         .parent         = &secure_32k_fck,
3377         .idlest_bit     = OMAP3430_ST_GPT12_SHIFT,
3378         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
3379         .clkdm          = { .name = "prm_clkdm" },
3380         .recalc         = &followparent_recalc,
3381 };
3382
3383 static struct clk wdt1_fck = {
3384         .name           = "wdt1_fck",
3385         .parent         = &secure_32k_fck,
3386         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3387         .clkdm          = { .name = "prm_clkdm" },
3388         .recalc         = &followparent_recalc,
3389 };
3390
3391 static struct clk *onchip_34xx_clks[] __initdata = {
3392         &omap_32k_fck,
3393         &virt_12m_ck,
3394         &virt_13m_ck,
3395         &virt_16_8m_ck,
3396         &virt_19_2m_ck,
3397         &virt_26m_ck,
3398         &virt_38_4m_ck,
3399         &osc_sys_ck,
3400         &sys_ck,
3401         &sys_altclk,
3402         &mcbsp_clks,
3403         &sys_clkout1,
3404         &dpll1_ck,
3405         &dpll1_x2_ck,
3406         &dpll1_x2m2_ck,
3407         &dpll2_ck,
3408         &dpll2_m2_ck,
3409         &dpll3_ck,
3410         &core_ck,
3411         &dpll3_x2_ck,
3412         &dpll3_m2_ck,
3413         &dpll3_m2x2_ck,
3414         &dpll3_m3_ck,
3415         &dpll3_m3x2_ck,
3416         &emu_core_alwon_ck,
3417         &dpll4_ck,
3418         &dpll4_x2_ck,
3419         &omap_96m_alwon_fck,
3420         &omap_96m_fck,
3421         &cm_96m_fck,
3422         &omap_54m_fck,
3423         &omap_48m_fck,
3424         &omap_12m_fck,
3425         &dpll4_m2_ck,
3426         &dpll4_m2x2_ck,
3427         &dpll4_m3_ck,
3428         &dpll4_m3x2_ck,
3429         &dpll4_m4_ck,
3430         &dpll4_m4x2_ck,
3431         &dpll4_m5_ck,
3432         &dpll4_m5x2_ck,
3433         &dpll4_m6_ck,
3434         &dpll4_m6x2_ck,
3435         &emu_per_alwon_ck,
3436         &dpll5_ck,
3437         &dpll5_m2_ck,
3438         &clkout2_src_ck,
3439         &sys_clkout2,
3440         &corex2_fck,
3441         &dpll1_fck,
3442         &mpu_ck,
3443         &arm_fck,
3444         &emu_mpu_alwon_ck,
3445         &dpll2_fck,
3446         &iva2_ck,
3447         &l3_ick,
3448         &l4_ick,
3449         &rm_ick,
3450         &gfx_l3_ck,
3451         &gfx_l3_fck,
3452         &gfx_l3_ick,
3453         &gfx_cg1_ck,
3454         &gfx_cg2_ck,
3455         &sgx_fck,
3456         &sgx_ick,
3457         &d2d_26m_fck,
3458         &gpt10_fck,
3459         &gpt11_fck,
3460         &cpefuse_fck,
3461         &ts_fck,
3462         &usbtll_fck,
3463         &core_96m_fck,
3464         &mmchs3_fck,
3465         &mmchs2_fck,
3466         &mspro_fck,
3467         &mmchs1_fck,
3468         &i2c3_fck,
3469         &i2c2_fck,
3470         &i2c1_fck,
3471         &mcbsp5_src_fck,
3472         &mcbsp5_fck,
3473         &mcbsp1_src_fck,
3474         &mcbsp1_fck,
3475         &core_48m_fck,
3476         &mcspi4_fck,
3477         &mcspi3_fck,
3478         &mcspi2_fck,
3479         &mcspi1_fck,
3480         &uart2_fck,
3481         &uart1_fck,
3482         &fshostusb_fck,
3483         &core_12m_fck,
3484         &hdq_fck,
3485         &ssi_ssr_fck_3430es1,
3486         &ssi_ssr_fck_3430es2,
3487         &ssi_sst_fck_3430es1,
3488         &ssi_sst_fck_3430es2,
3489         &core_l3_ick,
3490         &hsotgusb_ick_3430es1,
3491         &hsotgusb_ick_3430es2,
3492         &sdrc_ick,
3493         &gpmc_fck,
3494         &security_l3_ick,
3495         &pka_ick,
3496         &core_l4_ick,
3497         &usbtll_ick,
3498         &mmchs3_ick,
3499         &icr_ick,
3500         &aes2_ick,
3501         &sha12_ick,
3502         &des2_ick,
3503         &mmchs2_ick,
3504         &mmchs1_ick,
3505         &mspro_ick,
3506         &hdq_ick,
3507         &mcspi4_ick,
3508         &mcspi3_ick,
3509         &mcspi2_ick,
3510         &mcspi1_ick,
3511         &i2c3_ick,
3512         &i2c2_ick,
3513         &i2c1_ick,
3514         &uart2_ick,
3515         &uart1_ick,
3516         &gpt11_ick,
3517         &gpt10_ick,
3518         &mcbsp5_ick,
3519         &mcbsp1_ick,
3520         &fac_ick,
3521         &mailboxes_ick,
3522         &omapctrl_ick,
3523         &ssi_l4_ick,
3524         &ssi_ick_3430es1,
3525         &ssi_ick_3430es2,
3526         &usb_l4_ick,
3527         &security_l4_ick2,
3528         &aes1_ick,
3529         &rng_ick,
3530         &sha11_ick,
3531         &des1_ick,
3532         &dss1_alwon_fck_3430es1,
3533         &dss1_alwon_fck_3430es2,
3534         &dss_tv_fck,
3535         &dss_96m_fck,
3536         &dss2_alwon_fck,
3537         &dss_ick_3430es1,
3538         &dss_ick_3430es2,
3539         &cam_mclk,
3540         &cam_ick,
3541         &csi2_96m_fck,
3542         &usbhost_120m_fck,
3543         &usbhost_48m_fck,
3544         &usbhost_ick,
3545         &usim_fck,
3546         &gpt1_fck,
3547         &wkup_32k_fck,
3548         &gpio1_dbck,
3549         &wdt2_fck,
3550         &wkup_l4_ick,
3551         &usim_ick,
3552         &wdt2_ick,
3553         &wdt1_ick,
3554         &gpio1_ick,
3555         &omap_32ksync_ick,
3556         &gpt12_ick,
3557         &gpt1_ick,
3558         &per_96m_fck,
3559         &per_48m_fck,
3560         &uart3_fck,
3561         &gpt2_fck,
3562         &gpt3_fck,
3563         &gpt4_fck,
3564         &gpt5_fck,
3565         &gpt6_fck,
3566         &gpt7_fck,
3567         &gpt8_fck,
3568         &gpt9_fck,
3569         &per_32k_alwon_fck,
3570         &gpio6_dbck,
3571         &gpio5_dbck,
3572         &gpio4_dbck,
3573         &gpio3_dbck,
3574         &gpio2_dbck,
3575         &wdt3_fck,
3576         &per_l4_ick,
3577         &gpio6_ick,
3578         &gpio5_ick,
3579         &gpio4_ick,
3580         &gpio3_ick,
3581         &gpio2_ick,
3582         &wdt3_ick,
3583         &uart3_ick,
3584         &gpt9_ick,
3585         &gpt8_ick,
3586         &gpt7_ick,
3587         &gpt6_ick,
3588         &gpt5_ick,
3589         &gpt4_ick,
3590         &gpt3_ick,
3591         &gpt2_ick,
3592         &mcbsp2_ick,
3593         &mcbsp3_ick,
3594         &mcbsp4_ick,
3595         &mcbsp2_src_fck,
3596         &mcbsp2_fck,
3597         &mcbsp3_src_fck,
3598         &mcbsp3_fck,
3599         &mcbsp4_src_fck,
3600         &mcbsp4_fck,
3601         &emu_src_ck,
3602         &pclk_fck,
3603         &pclkx2_fck,
3604         &atclk_fck,
3605         &traceclk_src_fck,
3606         &traceclk_fck,
3607         &sr1_fck,
3608         &sr2_fck,
3609         &sr_l4_ick,
3610         &secure_32k_fck,
3611         &gpt12_fck,
3612         &wdt1_fck,
3613 };
3614
3615 #endif