arch/arm/mach-omap2/clock34xx.c

   1 /*
   2  * OMAP3-specific clock framework functions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Testing and integration fixes by Jouni Högander
   9  *
  10  * Parts of this code are based on code written by
  11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17 #undef DEBUG
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/device.h>
  22 #include <linux/list.h>
  23 #include <linux/errno.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/io.h>
  27 #include <linux/limits.h>
  28 #include <linux/bitops.h>
  29
  30 #include <mach/clock.h>
  31 #include <mach/sram.h>
  32 #include <asm/div64.h>
  33 #include <asm/clkdev.h>
  34
  35 #include "memory.h"
  36 #include "clock.h"
  37 #include "prm.h"
  38 #include "prm-regbits-34xx.h"
  39 #include "cm.h"
  40 #include "cm-regbits-34xx.h"
  41
  42 static const struct clkops clkops_noncore_dpll_ops;
  43
  44 #include "clock34xx.h"
  45
  46 struct omap_clk {
  47         u32             cpu;
  48         struct clk_lookup lk;
  49 };
  50
  51 #define CLK(dev, con, ck, cp)           \
  52         {                               \
  53                  .cpu = cp,             \
  54                 .lk = {                 \
  55                         .dev_id = dev,  \
  56                         .con_id = con,  \
  57                         .clk = ck,      \
  58                 },                      \
  59         }
  60
  61 #define CK_343X         (1 << 0)
  62 #define CK_3430ES1      (1 << 1)
  63 #define CK_3430ES2      (1 << 2)
  64
  65 static struct omap_clk omap34xx_clks[] = {
  66         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
  67         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
  68         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
  69         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
  70         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
  71         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
  72         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
  73         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
  74         CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
  75         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
  76         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
  77         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
  78         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
  79         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
  80         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
  81         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
  82         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
  83         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
  84         CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
  85         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
  86         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
  87         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
  88         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
  89         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
  90         CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
  91         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
  92         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
  93         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
  94         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
  95         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
  96         CLK(NULL,       "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X),
  97         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
  98         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
  99         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
 100         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
 101         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
 102         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
 103         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
 104         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
 105         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
 106         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
 107         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
 108         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
 109         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
 110         CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
 111         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
 112         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
 113         CLK(NULL,       "omap_120m_fck", &omap_120m_fck, CK_3430ES2),
 114         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
 115         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
 116         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
 117         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
 118         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
 119         CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
 120         CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
 121         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
 122         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
 123         CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
 124         CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
 125         CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
 126         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
 127         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
 128         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
 129         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
 130         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
 131         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
 132         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
 133         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
 134         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
 135         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
 136         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
 137         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
 138         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
 139         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
 140         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
 141         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
 142         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
 143         CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
 144         CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
 145         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
 146         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
 147         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
 148         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
 149         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
 150         CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
 151         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
 152         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
 153         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
 154         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
 155         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
 156         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
 157         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
 158         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
 159         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck,   CK_343X),
 160         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck,   CK_343X),
 161         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
 162         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick,  CK_343X),
 163         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
 164         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
 165         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
 166         CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
 167         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
 168         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
 169         CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
 170         CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
 171         CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
 172         CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
 173         CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
 174         CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
 175         CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
 176         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
 177         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
 178         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
 179         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
 180         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
 181         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
 182         CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
 183         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
 184         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
 185         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
 186         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
 187         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
 188         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
 189         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
 190         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
 191         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
 192         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
 193         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
 194         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
 195         CLK(NULL,       "ssi_ick",      &ssi_ick,       CK_343X),
 196         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
 197         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
 198         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
 199         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
 200         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
 201         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
 202         CLK(NULL,       "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
 203         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_343X),
 204         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_343X),
 205         CLK(NULL,       "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
 206         CLK(NULL,       "dss_ick",      &dss_ick,       CK_343X),
 207         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
 208         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
 209         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
 210         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
 211         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
 212         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
 213         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
 214         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
 215         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
 216         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
 217         CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
 218         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
 219         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
 220         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
 221         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
 222         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
 223         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
 224         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
 225         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
 226         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
 227         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
 228         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
 229         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
 230         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
 231         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
 232         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
 233         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
 234         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
 235         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
 236         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
 237         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
 238         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
 239         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
 240         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
 241         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
 242         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
 243         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
 244         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
 245         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
 246         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
 247         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
 248         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
 249         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
 250         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
 251         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
 252         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
 253         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
 254         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
 255         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
 256         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
 257         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
 258         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
 259         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
 260         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
 261         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
 262         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
 263         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
 264         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
 265         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
 266         CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_343X),
 267         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
 268         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
 269         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
 270         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
 271         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
 272         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
 273         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
 274         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
 275         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
 276         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
 277         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
 278 };
 279
 280 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
 281 #define DPLL_AUTOIDLE_DISABLE                   0x0
 282 #define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
 283
 284 #define MAX_DPLL_WAIT_TRIES             1000000
 285
 286 /**
 287  * omap3_dpll_recalc - recalculate DPLL rate
 288  * @clk: DPLL struct clk
 289  *
 290  * Recalculate and propagate the DPLL rate.
 291  */
 292 static void omap3_dpll_recalc(struct clk *clk)
 293 {
 294         clk->rate = omap2_get_dpll_rate(clk);
 295 }
 296
 297 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
 298 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 299 {
 300         const struct dpll_data *dd;
 301         u32 v;
 302
 303         dd = clk->dpll_data;
 304
 305         v = __raw_readl(dd->control_reg);
 306         v &= ~dd->enable_mask;
 307         v |= clken_bits << __ffs(dd->enable_mask);
 308         __raw_writel(v, dd->control_reg);
 309 }
 310
 311 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
 312 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 313 {
 314         const struct dpll_data *dd;
 315         int i = 0;
 316         int ret = -EINVAL;
 317         u32 idlest_mask;
 318
 319         dd = clk->dpll_data;
 320
 321         state <<= dd->idlest_bit;
 322         idlest_mask = 1 << dd->idlest_bit;
 323
 324         while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
 325                i < MAX_DPLL_WAIT_TRIES) {
 326                 i++;
 327                 udelay(1);
 328         }
 329
 330         if (i == MAX_DPLL_WAIT_TRIES) {
 331                 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
 332                        clk->name, (state) ? "locked" : "bypassed");
 333         } else {
 334                 pr_debug("clock: %s transition to '%s' in %d loops\n",
 335                          clk->name, (state) ? "locked" : "bypassed", i);
 336
 337                 ret = 0;
 338         }
 339
 340         return ret;
 341 }
 342
 343 /* From 3430 TRM ES2 4.7.6.2 */
 344 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
 345 {
 346         unsigned long fint;
 347         u16 f = 0;
 348
 349         fint = clk->parent->rate / (n + 1);
 350
 351         pr_debug("clock: fint is %lu\n", fint);
 352
 353         if (fint >= 750000 && fint <= 1000000)
 354                 f = 0x3;
 355         else if (fint > 1000000 && fint <= 1250000)
 356                 f = 0x4;
 357         else if (fint > 1250000 && fint <= 1500000)
 358                 f = 0x5;
 359         else if (fint > 1500000 && fint <= 1750000)
 360                 f = 0x6;
 361         else if (fint > 1750000 && fint <= 2100000)
 362                 f = 0x7;
 363         else if (fint > 7500000 && fint <= 10000000)
 364                 f = 0xB;
 365         else if (fint > 10000000 && fint <= 12500000)
 366                 f = 0xC;
 367         else if (fint > 12500000 && fint <= 15000000)
 368                 f = 0xD;
 369         else if (fint > 15000000 && fint <= 17500000)
 370                 f = 0xE;
 371         else if (fint > 17500000 && fint <= 21000000)
 372                 f = 0xF;
 373         else
 374                 pr_debug("clock: unknown freqsel setting for %d\n", n);
 375
 376         return f;
 377 }
 378
 379 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
 380
 381 /*
 382  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
 383  * @clk: pointer to a DPLL struct clk
 384  *
 385  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
 386  * readiness before returning.  Will save and restore the DPLL's
 387  * autoidle state across the enable, per the CDP code.  If the DPLL
 388  * locked successfully, return 0; if the DPLL did not lock in the time
 389  * allotted, or DPLL3 was passed in, return -EINVAL.
 390  */
 391 static int _omap3_noncore_dpll_lock(struct clk *clk)
 392 {
 393         u8 ai;
 394         int r;
 395
 396         if (clk == &dpll3_ck)
 397                 return -EINVAL;
 398
 399         pr_debug("clock: locking DPLL %s\n", clk->name);
 400
 401         ai = omap3_dpll_autoidle_read(clk);
 402
 403         _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 404
 405         if (ai) {
 406                 /*
 407                  * If no downstream clocks are enabled, CM_IDLEST bit
 408                  * may never become active, so don't wait for DPLL to lock.
 409                  */
 410                 r = 0;
 411                 omap3_dpll_allow_idle(clk);
 412         } else {
 413                 r = _omap3_wait_dpll_status(clk, 1);
 414                 omap3_dpll_deny_idle(clk);
 415         };
 416
 417         return r;
 418 }
 419
 420 /*
 421  * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
 422  * @clk: pointer to a DPLL struct clk
 423  *
 424  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
 425  * bypass mode, the DPLL's rate is set equal to its parent clock's
 426  * rate.  Waits for the DPLL to report readiness before returning.
 427  * Will save and restore the DPLL's autoidle state across the enable,
 428  * per the CDP code.  If the DPLL entered bypass mode successfully,
 429  * return 0; if the DPLL did not enter bypass in the time allotted, or
 430  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
 431  * return -EINVAL.
 432  */
 433 static int _omap3_noncore_dpll_bypass(struct clk *clk)
 434 {
 435         int r;
 436         u8 ai;
 437
 438         if (clk == &dpll3_ck)
 439                 return -EINVAL;
 440
 441         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
 442                 return -EINVAL;
 443
 444         pr_debug("clock: configuring DPLL %s for low-power bypass\n",
 445                  clk->name);
 446
 447         ai = omap3_dpll_autoidle_read(clk);
 448
 449         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
 450
 451         r = _omap3_wait_dpll_status(clk, 0);
 452
 453         if (ai)
 454                 omap3_dpll_allow_idle(clk);
 455         else
 456                 omap3_dpll_deny_idle(clk);
 457
 458         return r;
 459 }
 460
 461 /*
 462  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
 463  * @clk: pointer to a DPLL struct clk
 464  *
 465  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
 466  * restore the DPLL's autoidle state across the stop, per the CDP
 467  * code.  If DPLL3 was passed in, or the DPLL does not support
 468  * low-power stop, return -EINVAL; otherwise, return 0.
 469  */
 470 static int _omap3_noncore_dpll_stop(struct clk *clk)
 471 {
 472         u8 ai;
 473
 474         if (clk == &dpll3_ck)
 475                 return -EINVAL;
 476
 477         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
 478                 return -EINVAL;
 479
 480         pr_debug("clock: stopping DPLL %s\n", clk->name);
 481
 482         ai = omap3_dpll_autoidle_read(clk);
 483
 484         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
 485
 486         if (ai)
 487                 omap3_dpll_allow_idle(clk);
 488         else
 489                 omap3_dpll_deny_idle(clk);
 490
 491         return 0;
 492 }
 493
 494 /**
 495  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 496  * @clk: pointer to a DPLL struct clk
 497  *
 498  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 499  * The choice of modes depends on the DPLL's programmed rate: if it is
 500  * the same as the DPLL's parent clock, it will enter bypass;
 501  * otherwise, it will enter lock.  This code will wait for the DPLL to
 502  * indicate readiness before returning, unless the DPLL takes too long
 503  * to enter the target state.  Intended to be used as the struct clk's
 504  * enable function.  If DPLL3 was passed in, or the DPLL does not
 505  * support low-power stop, or if the DPLL took too long to enter
 506  * bypass or lock, return -EINVAL; otherwise, return 0.
 507  */
 508 static int omap3_noncore_dpll_enable(struct clk *clk)
 509 {
 510         int r;
 511
 512         if (clk == &dpll3_ck)
 513                 return -EINVAL;
 514
 515         if (clk->parent->rate == omap2_get_dpll_rate(clk))
 516                 r = _omap3_noncore_dpll_bypass(clk);
 517         else
 518                 r = _omap3_noncore_dpll_lock(clk);
 519
 520         return r;
 521 }
 522
 523 /**
 524  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 525  * @clk: pointer to a DPLL struct clk
 526  *
 527  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 528  * The choice of modes depends on the DPLL's programmed rate: if it is
 529  * the same as the DPLL's parent clock, it will enter bypass;
 530  * otherwise, it will enter lock.  This code will wait for the DPLL to
 531  * indicate readiness before returning, unless the DPLL takes too long
 532  * to enter the target state.  Intended to be used as the struct clk's
 533  * enable function.  If DPLL3 was passed in, or the DPLL does not
 534  * support low-power stop, or if the DPLL took too long to enter
 535  * bypass or lock, return -EINVAL; otherwise, return 0.
 536  */
 537 static void omap3_noncore_dpll_disable(struct clk *clk)
 538 {
 539         if (clk == &dpll3_ck)
 540                 return;
 541
 542         _omap3_noncore_dpll_stop(clk);
 543 }
 544
 545
 546 /* Non-CORE DPLL rate set code */
 547
 548 /*
 549  * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 550  * @clk: struct clk * of DPLL to set
 551  * @m: DPLL multiplier to set
 552  * @n: DPLL divider to set
 553  * @freqsel: FREQSEL value to set
 554  *
 555  * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 556  * lock..  Returns -EINVAL upon error, or 0 upon success.
 557  */
 558 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 559 {
 560         struct dpll_data *dd = clk->dpll_data;
 561         u32 v;
 562
 563         /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
 564         _omap3_noncore_dpll_bypass(clk);
 565
 566         v = __raw_readl(dd->mult_div1_reg);
 567         v &= ~(dd->mult_mask | dd->div1_mask);
 568
 569         /* Set mult (M), div1 (N), freqsel */
 570         v |= m << __ffs(dd->mult_mask);
 571         v |= n << __ffs(dd->div1_mask);
 572         v |= freqsel << __ffs(dd->freqsel_mask);
 573
 574         __raw_writel(v, dd->mult_div1_reg);
 575
 576         /* We let the clock framework set the other output dividers later */
 577
 578         /* REVISIT: Set ramp-up delay? */
 579
 580         _omap3_noncore_dpll_lock(clk);
 581
 582         return 0;
 583 }
 584
 585 /**
 586  * omap3_noncore_dpll_set_rate - set non-core DPLL rate
 587  * @clk: struct clk * of DPLL to set
 588  * @rate: rounded target rate
 589  *
 590  * Program the DPLL with the rounded target rate.  Returns -EINVAL upon
 591  * error, or 0 upon success.
 592  */
 593 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 594 {
 595         u16 freqsel;
 596         struct dpll_data *dd;
 597
 598         if (!clk || !rate)
 599                 return -EINVAL;
 600
 601         dd = clk->dpll_data;
 602         if (!dd)
 603                 return -EINVAL;
 604
 605         if (rate == omap2_get_dpll_rate(clk))
 606                 return 0;
 607
 608         if (dd->last_rounded_rate != rate)
 609                 omap2_dpll_round_rate(clk, rate);
 610
 611         if (dd->last_rounded_rate == 0)
 612                 return -EINVAL;
 613
 614         freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
 615         if (!freqsel)
 616                 WARN_ON(1);
 617
 618         omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n,
 619                                    freqsel);
 620
 621         omap3_dpll_recalc(clk);
 622
 623         return 0;
 624 }
 625
 626 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 627 {
 628         /*
 629          * According to the 12-5 CDP code from TI, "Limitation 2.5"
 630          * on 3430ES1 prevents us from changing DPLL multipliers or dividers
 631          * on DPLL4.
 632          */
 633         if (omap_rev() == OMAP3430_REV_ES1_0) {
 634                 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
 635                        "silicon 'Limitation 2.5' on 3430ES1.\n");
 636                 return -EINVAL;
 637         }
 638         return omap3_noncore_dpll_set_rate(clk, rate);
 639 }
 640
 641 static const struct clkops clkops_noncore_dpll_ops = {
 642         .enable         = &omap3_noncore_dpll_enable,
 643         .disable        = &omap3_noncore_dpll_disable,
 644 };
 645
 646 /* DPLL autoidle read/set code */
 647
 648
 649 /**
 650  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
 651  * @clk: struct clk * of the DPLL to read
 652  *
 653  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
 654  * -EINVAL if passed a null pointer or if the struct clk does not
 655  * appear to refer to a DPLL.
 656  */
 657 static u32 omap3_dpll_autoidle_read(struct clk *clk)
 658 {
 659         const struct dpll_data *dd;
 660         u32 v;
 661
 662         if (!clk || !clk->dpll_data)
 663                 return -EINVAL;
 664
 665         dd = clk->dpll_data;
 666
 667         v = __raw_readl(dd->autoidle_reg);
 668         v &= dd->autoidle_mask;
 669         v >>= __ffs(dd->autoidle_mask);
 670
 671         return v;
 672 }
 673
 674 /**
 675  * omap3_dpll_allow_idle - enable DPLL autoidle bits
 676  * @clk: struct clk * of the DPLL to operate on
 677  *
 678  * Enable DPLL automatic idle control.  This automatic idle mode
 679  * switching takes effect only when the DPLL is locked, at least on
 680  * OMAP3430.  The DPLL will enter low-power stop when its downstream
 681  * clocks are gated.  No return value.
 682  */
 683 static void omap3_dpll_allow_idle(struct clk *clk)
 684 {
 685         const struct dpll_data *dd;
 686         u32 v;
 687
 688         if (!clk || !clk->dpll_data)
 689                 return;
 690
 691         dd = clk->dpll_data;
 692
 693         /*
 694          * REVISIT: CORE DPLL can optionally enter low-power bypass
 695          * by writing 0x5 instead of 0x1.  Add some mechanism to
 696          * optionally enter this mode.
 697          */
 698         v = __raw_readl(dd->autoidle_reg);
 699         v &= ~dd->autoidle_mask;
 700         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
 701         __raw_writel(v, dd->autoidle_reg);
 702 }
 703
 704 /**
 705  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
 706  * @clk: struct clk * of the DPLL to operate on
 707  *
 708  * Disable DPLL automatic idle control.  No return value.
 709  */
 710 static void omap3_dpll_deny_idle(struct clk *clk)
 711 {
 712         const struct dpll_data *dd;
 713         u32 v;
 714
 715         if (!clk || !clk->dpll_data)
 716                 return;
 717
 718         dd = clk->dpll_data;
 719
 720         v = __raw_readl(dd->autoidle_reg);
 721         v &= ~dd->autoidle_mask;
 722         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
 723         __raw_writel(v, dd->autoidle_reg);
 724 }
 725
 726 /* Clock control for DPLL outputs */
 727
 728 /**
 729  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
 730  * @clk: DPLL output struct clk
 731  *
 732  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
 733  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
 734  */
 735 static void omap3_clkoutx2_recalc(struct clk *clk)
 736 {
 737         const struct dpll_data *dd;
 738         u32 v;
 739         struct clk *pclk;
 740
 741         /* Walk up the parents of clk, looking for a DPLL */
 742         pclk = clk->parent;
 743         while (pclk && !pclk->dpll_data)
 744                 pclk = pclk->parent;
 745
 746         /* clk does not have a DPLL as a parent? */
 747         WARN_ON(!pclk);
 748
 749         dd = pclk->dpll_data;
 750
 751         WARN_ON(!dd->control_reg || !dd->enable_mask);
 752
 753         v = __raw_readl(dd->control_reg) & dd->enable_mask;
 754         v >>= __ffs(dd->enable_mask);
 755         if (v != DPLL_LOCKED)
 756                 clk->rate = clk->parent->rate;
 757         else
 758                 clk->rate = clk->parent->rate * 2;
 759 }
 760
 761 /* Common clock code */
 762
 763 /*
 764  * As it is structured now, this will prevent an OMAP2/3 multiboot
 765  * kernel from compiling.  This will need further attention.
 766  */
 767 #if defined(CONFIG_ARCH_OMAP3)
 768
 769 static struct clk_functions omap2_clk_functions = {
 770         .clk_enable             = omap2_clk_enable,
 771         .clk_disable            = omap2_clk_disable,
 772         .clk_round_rate         = omap2_clk_round_rate,
 773         .clk_set_rate           = omap2_clk_set_rate,
 774         .clk_set_parent         = omap2_clk_set_parent,
 775         .clk_disable_unused     = omap2_clk_disable_unused,
 776 };
 777
 778 /*
 779  * Set clocks for bypass mode for reboot to work.
 780  */
 781 void omap2_clk_prepare_for_reboot(void)
 782 {
 783         /* REVISIT: Not ready for 343x */
 784 #if 0
 785         u32 rate;
 786
 787         if (vclk == NULL || sclk == NULL)
 788                 return;
 789
 790         rate = clk_get_rate(sclk);
 791         clk_set_rate(vclk, rate);
 792 #endif
 793 }
 794
 795 /* REVISIT: Move this init stuff out into clock.c */
 796
 797 /*
 798  * Switch the MPU rate if specified on cmdline.
 799  * We cannot do this early until cmdline is parsed.
 800  */
 801 static int __init omap2_clk_arch_init(void)
 802 {
 803         if (!mpurate)
 804                 return -EINVAL;
 805
 806         /* REVISIT: not yet ready for 343x */
 807 #if 0
 808         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
 809                 printk(KERN_ERR "Could not find matching MPU rate\n");
 810 #endif
 811
 812         recalculate_root_clocks();
 813
 814         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
 815                "%ld.%01ld/%ld/%ld MHz\n",
 816                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
 817                (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
 818
 819         return 0;
 820 }
 821 arch_initcall(omap2_clk_arch_init);
 822
 823 int __init omap2_clk_init(void)
 824 {
 825         /* struct prcm_config *prcm; */
 826         struct omap_clk *c;
 827         /* u32 clkrate; */
 828         u32 cpu_clkflg;
 829
 830         if (cpu_is_omap34xx()) {
 831                 cpu_mask = RATE_IN_343X;
 832                 cpu_clkflg = CK_343X;
 833
 834                 /*
 835                  * Update this if there are further clock changes between ES2
 836                  * and production parts
 837                  */
 838                 if (omap_rev() == OMAP3430_REV_ES1_0) {
 839                         /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
 840                         cpu_clkflg |= CK_3430ES1;
 841                 } else {
 842                         cpu_mask |= RATE_IN_3430ES2;
 843                         cpu_clkflg |= CK_3430ES2;
 844                 }
 845         }
 846
 847         clk_init(&omap2_clk_functions);
 848
 849         for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
 850                 if (c->cpu & cpu_clkflg) {
 851                         clkdev_add(&c->lk);
 852                         clk_register(c->lk.clk);
 853                         omap2_init_clk_clkdm(c->lk.clk);
 854                 }
 855
 856         /* REVISIT: Not yet ready for OMAP3 */
 857 #if 0
 858         /* Check the MPU rate set by bootloader */
 859         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
 860         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 861                 if (!(prcm->flags & cpu_mask))
 862                         continue;
 863                 if (prcm->xtal_speed != sys_ck.rate)
 864                         continue;
 865                 if (prcm->dpll_speed <= clkrate)
 866                          break;
 867         }
 868         curr_prcm_set = prcm;
 869 #endif
 870
 871         recalculate_root_clocks();
 872
 873         printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
 874                "%ld.%01ld/%ld/%ld MHz\n",
 875                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
 876                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
 877
 878         /*
 879          * Only enable those clocks we will need, let the drivers
 880          * enable other clocks as necessary
 881          */
 882         clk_enable_init_clocks();
 883
 884         /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
 885         /* REVISIT: not yet ready for 343x */
 886 #if 0
 887         vclk = clk_get(NULL, "virt_prcm_set");
 888         sclk = clk_get(NULL, "sys_ck");
 889 #endif
 890         return 0;
 891 }
 892
 893 #endif