2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
30 #include <mach/clock.h>
31 #include <mach/sram.h>
32 #include <asm/div64.h>
34 #include <mach/sdrc.h>
36 #include "clock34xx.h"
38 #include "prm-regbits-34xx.h"
40 #include "cm-regbits-34xx.h"
42 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
43 #define DPLL_AUTOIDLE_DISABLE 0x0
44 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
46 #define MAX_DPLL_WAIT_TRIES 1000000
49 * omap3_dpll_recalc - recalculate DPLL rate
50 * @clk: DPLL struct clk
52 * Recalculate and propagate the DPLL rate.
54 static void omap3_dpll_recalc(struct clk *clk)
56 clk->rate = omap2_get_dpll_rate(clk);
59 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
62 const struct dpll_data *dd;
67 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
68 v &= ~dd->enable_mask;
69 v |= clken_bits << __ffs(dd->enable_mask);
70 cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
73 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
74 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
76 const struct dpll_data *dd;
82 state <<= __ffs(dd->idlest_mask);
84 while (((cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg)
85 & dd->idlest_mask) != state) &&
86 i < MAX_DPLL_WAIT_TRIES) {
91 if (i == MAX_DPLL_WAIT_TRIES) {
92 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
93 clk->name, (state) ? "locked" : "bypassed");
95 pr_debug("clock: %s transition to '%s' in %d loops\n",
96 clk->name, (state) ? "locked" : "bypassed", i);
104 /* From 3430 TRM ES2 4.7.6.2 */
105 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
110 fint = clk->parent->rate / (n + 1);
112 pr_debug("clock: fint is %lu\n", fint);
114 if (fint >= 750000 && fint <= 1000000)
116 else if (fint > 1000000 && fint <= 1250000)
118 else if (fint > 1250000 && fint <= 1500000)
120 else if (fint > 1500000 && fint <= 1750000)
122 else if (fint > 1750000 && fint <= 2100000)
124 else if (fint > 7500000 && fint <= 10000000)
126 else if (fint > 10000000 && fint <= 12500000)
128 else if (fint > 12500000 && fint <= 15000000)
130 else if (fint > 15000000 && fint <= 17500000)
132 else if (fint > 17500000 && fint <= 21000000)
135 pr_debug("clock: unknown freqsel setting for %d\n", n);
140 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
143 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
144 * @clk: pointer to a DPLL struct clk
146 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
147 * readiness before returning. Will save and restore the DPLL's
148 * autoidle state across the enable, per the CDP code. If the DPLL
149 * locked successfully, return 0; if the DPLL did not lock in the time
150 * allotted, or DPLL3 was passed in, return -EINVAL.
152 static int _omap3_noncore_dpll_lock(struct clk *clk)
157 if (clk == &dpll3_ck)
160 pr_debug("clock: locking DPLL %s\n", clk->name);
162 ai = omap3_dpll_autoidle_read(clk);
164 omap3_dpll_deny_idle(clk);
166 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
168 r = _omap3_wait_dpll_status(clk, 1);
171 omap3_dpll_allow_idle(clk);
177 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
178 * @clk: pointer to a DPLL struct clk
180 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
181 * bypass mode, the DPLL's rate is set equal to its parent clock's
182 * rate. Waits for the DPLL to report readiness before returning.
183 * Will save and restore the DPLL's autoidle state across the enable,
184 * per the CDP code. If the DPLL entered bypass mode successfully,
185 * return 0; if the DPLL did not enter bypass in the time allotted, or
186 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
189 static int _omap3_noncore_dpll_bypass(struct clk *clk)
194 if (clk == &dpll3_ck)
197 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
200 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
203 ai = omap3_dpll_autoidle_read(clk);
205 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
207 r = _omap3_wait_dpll_status(clk, 0);
210 omap3_dpll_allow_idle(clk);
212 omap3_dpll_deny_idle(clk);
218 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
219 * @clk: pointer to a DPLL struct clk
221 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
222 * restore the DPLL's autoidle state across the stop, per the CDP
223 * code. If DPLL3 was passed in, or the DPLL does not support
224 * low-power stop, return -EINVAL; otherwise, return 0.
226 static int _omap3_noncore_dpll_stop(struct clk *clk)
230 if (clk == &dpll3_ck)
233 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
236 pr_debug("clock: stopping DPLL %s\n", clk->name);
238 ai = omap3_dpll_autoidle_read(clk);
240 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
243 omap3_dpll_allow_idle(clk);
245 omap3_dpll_deny_idle(clk);
251 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
252 * @clk: pointer to a DPLL struct clk
254 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
255 * The choice of modes depends on the DPLL's programmed rate: if it is
256 * the same as the DPLL's parent clock, it will enter bypass;
257 * otherwise, it will enter lock. This code will wait for the DPLL to
258 * indicate readiness before returning, unless the DPLL takes too long
259 * to enter the target state. Intended to be used as the struct clk's
260 * enable function. If DPLL3 was passed in, or the DPLL does not
261 * support low-power stop, or if the DPLL took too long to enter
262 * bypass or lock, return -EINVAL; otherwise, return 0.
264 static int omap3_noncore_dpll_enable(struct clk *clk)
267 struct dpll_data *dd;
269 if (clk == &dpll3_ck)
276 if (clk->rate == dd->bypass_clk->rate)
277 r = _omap3_noncore_dpll_bypass(clk);
279 r = _omap3_noncore_dpll_lock(clk);
282 clk->rate = omap2_get_dpll_rate(clk);
288 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
289 * @clk: pointer to a DPLL struct clk
291 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
292 * The choice of modes depends on the DPLL's programmed rate: if it is
293 * the same as the DPLL's parent clock, it will enter bypass;
294 * otherwise, it will enter lock. This code will wait for the DPLL to
295 * indicate readiness before returning, unless the DPLL takes too long
296 * to enter the target state. Intended to be used as the struct clk's
297 * enable function. If DPLL3 was passed in, or the DPLL does not
298 * support low-power stop, or if the DPLL took too long to enter
299 * bypass or lock, return -EINVAL; otherwise, return 0.
301 static void omap3_noncore_dpll_disable(struct clk *clk)
303 if (clk == &dpll3_ck)
306 _omap3_noncore_dpll_stop(clk);
310 /* Non-CORE DPLL rate set code */
313 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
314 * @clk: struct clk * of DPLL to set
315 * @m: DPLL multiplier to set
316 * @n: DPLL divider to set
317 * @freqsel: FREQSEL value to set
319 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
320 * lock.. Returns -EINVAL upon error, or 0 upon success.
322 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
324 struct dpll_data *dd;
335 * According to the 12-5 CDP code from TI, "Limitation 2.5"
336 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
339 if (omap_rev() == OMAP3430_REV_ES1_0 &&
340 !strcmp("dpll4_ck", clk->name)) {
341 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
342 "silicon 'Limitation 2.5' on 3430ES1.\n");
346 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
347 _omap3_noncore_dpll_bypass(clk);
349 /* Set jitter correction */
350 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
351 v &= ~dd->freqsel_mask;
352 v |= freqsel << __ffs(dd->freqsel_mask);
353 cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
355 /* Set DPLL multiplier, divider */
356 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
357 v &= ~(dd->mult_mask | dd->div1_mask);
358 v |= m << __ffs(dd->mult_mask);
359 v |= (n - 1) << __ffs(dd->div1_mask);
360 cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg);
362 /* We let the clock framework set the other output dividers later */
364 /* REVISIT: Set ramp-up delay? */
366 _omap3_noncore_dpll_lock(clk);
372 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
373 * @clk: struct clk * of DPLL to set
374 * @rate: rounded target rate
376 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
377 * low-power bypass, and the target rate is the bypass source clock
378 * rate, then configure the DPLL for bypass. Otherwise, round the
379 * target rate if it hasn't been done already, then program and lock
380 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
382 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
385 struct dpll_data *dd;
395 if (rate == omap2_get_dpll_rate(clk))
398 if (dd->bypass_clk->rate == rate &&
399 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
401 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
403 ret = _omap3_noncore_dpll_bypass(clk);
409 if (dd->last_rounded_rate != rate)
410 omap2_dpll_round_rate(clk, rate);
412 if (dd->last_rounded_rate == 0)
415 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
419 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
422 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
423 dd->last_rounded_n, freqsel);
435 * CORE DPLL (DPLL3) rate programming functions
437 * These call into SRAM code to do the actual CM writes, since the SDRAM
438 * is clocked from DPLL3.
442 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
443 * @clk: struct clk * of DPLL to set
444 * @rate: rounded target rate
446 * Program the DPLL M2 divider with the rounded target rate. Returns
447 * -EINVAL upon error, or 0 upon success.
449 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
452 unsigned long validrate, sdrcrate;
453 struct omap_sdrc_params *sp;
458 if (clk != &dpll3_m2_ck)
461 if (rate == clk->rate)
464 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
465 if (validrate != rate)
468 sdrcrate = sdrc_ick.rate;
469 if (rate > clk->rate)
470 sdrcrate <<= ((rate / clk->rate) - 1);
472 sdrcrate >>= ((clk->rate / rate) - 1);
474 sp = omap2_sdrc_get_params(sdrcrate);
478 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
480 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
481 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
483 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
484 WARN_ON(new_div != 1 && new_div != 2);
486 /* REVISIT: Add SDRC_MR changing to this code also */
488 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
489 sp->actim_ctrlb, new_div);
496 /* DPLL autoidle read/set code */
500 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
501 * @clk: struct clk * of the DPLL to read
503 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
504 * -EINVAL if passed a null pointer or if the struct clk does not
505 * appear to refer to a DPLL.
507 static u32 omap3_dpll_autoidle_read(struct clk *clk)
509 const struct dpll_data *dd;
512 if (!clk || !clk->dpll_data)
517 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
518 v &= dd->autoidle_mask;
519 v >>= __ffs(dd->autoidle_mask);
525 * omap3_dpll_allow_idle - enable DPLL autoidle bits
526 * @clk: struct clk * of the DPLL to operate on
528 * Enable DPLL automatic idle control. This automatic idle mode
529 * switching takes effect only when the DPLL is locked, at least on
530 * OMAP3430. The DPLL will enter low-power stop when its downstream
531 * clocks are gated. No return value.
533 static void omap3_dpll_allow_idle(struct clk *clk)
535 const struct dpll_data *dd;
538 if (!clk || !clk->dpll_data)
544 * REVISIT: CORE DPLL can optionally enter low-power bypass
545 * by writing 0x5 instead of 0x1. Add some mechanism to
546 * optionally enter this mode.
548 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
549 v &= ~dd->autoidle_mask;
550 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
551 cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
555 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
556 * @clk: struct clk * of the DPLL to operate on
558 * Disable DPLL automatic idle control. No return value.
560 static void omap3_dpll_deny_idle(struct clk *clk)
562 const struct dpll_data *dd;
565 if (!clk || !clk->dpll_data)
570 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
571 v &= ~dd->autoidle_mask;
572 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
573 cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
576 /* Clock control for DPLL outputs */
579 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
580 * @clk: DPLL output struct clk
582 * Using parent clock DPLL data, look up DPLL state. If locked, set our
583 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
585 static void omap3_clkoutx2_recalc(struct clk *clk)
587 const struct dpll_data *dd;
591 /* Walk up the parents of clk, looking for a DPLL */
593 while (pclk && !pclk->dpll_data)
596 /* clk does not have a DPLL as a parent? */
599 dd = pclk->dpll_data;
601 WARN_ON(!dd->enable_mask);
603 v = cm_read_mod_reg(pclk->prcm_mod, dd->control_reg) & dd->enable_mask;
604 v >>= __ffs(dd->enable_mask);
605 if (v != OMAP3XXX_EN_DPLL_LOCKED)
606 clk->rate = clk->parent->rate;
608 clk->rate = clk->parent->rate * 2;
611 /* Common clock code */
614 * As it is structured now, this will prevent an OMAP2/3 multiboot
615 * kernel from compiling. This will need further attention.
617 #if defined(CONFIG_ARCH_OMAP3)
619 static struct clk_functions omap2_clk_functions = {
620 .clk_enable = omap2_clk_enable,
621 .clk_disable = omap2_clk_disable,
622 .clk_round_rate = omap2_clk_round_rate,
623 .clk_set_rate = omap2_clk_set_rate,
624 .clk_set_parent = omap2_clk_set_parent,
625 .clk_get_parent = omap2_clk_get_parent,
626 .clk_disable_unused = omap2_clk_disable_unused,
630 * Set clocks for bypass mode for reboot to work.
632 void omap2_clk_prepare_for_reboot(void)
634 /* REVISIT: Not ready for 343x */
638 if (vclk == NULL || sclk == NULL)
641 rate = clk_get_rate(sclk);
642 clk_set_rate(vclk, rate);
646 /* REVISIT: Move this init stuff out into clock.c */
649 * Switch the MPU rate if specified on cmdline.
650 * We cannot do this early until cmdline is parsed.
652 static int __init omap2_clk_arch_init(void)
657 /* REVISIT: not yet ready for 343x */
659 if (clk_set_rate(&virt_prcm_set, mpurate))
660 printk(KERN_ERR "Could not find matching MPU rate\n");
663 recalculate_root_clocks();
665 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
666 "%ld.%01ld/%ld/%ld MHz\n",
667 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
668 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
672 arch_initcall(omap2_clk_arch_init);
674 int __init omap2_clk_init(void)
676 /* struct prcm_config *prcm; */
681 /* REVISIT: Ultimately this will be used for multiboot */
683 if (cpu_is_omap242x()) {
684 cpu_mask = RATE_IN_242X;
685 cpu_clkflg = CLOCK_IN_OMAP242X;
686 clkp = onchip_24xx_clks;
687 } else if (cpu_is_omap2430()) {
688 cpu_mask = RATE_IN_243X;
689 cpu_clkflg = CLOCK_IN_OMAP243X;
690 clkp = onchip_24xx_clks;
693 if (cpu_is_omap34xx()) {
694 cpu_mask = RATE_IN_343X;
695 cpu_clkflg = CLOCK_IN_OMAP343X;
696 clkp = onchip_34xx_clks;
699 * Update this if there are further clock changes between ES2
700 * and production parts
702 if (omap_rev() == OMAP3430_REV_ES1_0) {
703 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
704 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
706 cpu_mask |= RATE_IN_3430ES2;
707 cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
711 clk_init(&omap2_clk_functions);
713 for (clkp = onchip_34xx_clks;
714 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
716 if ((*clkp)->flags & cpu_clkflg) {
718 omap2_init_clk_clkdm(*clkp);
722 /* REVISIT: Not yet ready for OMAP3 */
724 /* Check the MPU rate set by bootloader */
725 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
726 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
727 if (!(prcm->flags & cpu_mask))
729 if (prcm->xtal_speed != sys_ck.rate)
731 if (prcm->dpll_speed <= clkrate)
734 curr_prcm_set = prcm;
737 recalculate_root_clocks();
739 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
740 "%ld.%01ld/%ld/%ld MHz\n",
741 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
742 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
745 * Only enable those clocks we will need, let the drivers
746 * enable other clocks as necessary
748 clk_enable_init_clocks();
750 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
751 /* REVISIT: not yet ready for 343x */
753 vclk = clk_get(NULL, "virt_prcm_set");
754 sclk = clk_get(NULL, "sys_ck");