arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  35
  36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  37  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  38  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  39  */
  40 struct prcm_config {
  41         unsigned long xtal_speed;       /* crystal rate */
  42         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  43         unsigned long mpu_speed;        /* speed of MPU */
  44         unsigned long cm_clksel_mpu;    /* mpu divider */
  45         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  46         unsigned long cm_clksel_gfx;    /* gfx dividers */
  47         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  48         unsigned long cm_clksel1_pll;   /* m,n */
  49         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  50         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  51         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  52         unsigned char flags;
  53 };
  54
  55 /*
  56  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  57  * These configurations are characterized by voltage and speed for clocks.
  58  * The device is only validated for certain combinations. One way to express
  59  * these combinations is via the 'ratio's' which the clocks operate with
  60  * respect to each other. These ratio sets are for a given voltage/DPLL
  61  * setting. All configurations can be described by a DPLL setting and a ratio
  62  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  63  *
  64  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  65  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  66  * 2430 (iva2.1, NOdsp, mdm)
  67  */
  68
  69 /* Core fields for cm_clksel, not ratio governed */
  70 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  71 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  72 #define RX_CLKSEL_SSI                   (0x5 << 20)
  73
  74 /*-------------------------------------------------------------------------
  75  * Voltage/DPLL ratios
  76  *-------------------------------------------------------------------------*/
  77
  78 /* 2430 Ratio's, 2430-Ratio Config 1 */
  79 #define R1_CLKSEL_L3                    (4 << 0)
  80 #define R1_CLKSEL_L4                    (2 << 5)
  81 #define R1_CLKSEL_USB                   (4 << 25)
  82 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  83                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  84                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  85 #define R1_CLKSEL_MPU                   (2 << 0)
  86 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  87 #define R1_CLKSEL_DSP                   (2 << 0)
  88 #define R1_CLKSEL_DSP_IF                (2 << 5)
  89 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  90 #define R1_CLKSEL_GFX                   (2 << 0)
  91 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  92 #define R1_CLKSEL_MDM                   (4 << 0)
  93 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  94
  95 /* 2430-Ratio Config 2 */
  96 #define R2_CLKSEL_L3                    (6 << 0)
  97 #define R2_CLKSEL_L4                    (2 << 5)
  98 #define R2_CLKSEL_USB                   (2 << 25)
  99 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 100                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 101                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 102 #define R2_CLKSEL_MPU                   (2 << 0)
 103 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 104 #define R2_CLKSEL_DSP                   (2 << 0)
 105 #define R2_CLKSEL_DSP_IF                (3 << 5)
 106 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 107 #define R2_CLKSEL_GFX                   (2 << 0)
 108 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 109 #define R2_CLKSEL_MDM                   (6 << 0)
 110 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 111
 112 /* 2430-Ratio Bootm (BYPASS) */
 113 #define RB_CLKSEL_L3                    (1 << 0)
 114 #define RB_CLKSEL_L4                    (1 << 5)
 115 #define RB_CLKSEL_USB                   (1 << 25)
 116 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 117                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 118                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 119 #define RB_CLKSEL_MPU                   (1 << 0)
 120 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 121 #define RB_CLKSEL_DSP                   (1 << 0)
 122 #define RB_CLKSEL_DSP_IF                (1 << 5)
 123 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 124 #define RB_CLKSEL_GFX                   (1 << 0)
 125 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 126 #define RB_CLKSEL_MDM                   (1 << 0)
 127 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 128
 129 /* 2420 Ratio Equivalents */
 130 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 131 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 132
 133 /* 2420-PRCM III 532MHz core */
 134 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 135 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 136 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 137 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 138                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 139                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 140                                         RIII_CLKSEL_L3
 141 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 142 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 143 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 144 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 145 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 146 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 147 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 148 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 149                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 150                                         RIII_CLKSEL_DSP
 151 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 152 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 153
 154 /* 2420-PRCM II 600MHz core */
 155 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 156 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 157 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 158 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 159                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 160                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 161                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 162 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 163 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 164 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 165 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 166 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 167 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 168 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 169 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 170                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 171                                         RII_CLKSEL_DSP
 172 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 173 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 174
 175 /* 2420-PRCM I 660MHz core */
 176 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 177 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 178 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 179 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 180                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 181                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 182                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 183 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 184 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 185 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 186 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 187 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 188 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 189 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 190 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 191                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 192                                         RI_CLKSEL_DSP
 193 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 194 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 195
 196 /* 2420-PRCM VII (boot) */
 197 #define RVII_CLKSEL_L3                  (1 << 0)
 198 #define RVII_CLKSEL_L4                  (1 << 5)
 199 #define RVII_CLKSEL_DSS1                (1 << 8)
 200 #define RVII_CLKSEL_DSS2                (0 << 13)
 201 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 202 #define RVII_CLKSEL_SSI                 (1 << 20)
 203 #define RVII_CLKSEL_USB                 (1 << 25)
 204
 205 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 206                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 207                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 208
 209 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 210 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 211
 212 #define RVII_CLKSEL_DSP                 (1 << 0)
 213 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 214 #define RVII_SYNC_DSP                   (0 << 7)
 215 #define RVII_CLKSEL_IVA                 (1 << 8)
 216 #define RVII_SYNC_IVA                   (0 << 13)
 217 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 218                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 219
 220 #define RVII_CLKSEL_GFX                 (1 << 0)
 221 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 222
 223 /*-------------------------------------------------------------------------
 224  * 2430 Target modes: Along with each configuration the CPU has several
 225  * modes which goes along with them. Modes mainly are the addition of
 226  * describe DPLL combinations to go along with a ratio.
 227  *-------------------------------------------------------------------------*/
 228
 229 /* Hardware governed */
 230 #define MX_48M_SRC                      (0 << 3)
 231 #define MX_54M_SRC                      (0 << 5)
 232 #define MX_APLLS_CLIKIN_12              (3 << 23)
 233 #define MX_APLLS_CLIKIN_13              (2 << 23)
 234 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 235
 236 /*
 237  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 238  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 239  */
 240 #define M5A_DPLL_MULT_12                (133 << 12)
 241 #define M5A_DPLL_DIV_12                 (5 << 8)
 242 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 243                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 244                                         MX_APLLS_CLIKIN_12
 245 #define M5A_DPLL_MULT_13                (61 << 12)
 246 #define M5A_DPLL_DIV_13                 (2 << 8)
 247 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 248                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 249                                         MX_APLLS_CLIKIN_13
 250 #define M5A_DPLL_MULT_19                (55 << 12)
 251 #define M5A_DPLL_DIV_19                 (3 << 8)
 252 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 253                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 254                                         MX_APLLS_CLIKIN_19_2
 255 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 256 #define M5B_DPLL_MULT_12                (50 << 12)
 257 #define M5B_DPLL_DIV_12                 (2 << 8)
 258 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 259                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 260                                         MX_APLLS_CLIKIN_12
 261 #define M5B_DPLL_MULT_13                (200 << 12)
 262 #define M5B_DPLL_DIV_13                 (12 << 8)
 263
 264 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 265                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 266                                         MX_APLLS_CLIKIN_13
 267 #define M5B_DPLL_MULT_19                (125 << 12)
 268 #define M5B_DPLL_DIV_19                 (31 << 8)
 269 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 270                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 271                                         MX_APLLS_CLIKIN_19_2
 272 /*
 273  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 274  */
 275 #define M4_DPLL_MULT_12                 (133 << 12)
 276 #define M4_DPLL_DIV_12                  (3 << 8)
 277 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 278                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 279                                         MX_APLLS_CLIKIN_12
 280
 281 #define M4_DPLL_MULT_13                 (399 << 12)
 282 #define M4_DPLL_DIV_13                  (12 << 8)
 283 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 284                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 285                                         MX_APLLS_CLIKIN_13
 286
 287 #define M4_DPLL_MULT_19                 (145 << 12)
 288 #define M4_DPLL_DIV_19                  (6 << 8)
 289 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 290                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 291                                         MX_APLLS_CLIKIN_19_2
 292
 293 /*
 294  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 295  */
 296 #define M3_DPLL_MULT_12                 (55 << 12)
 297 #define M3_DPLL_DIV_12                  (1 << 8)
 298 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 299                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 300                                         MX_APLLS_CLIKIN_12
 301 #define M3_DPLL_MULT_13                 (76 << 12)
 302 #define M3_DPLL_DIV_13                  (2 << 8)
 303 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 304                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 305                                         MX_APLLS_CLIKIN_13
 306 #define M3_DPLL_MULT_19                 (17 << 12)
 307 #define M3_DPLL_DIV_19                  (0 << 8)
 308 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 309                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 310                                         MX_APLLS_CLIKIN_19_2
 311
 312 /*
 313  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 314  */
 315 #define M2_DPLL_MULT_12                 (55 << 12)
 316 #define M2_DPLL_DIV_12                  (1 << 8)
 317 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 318                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 319                                         MX_APLLS_CLIKIN_12
 320
 321 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 322  * relock time issue */
 323 /* Core frequency changed from 330/165 to 329/164 MHz*/
 324 #define M2_DPLL_MULT_13                 (76 << 12)
 325 #define M2_DPLL_DIV_13                  (2 << 8)
 326 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 327                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 328                                         MX_APLLS_CLIKIN_13
 329
 330 #define M2_DPLL_MULT_19                 (17 << 12)
 331 #define M2_DPLL_DIV_19                  (0 << 8)
 332 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 333                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 334                                         MX_APLLS_CLIKIN_19_2
 335
 336 /* boot (boot) */
 337 #define MB_DPLL_MULT                    (1 << 12)
 338 #define MB_DPLL_DIV                     (0 << 8)
 339 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 340                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 341
 342 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 343                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 344
 345 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 346                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 347
 348 /*
 349  * 2430 - chassis (sedna)
 350  * 165 (ratio1) same as above #2
 351  * 150 (ratio1)
 352  * 133 (ratio2) same as above #4
 353  * 110 (ratio2) same as above #3
 354  * 104 (ratio2)
 355  * boot (boot)
 356  */
 357
 358 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 359 #define MI_DPLL_MULT_12                 (55 << 12)
 360 #define MI_DPLL_DIV_12                  (1 << 8)
 361 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 362                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 363                                         MX_APLLS_CLIKIN_12
 364
 365 /*
 366  * 2420 Equivalent - mode registers
 367  * PRCM II , target DPLL = 2*300MHz = 600MHz
 368  */
 369 #define MII_DPLL_MULT_12                (50 << 12)
 370 #define MII_DPLL_DIV_12                 (1 << 8)
 371 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 372                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 373                                         MX_APLLS_CLIKIN_12
 374 #define MII_DPLL_MULT_13                (300 << 12)
 375 #define MII_DPLL_DIV_13                 (12 << 8)
 376 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 377                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 378                                         MX_APLLS_CLIKIN_13
 379
 380 /* PRCM III target DPLL = 2*266 = 532MHz*/
 381 #define MIII_DPLL_MULT_12               (133 << 12)
 382 #define MIII_DPLL_DIV_12                (5 << 8)
 383 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 384                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 385                                         MX_APLLS_CLIKIN_12
 386 #define MIII_DPLL_MULT_13               (266 << 12)
 387 #define MIII_DPLL_DIV_13                (12 << 8)
 388 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 389                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 390                                         MX_APLLS_CLIKIN_13
 391
 392 /* PRCM VII (boot bypass) */
 393 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 394 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 395
 396 /* High and low operation value */
 397 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 398 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 399
 400 /* MPU speed defines */
 401 #define S12M    12000000
 402 #define S13M    13000000
 403 #define S19M    19200000
 404 #define S26M    26000000
 405 #define S100M   100000000
 406 #define S133M   133000000
 407 #define S150M   150000000
 408 #define S164M   164000000
 409 #define S165M   165000000
 410 #define S199M   199000000
 411 #define S200M   200000000
 412 #define S266M   266000000
 413 #define S300M   300000000
 414 #define S329M   329000000
 415 #define S330M   330000000
 416 #define S399M   399000000
 417 #define S400M   400000000
 418 #define S532M   532000000
 419 #define S600M   600000000
 420 #define S658M   658000000
 421 #define S660M   660000000
 422 #define S798M   798000000
 423
 424 /*-------------------------------------------------------------------------
 425  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 426  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 427  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 428  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 429  *
 430  * Filling in table based on H4 boards and 2430-SDPs variants available.
 431  * There are quite a few more rates combinations which could be defined.
 432  *
 433  * When multiple values are defined the start up will try and choose the
 434  * fastest one. If a 'fast' value is defined, then automatically, the /2
 435  * one should be included as it can be used.    Generally having more that
 436  * one fast set does not make sense, as static timings need to be changed
 437  * to change the set.    The exception is the bypass setting which is
 438  * availble for low power bypass.
 439  *
 440  * Note: This table needs to be sorted, fastest to slowest.
 441  *-------------------------------------------------------------------------*/
 442 static struct prcm_config rate_table[] = {
 443         /* PRCM I - FAST */
 444         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 445                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 446                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 447                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 448                 RATE_IN_242X},
 449
 450         /* PRCM II - FAST */
 451         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 452                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 453                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 454                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 455                 RATE_IN_242X},
 456
 457         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 458                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 459                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 460                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 461                 RATE_IN_242X},
 462
 463         /* PRCM III - FAST */
 464         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 465                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 466                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 467                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 468                 RATE_IN_242X},
 469
 470         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 471                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 472                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 473                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 474                 RATE_IN_242X},
 475
 476         /* PRCM II - SLOW */
 477         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 478                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 479                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 480                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 481                 RATE_IN_242X},
 482
 483         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 484                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 485                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 486                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 487                 RATE_IN_242X},
 488
 489         /* PRCM III - SLOW */
 490         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 491                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 492                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 493                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 494                 RATE_IN_242X},
 495
 496         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 497                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 498                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 499                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 500                 RATE_IN_242X},
 501
 502         /* PRCM-VII (boot-bypass) */
 503         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 504                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 505                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 506                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 507                 RATE_IN_242X},
 508
 509         /* PRCM-VII (boot-bypass) */
 510         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 511                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 512                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 513                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 514                 RATE_IN_242X},
 515
 516         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 517         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 518                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 519                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 520                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 521                 SDRC_RFR_CTRL_133MHz,
 522                 RATE_IN_243X},
 523
 524         /* PRCM #2 - ratio1 (ES2) - FAST */
 525         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 526                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 527                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 528                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 529                 SDRC_RFR_CTRL_165MHz,
 530                 RATE_IN_243X},
 531
 532         /* PRCM #5a - ratio1 - FAST */
 533         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 534                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 535                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 536                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 537                 SDRC_RFR_CTRL_133MHz,
 538                 RATE_IN_243X},
 539
 540         /* PRCM #5b - ratio1 - FAST */
 541         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 542                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 543                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 544                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 545                 SDRC_RFR_CTRL_100MHz,
 546                 RATE_IN_243X},
 547
 548         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 549         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 550                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 551                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 552                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 553                 SDRC_RFR_CTRL_133MHz,
 554                 RATE_IN_243X},
 555
 556         /* PRCM #2 - ratio1 (ES2) - SLOW */
 557         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 558                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 559                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 560                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 561                 SDRC_RFR_CTRL_165MHz,
 562                 RATE_IN_243X},
 563
 564         /* PRCM #5a - ratio1 - SLOW */
 565         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 566                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 567                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 568                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 569                 SDRC_RFR_CTRL_133MHz,
 570                 RATE_IN_243X},
 571
 572         /* PRCM #5b - ratio1 - SLOW*/
 573         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 574                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 575                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 576                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 577                 SDRC_RFR_CTRL_100MHz,
 578                 RATE_IN_243X},
 579
 580         /* PRCM-boot/bypass */
 581         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 582                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 583                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 584                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 585                 SDRC_RFR_CTRL_BYPASS,
 586                 RATE_IN_243X},
 587
 588         /* PRCM-boot/bypass */
 589         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 590                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 591                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 592                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 593                 SDRC_RFR_CTRL_BYPASS,
 594                 RATE_IN_243X},
 595
 596         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 597 };
 598
 599 /*-------------------------------------------------------------------------
 600  * 24xx clock tree.
 601  *
 602  * NOTE:In many cases here we are assigning a 'default' parent. In many
 603  *      cases the parent is selectable. The get/set parent calls will also
 604  *      switch sources.
 605  *
 606  *      Many some clocks say always_enabled, but they can be auto idled for
 607  *      power savings. They will always be available upon clock request.
 608  *
 609  *      Several sources are given initial rates which may be wrong, this will
 610  *      be fixed up in the init func.
 611  *
 612  *      Things are broadly separated below by clock domains. It is
 613  *      noteworthy that most periferals have dependencies on multiple clock
 614  *      domains. Many get their interface clocks from the L4 domain, but get
 615  *      functional clocks from fixed sources or other core domain derived
 616  *      clocks.
 617  *-------------------------------------------------------------------------*/
 618
 619 /* Base external input clocks */
 620 static struct clk func_32k_ck = {
 621         .name           = "func_32k_ck",
 622         .ops            = &clkops_null,
 623         .rate           = 32000,
 624         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 625                                 RATE_FIXED | RATE_PROPAGATES,
 626         .clkdm_name     = "wkup_clkdm",
 627         .recalc         = &propagate_rate,
 628 };
 629
 630 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 631 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 632         .name           = "osc_ck",
 633         .ops            = &clkops_oscck,
 634         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 635                                 RATE_PROPAGATES,
 636         .clkdm_name     = "wkup_clkdm",
 637         .recalc         = &omap2_osc_clk_recalc,
 638 };
 639
 640 /* Without modem likely 12MHz, with modem likely 13MHz */
 641 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 642         .name           = "sys_ck",             /* ~ ref_clk also */
 643         .ops            = &clkops_null,
 644         .parent         = &osc_ck,
 645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 646                                 RATE_PROPAGATES,
 647         .clkdm_name     = "wkup_clkdm",
 648         .recalc         = &omap2_sys_clk_recalc,
 649 };
 650
 651 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 652         .name           = "alt_ck",
 653         .ops            = &clkops_null,
 654         .rate           = 54000000,
 655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 656                                 RATE_FIXED | RATE_PROPAGATES,
 657         .clkdm_name     = "wkup_clkdm",
 658         .recalc         = &propagate_rate,
 659 };
 660
 661 /*
 662  * Analog domain root source clocks
 663  */
 664
 665 /* dpll_ck, is broken out in to special cases through clksel */
 666 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 667  * deal with this
 668  */
 669
 670 static struct dpll_data dpll_dd = {
 671         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 672         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 673         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 674         .max_multiplier         = 1024,
 675         .max_divider            = 16,
 676         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 677 };
 678
 679 /*
 680  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 681  * not just a DPLL
 682  */
 683 static struct clk dpll_ck = {
 684         .name           = "dpll_ck",
 685         .ops            = &clkops_null,
 686         .parent         = &sys_ck,              /* Can be func_32k also */
 687         .dpll_data      = &dpll_dd,
 688         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 689                                 RATE_PROPAGATES,
 690         .clkdm_name     = "wkup_clkdm",
 691         .recalc         = &omap2_dpllcore_recalc,
 692         .set_rate       = &omap2_reprogram_dpllcore,
 693 };
 694
 695 static struct clk apll96_ck = {
 696         .name           = "apll96_ck",
 697         .ops            = &clkops_fixed,
 698         .parent         = &sys_ck,
 699         .rate           = 96000000,
 700         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 701                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 702         .clkdm_name     = "wkup_clkdm",
 703         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 704         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 705         .recalc         = &propagate_rate,
 706 };
 707
 708 static struct clk apll54_ck = {
 709         .name           = "apll54_ck",
 710         .ops            = &clkops_fixed,
 711         .parent         = &sys_ck,
 712         .rate           = 54000000,
 713         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 714                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 715         .clkdm_name     = "wkup_clkdm",
 716         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 717         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 718         .recalc         = &propagate_rate,
 719 };
 720
 721 /*
 722  * PRCM digital base sources
 723  */
 724
 725 /* func_54m_ck */
 726
 727 static const struct clksel_rate func_54m_apll54_rates[] = {
 728         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 729         { .div = 0 },
 730 };
 731
 732 static const struct clksel_rate func_54m_alt_rates[] = {
 733         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 734         { .div = 0 },
 735 };
 736
 737 static const struct clksel func_54m_clksel[] = {
 738         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 739         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 740         { .parent = NULL },
 741 };
 742
 743 static struct clk func_54m_ck = {
 744         .name           = "func_54m_ck",
 745         .ops            = &clkops_null,
 746         .parent         = &apll54_ck,   /* can also be alt_clk */
 747         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 748                                 RATE_PROPAGATES,
 749         .clkdm_name     = "wkup_clkdm",
 750         .init           = &omap2_init_clksel_parent,
 751         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 752         .clksel_mask    = OMAP24XX_54M_SOURCE,
 753         .clksel         = func_54m_clksel,
 754         .recalc         = &omap2_clksel_recalc,
 755 };
 756
 757 static struct clk core_ck = {
 758         .name           = "core_ck",
 759         .ops            = &clkops_null,
 760         .parent         = &dpll_ck,             /* can also be 32k */
 761         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 762                                 RATE_PROPAGATES,
 763         .clkdm_name     = "wkup_clkdm",
 764         .recalc         = &followparent_recalc,
 765 };
 766
 767 /* func_96m_ck */
 768 static const struct clksel_rate func_96m_apll96_rates[] = {
 769         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 770         { .div = 0 },
 771 };
 772
 773 static const struct clksel_rate func_96m_alt_rates[] = {
 774         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 775         { .div = 0 },
 776 };
 777
 778 static const struct clksel func_96m_clksel[] = {
 779         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 780         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 781         { .parent = NULL }
 782 };
 783
 784 /* The parent of this clock is not selectable on 2420. */
 785 static struct clk func_96m_ck = {
 786         .name           = "func_96m_ck",
 787         .ops            = &clkops_null,
 788         .parent         = &apll96_ck,
 789         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 790                                 RATE_PROPAGATES,
 791         .clkdm_name     = "wkup_clkdm",
 792         .init           = &omap2_init_clksel_parent,
 793         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 794         .clksel_mask    = OMAP2430_96M_SOURCE,
 795         .clksel         = func_96m_clksel,
 796         .recalc         = &omap2_clksel_recalc,
 797         .round_rate     = &omap2_clksel_round_rate,
 798         .set_rate       = &omap2_clksel_set_rate
 799 };
 800
 801 /* func_48m_ck */
 802
 803 static const struct clksel_rate func_48m_apll96_rates[] = {
 804         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 805         { .div = 0 },
 806 };
 807
 808 static const struct clksel_rate func_48m_alt_rates[] = {
 809         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 810         { .div = 0 },
 811 };
 812
 813 static const struct clksel func_48m_clksel[] = {
 814         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 815         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 816         { .parent = NULL }
 817 };
 818
 819 static struct clk func_48m_ck = {
 820         .name           = "func_48m_ck",
 821         .ops            = &clkops_null,
 822         .parent         = &apll96_ck,    /* 96M or Alt */
 823         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 824                                 RATE_PROPAGATES,
 825         .clkdm_name     = "wkup_clkdm",
 826         .init           = &omap2_init_clksel_parent,
 827         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 828         .clksel_mask    = OMAP24XX_48M_SOURCE,
 829         .clksel         = func_48m_clksel,
 830         .recalc         = &omap2_clksel_recalc,
 831         .round_rate     = &omap2_clksel_round_rate,
 832         .set_rate       = &omap2_clksel_set_rate
 833 };
 834
 835 static struct clk func_12m_ck = {
 836         .name           = "func_12m_ck",
 837         .ops            = &clkops_null,
 838         .parent         = &func_48m_ck,
 839         .fixed_div      = 4,
 840         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 841                                 RATE_PROPAGATES,
 842         .clkdm_name     = "wkup_clkdm",
 843         .recalc         = &omap2_fixed_divisor_recalc,
 844 };
 845
 846 /* Secure timer, only available in secure mode */
 847 static struct clk wdt1_osc_ck = {
 848         .name           = "ck_wdt1_osc",
 849         .ops            = &clkops_null, /* RMK: missing? */
 850         .parent         = &osc_ck,
 851         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 852         .recalc         = &followparent_recalc,
 853 };
 854
 855 /*
 856  * The common_clkout* clksel_rate structs are common to
 857  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 858  * sys_clkout2_* are 2420-only, so the
 859  * clksel_rate flags fields are inaccurate for those clocks. This is
 860  * harmless since access to those clocks are gated by the struct clk
 861  * flags fields, which mark them as 2420-only.
 862  */
 863 static const struct clksel_rate common_clkout_src_core_rates[] = {
 864         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 865         { .div = 0 }
 866 };
 867
 868 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 869         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 870         { .div = 0 }
 871 };
 872
 873 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 874         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 875         { .div = 0 }
 876 };
 877
 878 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 879         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 880         { .div = 0 }
 881 };
 882
 883 static const struct clksel common_clkout_src_clksel[] = {
 884         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 885         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 886         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 887         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 888         { .parent = NULL }
 889 };
 890
 891 static struct clk sys_clkout_src = {
 892         .name           = "sys_clkout_src",
 893         .ops            = &clkops_omap2_dflt_wait,
 894         .parent         = &func_54m_ck,
 895         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 896                                 RATE_PROPAGATES,
 897         .clkdm_name     = "wkup_clkdm",
 898         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 899         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 900         .init           = &omap2_init_clksel_parent,
 901         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 902         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 903         .clksel         = common_clkout_src_clksel,
 904         .recalc         = &omap2_clksel_recalc,
 905         .round_rate     = &omap2_clksel_round_rate,
 906         .set_rate       = &omap2_clksel_set_rate
 907 };
 908
 909 static const struct clksel_rate common_clkout_rates[] = {
 910         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 911         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 912         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 913         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 914         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 915         { .div = 0 },
 916 };
 917
 918 static const struct clksel sys_clkout_clksel[] = {
 919         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 920         { .parent = NULL }
 921 };
 922
 923 static struct clk sys_clkout = {
 924         .name           = "sys_clkout",
 925         .ops            = &clkops_null,
 926         .parent         = &sys_clkout_src,
 927         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 928         .clkdm_name     = "wkup_clkdm",
 929         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 930         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 931         .clksel         = sys_clkout_clksel,
 932         .recalc         = &omap2_clksel_recalc,
 933         .round_rate     = &omap2_clksel_round_rate,
 934         .set_rate       = &omap2_clksel_set_rate
 935 };
 936
 937 /* In 2430, new in 2420 ES2 */
 938 static struct clk sys_clkout2_src = {
 939         .name           = "sys_clkout2_src",
 940         .ops            = &clkops_omap2_dflt_wait,
 941         .parent         = &func_54m_ck,
 942         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 943         .clkdm_name     = "wkup_clkdm",
 944         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 945         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 946         .init           = &omap2_init_clksel_parent,
 947         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 948         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 949         .clksel         = common_clkout_src_clksel,
 950         .recalc         = &omap2_clksel_recalc,
 951         .round_rate     = &omap2_clksel_round_rate,
 952         .set_rate       = &omap2_clksel_set_rate
 953 };
 954
 955 static const struct clksel sys_clkout2_clksel[] = {
 956         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 957         { .parent = NULL }
 958 };
 959
 960 /* In 2430, new in 2420 ES2 */
 961 static struct clk sys_clkout2 = {
 962         .name           = "sys_clkout2",
 963         .ops            = &clkops_null,
 964         .parent         = &sys_clkout2_src,
 965         .flags          = CLOCK_IN_OMAP242X,
 966         .clkdm_name     = "wkup_clkdm",
 967         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 968         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 969         .clksel         = sys_clkout2_clksel,
 970         .recalc         = &omap2_clksel_recalc,
 971         .round_rate     = &omap2_clksel_round_rate,
 972         .set_rate       = &omap2_clksel_set_rate
 973 };
 974
 975 static struct clk emul_ck = {
 976         .name           = "emul_ck",
 977         .ops            = &clkops_omap2_dflt_wait,
 978         .parent         = &func_54m_ck,
 979         .flags          = CLOCK_IN_OMAP242X,
 980         .clkdm_name     = "wkup_clkdm",
 981         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 982         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 983         .recalc         = &followparent_recalc,
 984
 985 };
 986
 987 /*
 988  * MPU clock domain
 989  *      Clocks:
 990  *              MPU_FCLK, MPU_ICLK
 991  *              INT_M_FCLK, INT_M_I_CLK
 992  *
 993  * - Individual clocks are hardware managed.
 994  * - Base divider comes from: CM_CLKSEL_MPU
 995  *
 996  */
 997 static const struct clksel_rate mpu_core_rates[] = {
 998         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 999         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1000         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1001         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1002         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1003         { .div = 0 },
1004 };
1005
1006 static const struct clksel mpu_clksel[] = {
1007         { .parent = &core_ck, .rates = mpu_core_rates },
1008         { .parent = NULL }
1009 };
1010
1011 static struct clk mpu_ck = {    /* Control cpu */
1012         .name           = "mpu_ck",
1013         .ops            = &clkops_null,
1014         .parent         = &core_ck,
1015         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1016                                 DELAYED_APP |
1017                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1018         .clkdm_name     = "mpu_clkdm",
1019         .init           = &omap2_init_clksel_parent,
1020         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1021         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1022         .clksel         = mpu_clksel,
1023         .recalc         = &omap2_clksel_recalc,
1024         .round_rate     = &omap2_clksel_round_rate,
1025         .set_rate       = &omap2_clksel_set_rate
1026 };
1027
1028 /*
1029  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1030  * Clocks:
1031  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1032  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1033  *
1034  * Won't be too specific here. The core clock comes into this block
1035  * it is divided then tee'ed. One branch goes directly to xyz enable
1036  * controls. The other branch gets further divided by 2 then possibly
1037  * routed into a synchronizer and out of clocks abc.
1038  */
1039 static const struct clksel_rate dsp_fck_core_rates[] = {
1040         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1041         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1042         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1043         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1044         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1045         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1046         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1047         { .div = 0 },
1048 };
1049
1050 static const struct clksel dsp_fck_clksel[] = {
1051         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1052         { .parent = NULL }
1053 };
1054
1055 static struct clk dsp_fck = {
1056         .name           = "dsp_fck",
1057         .ops            = &clkops_omap2_dflt_wait,
1058         .parent         = &core_ck,
1059         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1060                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1061         .clkdm_name     = "dsp_clkdm",
1062         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1063         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1064         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1065         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1066         .clksel         = dsp_fck_clksel,
1067         .recalc         = &omap2_clksel_recalc,
1068         .round_rate     = &omap2_clksel_round_rate,
1069         .set_rate       = &omap2_clksel_set_rate
1070 };
1071
1072 /* DSP interface clock */
1073 static const struct clksel_rate dsp_irate_ick_rates[] = {
1074         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1075         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1076         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1077         { .div = 0 },
1078 };
1079
1080 static const struct clksel dsp_irate_ick_clksel[] = {
1081         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1082         { .parent = NULL }
1083 };
1084
1085 /* This clock does not exist as such in the TRM. */
1086 static struct clk dsp_irate_ick = {
1087         .name           = "dsp_irate_ick",
1088         .ops            = &clkops_null,
1089         .parent         = &dsp_fck,
1090         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1091                                 CONFIG_PARTICIPANT,
1092         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1093         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1094         .clksel         = dsp_irate_ick_clksel,
1095         .recalc         = &omap2_clksel_recalc,
1096         .round_rate     = &omap2_clksel_round_rate,
1097         .set_rate             = &omap2_clksel_set_rate
1098 };
1099
1100 /* 2420 only */
1101 static struct clk dsp_ick = {
1102         .name           = "dsp_ick",     /* apparently ipi and isp */
1103         .ops            = &clkops_omap2_dflt_wait,
1104         .parent         = &dsp_irate_ick,
1105         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1106         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1107         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1108 };
1109
1110 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1111 static struct clk iva2_1_ick = {
1112         .name           = "iva2_1_ick",
1113         .ops            = &clkops_omap2_dflt_wait,
1114         .parent         = &dsp_irate_ick,
1115         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1116         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1117         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1118 };
1119
1120 /*
1121  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1122  * the C54x, but which is contained in the DSP powerdomain.  Does not
1123  * exist on later OMAPs.
1124  */
1125 static struct clk iva1_ifck = {
1126         .name           = "iva1_ifck",
1127         .ops            = &clkops_omap2_dflt_wait,
1128         .parent         = &core_ck,
1129         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1130                                 RATE_PROPAGATES | DELAYED_APP,
1131         .clkdm_name     = "iva1_clkdm",
1132         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1133         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1134         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1135         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1136         .clksel         = dsp_fck_clksel,
1137         .recalc         = &omap2_clksel_recalc,
1138         .round_rate     = &omap2_clksel_round_rate,
1139         .set_rate       = &omap2_clksel_set_rate
1140 };
1141
1142 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1143 static struct clk iva1_mpu_int_ifck = {
1144         .name           = "iva1_mpu_int_ifck",
1145         .ops            = &clkops_omap2_dflt_wait,
1146         .parent         = &iva1_ifck,
1147         .flags          = CLOCK_IN_OMAP242X,
1148         .clkdm_name     = "iva1_clkdm",
1149         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1150         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1151         .fixed_div      = 2,
1152         .recalc         = &omap2_fixed_divisor_recalc,
1153 };
1154
1155 /*
1156  * L3 clock domain
1157  * L3 clocks are used for both interface and functional clocks to
1158  * multiple entities. Some of these clocks are completely managed
1159  * by hardware, and some others allow software control. Hardware
1160  * managed ones general are based on directly CLK_REQ signals and
1161  * various auto idle settings. The functional spec sets many of these
1162  * as 'tie-high' for their enables.
1163  *
1164  * I-CLOCKS:
1165  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1166  *      CAM, HS-USB.
1167  * F-CLOCK
1168  *      SSI.
1169  *
1170  * GPMC memories and SDRC have timing and clock sensitive registers which
1171  * may very well need notification when the clock changes. Currently for low
1172  * operating points, these are taken care of in sleep.S.
1173  */
1174 static const struct clksel_rate core_l3_core_rates[] = {
1175         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1176         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1177         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1178         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1179         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1180         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1181         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1182         { .div = 0 }
1183 };
1184
1185 static const struct clksel core_l3_clksel[] = {
1186         { .parent = &core_ck, .rates = core_l3_core_rates },
1187         { .parent = NULL }
1188 };
1189
1190 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1191         .name           = "core_l3_ck",
1192         .ops            = &clkops_null,
1193         .parent         = &core_ck,
1194         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1195                                 DELAYED_APP |
1196                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1197         .clkdm_name     = "core_l3_clkdm",
1198         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1199         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1200         .clksel         = core_l3_clksel,
1201         .recalc         = &omap2_clksel_recalc,
1202         .round_rate     = &omap2_clksel_round_rate,
1203         .set_rate       = &omap2_clksel_set_rate
1204 };
1205
1206 /* usb_l4_ick */
1207 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1208         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1209         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1210         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1211         { .div = 0 }
1212 };
1213
1214 static const struct clksel usb_l4_ick_clksel[] = {
1215         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1216         { .parent = NULL },
1217 };
1218
1219 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1220 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1221         .name           = "usb_l4_ick",
1222         .ops            = &clkops_omap2_dflt_wait,
1223         .parent         = &core_l3_ck,
1224         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1225                                 DELAYED_APP | CONFIG_PARTICIPANT,
1226         .clkdm_name     = "core_l4_clkdm",
1227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1228         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1229         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1230         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1231         .clksel         = usb_l4_ick_clksel,
1232         .recalc         = &omap2_clksel_recalc,
1233         .round_rate     = &omap2_clksel_round_rate,
1234         .set_rate       = &omap2_clksel_set_rate
1235 };
1236
1237 /*
1238  * L4 clock management domain
1239  *
1240  * This domain contains lots of interface clocks from the L4 interface, some
1241  * functional clocks.   Fixed APLL functional source clocks are managed in
1242  * this domain.
1243  */
1244 static const struct clksel_rate l4_core_l3_rates[] = {
1245         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1246         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1247         { .div = 0 }
1248 };
1249
1250 static const struct clksel l4_clksel[] = {
1251         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1252         { .parent = NULL }
1253 };
1254
1255 static struct clk l4_ck = {             /* used both as an ick and fck */
1256         .name           = "l4_ck",
1257         .ops            = &clkops_null,
1258         .parent         = &core_l3_ck,
1259         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1260                                 DELAYED_APP | RATE_PROPAGATES,
1261         .clkdm_name     = "core_l4_clkdm",
1262         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1263         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1264         .clksel         = l4_clksel,
1265         .recalc         = &omap2_clksel_recalc,
1266         .round_rate     = &omap2_clksel_round_rate,
1267         .set_rate       = &omap2_clksel_set_rate
1268 };
1269
1270 /*
1271  * SSI is in L3 management domain, its direct parent is core not l3,
1272  * many core power domain entities are grouped into the L3 clock
1273  * domain.
1274  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1275  *
1276  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1277  */
1278 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1279         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1280         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1281         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1282         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1283         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1284         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1285         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1286         { .div = 0 }
1287 };
1288
1289 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1290         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1291         { .parent = NULL }
1292 };
1293
1294 static struct clk ssi_ssr_sst_fck = {
1295         .name           = "ssi_fck",
1296         .ops            = &clkops_omap2_dflt_wait,
1297         .parent         = &core_ck,
1298         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1299                                 DELAYED_APP,
1300         .clkdm_name     = "core_l3_clkdm",
1301         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1302         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1303         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1304         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1305         .clksel         = ssi_ssr_sst_fck_clksel,
1306         .recalc         = &omap2_clksel_recalc,
1307         .round_rate     = &omap2_clksel_round_rate,
1308         .set_rate       = &omap2_clksel_set_rate
1309 };
1310
1311
1312 /*
1313  * GFX clock domain
1314  *      Clocks:
1315  * GFX_FCLK, GFX_ICLK
1316  * GFX_CG1(2d), GFX_CG2(3d)
1317  *
1318  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1319  * The 2d and 3d clocks run at a hardware determined
1320  * divided value of fclk.
1321  *
1322  */
1323 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1324
1325 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1326 static const struct clksel gfx_fck_clksel[] = {
1327         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1328         { .parent = NULL },
1329 };
1330
1331 static struct clk gfx_3d_fck = {
1332         .name           = "gfx_3d_fck",
1333         .ops            = &clkops_omap2_dflt_wait,
1334         .parent         = &core_l3_ck,
1335         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1336         .clkdm_name     = "gfx_clkdm",
1337         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1338         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1339         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1340         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1341         .clksel         = gfx_fck_clksel,
1342         .recalc         = &omap2_clksel_recalc,
1343         .round_rate     = &omap2_clksel_round_rate,
1344         .set_rate       = &omap2_clksel_set_rate
1345 };
1346
1347 static struct clk gfx_2d_fck = {
1348         .name           = "gfx_2d_fck",
1349         .ops            = &clkops_omap2_dflt_wait,
1350         .parent         = &core_l3_ck,
1351         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1352         .clkdm_name     = "gfx_clkdm",
1353         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1354         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1355         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1356         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1357         .clksel         = gfx_fck_clksel,
1358         .recalc         = &omap2_clksel_recalc,
1359         .round_rate     = &omap2_clksel_round_rate,
1360         .set_rate       = &omap2_clksel_set_rate
1361 };
1362
1363 static struct clk gfx_ick = {
1364         .name           = "gfx_ick",            /* From l3 */
1365         .ops            = &clkops_omap2_dflt_wait,
1366         .parent         = &core_l3_ck,
1367         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1368         .clkdm_name     = "gfx_clkdm",
1369         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1370         .enable_bit     = OMAP_EN_GFX_SHIFT,
1371         .recalc         = &followparent_recalc,
1372 };
1373
1374 /*
1375  * Modem clock domain (2430)
1376  *      CLOCKS:
1377  *              MDM_OSC_CLK
1378  *              MDM_ICLK
1379  * These clocks are usable in chassis mode only.
1380  */
1381 static const struct clksel_rate mdm_ick_core_rates[] = {
1382         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1383         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1384         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1385         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1386         { .div = 0 }
1387 };
1388
1389 static const struct clksel mdm_ick_clksel[] = {
1390         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1391         { .parent = NULL }
1392 };
1393
1394 static struct clk mdm_ick = {           /* used both as a ick and fck */
1395         .name           = "mdm_ick",
1396         .ops            = &clkops_omap2_dflt_wait,
1397         .parent         = &core_ck,
1398         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1399         .clkdm_name     = "mdm_clkdm",
1400         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1401         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1402         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1403         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1404         .clksel         = mdm_ick_clksel,
1405         .recalc         = &omap2_clksel_recalc,
1406         .round_rate     = &omap2_clksel_round_rate,
1407         .set_rate       = &omap2_clksel_set_rate
1408 };
1409
1410 static struct clk mdm_osc_ck = {
1411         .name           = "mdm_osc_ck",
1412         .ops            = &clkops_omap2_dflt_wait,
1413         .parent         = &osc_ck,
1414         .flags          = CLOCK_IN_OMAP243X,
1415         .clkdm_name     = "mdm_clkdm",
1416         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1417         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1418         .recalc         = &followparent_recalc,
1419 };
1420
1421 /*
1422  * DSS clock domain
1423  * CLOCKs:
1424  * DSS_L4_ICLK, DSS_L3_ICLK,
1425  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1426  *
1427  * DSS is both initiator and target.
1428  */
1429 /* XXX Add RATE_NOT_VALIDATED */
1430
1431 static const struct clksel_rate dss1_fck_sys_rates[] = {
1432         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1433         { .div = 0 }
1434 };
1435
1436 static const struct clksel_rate dss1_fck_core_rates[] = {
1437         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1438         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1439         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1440         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1441         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1442         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1443         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1444         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1445         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1446         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1447         { .div = 0 }
1448 };
1449
1450 static const struct clksel dss1_fck_clksel[] = {
1451         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1452         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1453         { .parent = NULL },
1454 };
1455
1456 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1457         .name           = "dss_ick",
1458         .ops            = &clkops_omap2_dflt,
1459         .parent         = &l4_ck,       /* really both l3 and l4 */
1460         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1461         .clkdm_name     = "dss_clkdm",
1462         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1463         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk dss1_fck = {
1468         .name           = "dss1_fck",
1469         .ops            = &clkops_omap2_dflt,
1470         .parent         = &core_ck,             /* Core or sys */
1471         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1472                                 DELAYED_APP,
1473         .clkdm_name     = "dss_clkdm",
1474         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1476         .init           = &omap2_init_clksel_parent,
1477         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1478         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1479         .clksel         = dss1_fck_clksel,
1480         .recalc         = &omap2_clksel_recalc,
1481         .round_rate     = &omap2_clksel_round_rate,
1482         .set_rate       = &omap2_clksel_set_rate
1483 };
1484
1485 static const struct clksel_rate dss2_fck_sys_rates[] = {
1486         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1487         { .div = 0 }
1488 };
1489
1490 static const struct clksel_rate dss2_fck_48m_rates[] = {
1491         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1492         { .div = 0 }
1493 };
1494
1495 static const struct clksel dss2_fck_clksel[] = {
1496         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1497         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1498         { .parent = NULL }
1499 };
1500
1501 static struct clk dss2_fck = {          /* Alt clk used in power management */
1502         .name           = "dss2_fck",
1503         .ops            = &clkops_omap2_dflt,
1504         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1505         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1506                                 DELAYED_APP,
1507         .clkdm_name     = "dss_clkdm",
1508         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1509         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1510         .init           = &omap2_init_clksel_parent,
1511         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1512         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1513         .clksel         = dss2_fck_clksel,
1514         .recalc         = &followparent_recalc,
1515 };
1516
1517 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1518         .name           = "dss_54m_fck",        /* 54m tv clk */
1519         .ops            = &clkops_omap2_dflt_wait,
1520         .parent         = &func_54m_ck,
1521         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1522         .clkdm_name     = "dss_clkdm",
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1525         .recalc         = &followparent_recalc,
1526 };
1527
1528 /*
1529  * CORE power domain ICLK & FCLK defines.
1530  * Many of the these can have more than one possible parent. Entries
1531  * here will likely have an L4 interface parent, and may have multiple
1532  * functional clock parents.
1533  */
1534 static const struct clksel_rate gpt_alt_rates[] = {
1535         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1536         { .div = 0 }
1537 };
1538
1539 static const struct clksel omap24xx_gpt_clksel[] = {
1540         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1541         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1542         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1543         { .parent = NULL },
1544 };
1545
1546 static struct clk gpt1_ick = {
1547         .name           = "gpt1_ick",
1548         .ops            = &clkops_omap2_dflt_wait,
1549         .parent         = &l4_ck,
1550         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1551         .clkdm_name     = "core_l4_clkdm",
1552         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1553         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1554         .recalc         = &followparent_recalc,
1555 };
1556
1557 static struct clk gpt1_fck = {
1558         .name           = "gpt1_fck",
1559         .ops            = &clkops_omap2_dflt_wait,
1560         .parent         = &func_32k_ck,
1561         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1562         .clkdm_name     = "core_l4_clkdm",
1563         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1564         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1565         .init           = &omap2_init_clksel_parent,
1566         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1567         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1568         .clksel         = omap24xx_gpt_clksel,
1569         .recalc         = &omap2_clksel_recalc,
1570         .round_rate     = &omap2_clksel_round_rate,
1571         .set_rate       = &omap2_clksel_set_rate
1572 };
1573
1574 static struct clk gpt2_ick = {
1575         .name           = "gpt2_ick",
1576         .ops            = &clkops_omap2_dflt_wait,
1577         .parent         = &l4_ck,
1578         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1579         .clkdm_name     = "core_l4_clkdm",
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1581         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk gpt2_fck = {
1586         .name           = "gpt2_fck",
1587         .ops            = &clkops_omap2_dflt_wait,
1588         .parent         = &func_32k_ck,
1589         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1590         .clkdm_name     = "core_l4_clkdm",
1591         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1593         .init           = &omap2_init_clksel_parent,
1594         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1595         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1596         .clksel         = omap24xx_gpt_clksel,
1597         .recalc         = &omap2_clksel_recalc,
1598 };
1599
1600 static struct clk gpt3_ick = {
1601         .name           = "gpt3_ick",
1602         .ops            = &clkops_omap2_dflt_wait,
1603         .parent         = &l4_ck,
1604         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1605         .clkdm_name     = "core_l4_clkdm",
1606         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1607         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1608         .recalc         = &followparent_recalc,
1609 };
1610
1611 static struct clk gpt3_fck = {
1612         .name           = "gpt3_fck",
1613         .ops            = &clkops_omap2_dflt_wait,
1614         .parent         = &func_32k_ck,
1615         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1616         .clkdm_name     = "core_l4_clkdm",
1617         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1618         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1619         .init           = &omap2_init_clksel_parent,
1620         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1621         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1622         .clksel         = omap24xx_gpt_clksel,
1623         .recalc         = &omap2_clksel_recalc,
1624 };
1625
1626 static struct clk gpt4_ick = {
1627         .name           = "gpt4_ick",
1628         .ops            = &clkops_omap2_dflt_wait,
1629         .parent         = &l4_ck,
1630         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631         .clkdm_name     = "core_l4_clkdm",
1632         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1633         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 static struct clk gpt4_fck = {
1638         .name           = "gpt4_fck",
1639         .ops            = &clkops_omap2_dflt_wait,
1640         .parent         = &func_32k_ck,
1641         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1642         .clkdm_name     = "core_l4_clkdm",
1643         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1645         .init           = &omap2_init_clksel_parent,
1646         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1647         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1648         .clksel         = omap24xx_gpt_clksel,
1649         .recalc         = &omap2_clksel_recalc,
1650 };
1651
1652 static struct clk gpt5_ick = {
1653         .name           = "gpt5_ick",
1654         .ops            = &clkops_omap2_dflt_wait,
1655         .parent         = &l4_ck,
1656         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1657         .clkdm_name     = "core_l4_clkdm",
1658         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1659         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1660         .recalc         = &followparent_recalc,
1661 };
1662
1663 static struct clk gpt5_fck = {
1664         .name           = "gpt5_fck",
1665         .ops            = &clkops_omap2_dflt_wait,
1666         .parent         = &func_32k_ck,
1667         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1668         .clkdm_name     = "core_l4_clkdm",
1669         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1670         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1671         .init           = &omap2_init_clksel_parent,
1672         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1673         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1674         .clksel         = omap24xx_gpt_clksel,
1675         .recalc         = &omap2_clksel_recalc,
1676 };
1677
1678 static struct clk gpt6_ick = {
1679         .name           = "gpt6_ick",
1680         .ops            = &clkops_omap2_dflt_wait,
1681         .parent         = &l4_ck,
1682         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1683         .clkdm_name     = "core_l4_clkdm",
1684         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1685         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1686         .recalc         = &followparent_recalc,
1687 };
1688
1689 static struct clk gpt6_fck = {
1690         .name           = "gpt6_fck",
1691         .ops            = &clkops_omap2_dflt_wait,
1692         .parent         = &func_32k_ck,
1693         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1694         .clkdm_name     = "core_l4_clkdm",
1695         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1696         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1697         .init           = &omap2_init_clksel_parent,
1698         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1699         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1700         .clksel         = omap24xx_gpt_clksel,
1701         .recalc         = &omap2_clksel_recalc,
1702 };
1703
1704 static struct clk gpt7_ick = {
1705         .name           = "gpt7_ick",
1706         .ops            = &clkops_omap2_dflt_wait,
1707         .parent         = &l4_ck,
1708         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1709         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1710         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1711         .recalc         = &followparent_recalc,
1712 };
1713
1714 static struct clk gpt7_fck = {
1715         .name           = "gpt7_fck",
1716         .ops            = &clkops_omap2_dflt_wait,
1717         .parent         = &func_32k_ck,
1718         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1719         .clkdm_name     = "core_l4_clkdm",
1720         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1721         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1722         .init           = &omap2_init_clksel_parent,
1723         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1724         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1725         .clksel         = omap24xx_gpt_clksel,
1726         .recalc         = &omap2_clksel_recalc,
1727 };
1728
1729 static struct clk gpt8_ick = {
1730         .name           = "gpt8_ick",
1731         .ops            = &clkops_omap2_dflt_wait,
1732         .parent         = &l4_ck,
1733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734         .clkdm_name     = "core_l4_clkdm",
1735         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1736         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1737         .recalc         = &followparent_recalc,
1738 };
1739
1740 static struct clk gpt8_fck = {
1741         .name           = "gpt8_fck",
1742         .ops            = &clkops_omap2_dflt_wait,
1743         .parent         = &func_32k_ck,
1744         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1745         .clkdm_name     = "core_l4_clkdm",
1746         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1747         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1748         .init           = &omap2_init_clksel_parent,
1749         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1750         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1751         .clksel         = omap24xx_gpt_clksel,
1752         .recalc         = &omap2_clksel_recalc,
1753 };
1754
1755 static struct clk gpt9_ick = {
1756         .name           = "gpt9_ick",
1757         .ops            = &clkops_omap2_dflt_wait,
1758         .parent         = &l4_ck,
1759         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1760         .clkdm_name     = "core_l4_clkdm",
1761         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1762         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1763         .recalc         = &followparent_recalc,
1764 };
1765
1766 static struct clk gpt9_fck = {
1767         .name           = "gpt9_fck",
1768         .ops            = &clkops_omap2_dflt_wait,
1769         .parent         = &func_32k_ck,
1770         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1771         .clkdm_name     = "core_l4_clkdm",
1772         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1773         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1774         .init           = &omap2_init_clksel_parent,
1775         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1776         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1777         .clksel         = omap24xx_gpt_clksel,
1778         .recalc         = &omap2_clksel_recalc,
1779 };
1780
1781 static struct clk gpt10_ick = {
1782         .name           = "gpt10_ick",
1783         .ops            = &clkops_omap2_dflt_wait,
1784         .parent         = &l4_ck,
1785         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1786         .clkdm_name     = "core_l4_clkdm",
1787         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1789         .recalc         = &followparent_recalc,
1790 };
1791
1792 static struct clk gpt10_fck = {
1793         .name           = "gpt10_fck",
1794         .ops            = &clkops_omap2_dflt_wait,
1795         .parent         = &func_32k_ck,
1796         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1797         .clkdm_name     = "core_l4_clkdm",
1798         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1799         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1800         .init           = &omap2_init_clksel_parent,
1801         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1802         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1803         .clksel         = omap24xx_gpt_clksel,
1804         .recalc         = &omap2_clksel_recalc,
1805 };
1806
1807 static struct clk gpt11_ick = {
1808         .name           = "gpt11_ick",
1809         .ops            = &clkops_omap2_dflt_wait,
1810         .parent         = &l4_ck,
1811         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1812         .clkdm_name     = "core_l4_clkdm",
1813         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1814         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1815         .recalc         = &followparent_recalc,
1816 };
1817
1818 static struct clk gpt11_fck = {
1819         .name           = "gpt11_fck",
1820         .ops            = &clkops_omap2_dflt_wait,
1821         .parent         = &func_32k_ck,
1822         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1823         .clkdm_name     = "core_l4_clkdm",
1824         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1825         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1826         .init           = &omap2_init_clksel_parent,
1827         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1828         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1829         .clksel         = omap24xx_gpt_clksel,
1830         .recalc         = &omap2_clksel_recalc,
1831 };
1832
1833 static struct clk gpt12_ick = {
1834         .name           = "gpt12_ick",
1835         .ops            = &clkops_omap2_dflt_wait,
1836         .parent         = &l4_ck,
1837         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1838         .clkdm_name     = "core_l4_clkdm",
1839         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1840         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 static struct clk gpt12_fck = {
1845         .name           = "gpt12_fck",
1846         .ops            = &clkops_omap2_dflt_wait,
1847         .parent         = &func_32k_ck,
1848         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1849         .clkdm_name     = "core_l4_clkdm",
1850         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1851         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1852         .init           = &omap2_init_clksel_parent,
1853         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1854         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1855         .clksel         = omap24xx_gpt_clksel,
1856         .recalc         = &omap2_clksel_recalc,
1857 };
1858
1859 static struct clk mcbsp1_ick = {
1860         .name           = "mcbsp_ick",
1861         .ops            = &clkops_omap2_dflt_wait,
1862         .id             = 1,
1863         .parent         = &l4_ck,
1864         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1865         .clkdm_name     = "core_l4_clkdm",
1866         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1868         .recalc         = &followparent_recalc,
1869 };
1870
1871 static struct clk mcbsp1_fck = {
1872         .name           = "mcbsp_fck",
1873         .ops            = &clkops_omap2_dflt_wait,
1874         .id             = 1,
1875         .parent         = &func_96m_ck,
1876         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1877         .clkdm_name     = "core_l4_clkdm",
1878         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1879         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1880         .recalc         = &followparent_recalc,
1881 };
1882
1883 static struct clk mcbsp2_ick = {
1884         .name           = "mcbsp_ick",
1885         .ops            = &clkops_omap2_dflt_wait,
1886         .id             = 2,
1887         .parent         = &l4_ck,
1888         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1889         .clkdm_name     = "core_l4_clkdm",
1890         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1891         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk mcbsp2_fck = {
1896         .name           = "mcbsp_fck",
1897         .ops            = &clkops_omap2_dflt_wait,
1898         .id             = 2,
1899         .parent         = &func_96m_ck,
1900         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1901         .clkdm_name     = "core_l4_clkdm",
1902         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1903         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mcbsp3_ick = {
1908         .name           = "mcbsp_ick",
1909         .ops            = &clkops_omap2_dflt_wait,
1910         .id             = 3,
1911         .parent         = &l4_ck,
1912         .flags          = CLOCK_IN_OMAP243X,
1913         .clkdm_name     = "core_l4_clkdm",
1914         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1915         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1916         .recalc         = &followparent_recalc,
1917 };
1918
1919 static struct clk mcbsp3_fck = {
1920         .name           = "mcbsp_fck",
1921         .ops            = &clkops_omap2_dflt_wait,
1922         .id             = 3,
1923         .parent         = &func_96m_ck,
1924         .flags          = CLOCK_IN_OMAP243X,
1925         .clkdm_name     = "core_l4_clkdm",
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1927         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1928         .recalc         = &followparent_recalc,
1929 };
1930
1931 static struct clk mcbsp4_ick = {
1932         .name           = "mcbsp_ick",
1933         .ops            = &clkops_omap2_dflt_wait,
1934         .id             = 4,
1935         .parent         = &l4_ck,
1936         .flags          = CLOCK_IN_OMAP243X,
1937         .clkdm_name     = "core_l4_clkdm",
1938         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1939         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk mcbsp4_fck = {
1944         .name           = "mcbsp_fck",
1945         .ops            = &clkops_omap2_dflt_wait,
1946         .id             = 4,
1947         .parent         = &func_96m_ck,
1948         .flags          = CLOCK_IN_OMAP243X,
1949         .clkdm_name     = "core_l4_clkdm",
1950         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1951         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk mcbsp5_ick = {
1956         .name           = "mcbsp_ick",
1957         .ops            = &clkops_omap2_dflt_wait,
1958         .id             = 5,
1959         .parent         = &l4_ck,
1960         .flags          = CLOCK_IN_OMAP243X,
1961         .clkdm_name     = "core_l4_clkdm",
1962         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1963         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1964         .recalc         = &followparent_recalc,
1965 };
1966
1967 static struct clk mcbsp5_fck = {
1968         .name           = "mcbsp_fck",
1969         .ops            = &clkops_omap2_dflt_wait,
1970         .id             = 5,
1971         .parent         = &func_96m_ck,
1972         .flags          = CLOCK_IN_OMAP243X,
1973         .clkdm_name     = "core_l4_clkdm",
1974         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1975         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk mcspi1_ick = {
1980         .name           = "mcspi_ick",
1981         .ops            = &clkops_omap2_dflt_wait,
1982         .id             = 1,
1983         .parent         = &l4_ck,
1984         .clkdm_name     = "core_l4_clkdm",
1985         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1986         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1988         .recalc         = &followparent_recalc,
1989 };
1990
1991 static struct clk mcspi1_fck = {
1992         .name           = "mcspi_fck",
1993         .ops            = &clkops_omap2_dflt_wait,
1994         .id             = 1,
1995         .parent         = &func_48m_ck,
1996         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1997         .clkdm_name     = "core_l4_clkdm",
1998         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1999         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2000         .recalc         = &followparent_recalc,
2001 };
2002
2003 static struct clk mcspi2_ick = {
2004         .name           = "mcspi_ick",
2005         .ops            = &clkops_omap2_dflt_wait,
2006         .id             = 2,
2007         .parent         = &l4_ck,
2008         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2009         .clkdm_name     = "core_l4_clkdm",
2010         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2011         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2012         .recalc         = &followparent_recalc,
2013 };
2014
2015 static struct clk mcspi2_fck = {
2016         .name           = "mcspi_fck",
2017         .ops            = &clkops_omap2_dflt_wait,
2018         .id             = 2,
2019         .parent         = &func_48m_ck,
2020         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2021         .clkdm_name     = "core_l4_clkdm",
2022         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2023         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2024         .recalc         = &followparent_recalc,
2025 };
2026
2027 static struct clk mcspi3_ick = {
2028         .name           = "mcspi_ick",
2029         .ops            = &clkops_omap2_dflt_wait,
2030         .id             = 3,
2031         .parent         = &l4_ck,
2032         .flags          = CLOCK_IN_OMAP243X,
2033         .clkdm_name     = "core_l4_clkdm",
2034         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2035         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk mcspi3_fck = {
2040         .name           = "mcspi_fck",
2041         .ops            = &clkops_omap2_dflt_wait,
2042         .id             = 3,
2043         .parent         = &func_48m_ck,
2044         .flags          = CLOCK_IN_OMAP243X,
2045         .clkdm_name     = "core_l4_clkdm",
2046         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2047         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2048         .recalc         = &followparent_recalc,
2049 };
2050
2051 static struct clk uart1_ick = {
2052         .name           = "uart1_ick",
2053         .ops            = &clkops_omap2_dflt_wait,
2054         .parent         = &l4_ck,
2055         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2056         .clkdm_name     = "core_l4_clkdm",
2057         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2058         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2059         .recalc         = &followparent_recalc,
2060 };
2061
2062 static struct clk uart1_fck = {
2063         .name           = "uart1_fck",
2064         .ops            = &clkops_omap2_dflt_wait,
2065         .parent         = &func_48m_ck,
2066         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2067         .clkdm_name     = "core_l4_clkdm",
2068         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2069         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2070         .recalc         = &followparent_recalc,
2071 };
2072
2073 static struct clk uart2_ick = {
2074         .name           = "uart2_ick",
2075         .ops            = &clkops_omap2_dflt_wait,
2076         .parent         = &l4_ck,
2077         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2078         .clkdm_name     = "core_l4_clkdm",
2079         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2080         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2081         .recalc         = &followparent_recalc,
2082 };
2083
2084 static struct clk uart2_fck = {
2085         .name           = "uart2_fck",
2086         .ops            = &clkops_omap2_dflt_wait,
2087         .parent         = &func_48m_ck,
2088         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2089         .clkdm_name     = "core_l4_clkdm",
2090         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2091         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2092         .recalc         = &followparent_recalc,
2093 };
2094
2095 static struct clk uart3_ick = {
2096         .name           = "uart3_ick",
2097         .ops            = &clkops_omap2_dflt_wait,
2098         .parent         = &l4_ck,
2099         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2100         .clkdm_name     = "core_l4_clkdm",
2101         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2102         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk uart3_fck = {
2107         .name           = "uart3_fck",
2108         .ops            = &clkops_omap2_dflt_wait,
2109         .parent         = &func_48m_ck,
2110         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2111         .clkdm_name     = "core_l4_clkdm",
2112         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2113         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk gpios_ick = {
2118         .name           = "gpios_ick",
2119         .ops            = &clkops_omap2_dflt_wait,
2120         .parent         = &l4_ck,
2121         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2122         .clkdm_name     = "core_l4_clkdm",
2123         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2124         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 static struct clk gpios_fck = {
2129         .name           = "gpios_fck",
2130         .ops            = &clkops_omap2_dflt_wait,
2131         .parent         = &func_32k_ck,
2132         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2133         .clkdm_name     = "wkup_clkdm",
2134         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2135         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2136         .recalc         = &followparent_recalc,
2137 };
2138
2139 static struct clk mpu_wdt_ick = {
2140         .name           = "mpu_wdt_ick",
2141         .ops            = &clkops_omap2_dflt_wait,
2142         .parent         = &l4_ck,
2143         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2144         .clkdm_name     = "core_l4_clkdm",
2145         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2146         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2147         .recalc         = &followparent_recalc,
2148 };
2149
2150 static struct clk mpu_wdt_fck = {
2151         .name           = "mpu_wdt_fck",
2152         .ops            = &clkops_omap2_dflt_wait,
2153         .parent         = &func_32k_ck,
2154         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155         .clkdm_name     = "wkup_clkdm",
2156         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2157         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2158         .recalc         = &followparent_recalc,
2159 };
2160
2161 static struct clk sync_32k_ick = {
2162         .name           = "sync_32k_ick",
2163         .ops            = &clkops_omap2_dflt_wait,
2164         .parent         = &l4_ck,
2165         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2166                                 ENABLE_ON_INIT,
2167         .clkdm_name     = "core_l4_clkdm",
2168         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2169         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk wdt1_ick = {
2174         .name           = "wdt1_ick",
2175         .ops            = &clkops_omap2_dflt_wait,
2176         .parent         = &l4_ck,
2177         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2178         .clkdm_name     = "core_l4_clkdm",
2179         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2180         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 static struct clk omapctrl_ick = {
2185         .name           = "omapctrl_ick",
2186         .ops            = &clkops_omap2_dflt_wait,
2187         .parent         = &l4_ck,
2188         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2189                                 ENABLE_ON_INIT,
2190         .clkdm_name     = "core_l4_clkdm",
2191         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2192         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk icr_ick = {
2197         .name           = "icr_ick",
2198         .ops            = &clkops_omap2_dflt_wait,
2199         .parent         = &l4_ck,
2200         .flags          = CLOCK_IN_OMAP243X,
2201         .clkdm_name     = "core_l4_clkdm",
2202         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2203         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2204         .recalc         = &followparent_recalc,
2205 };
2206
2207 static struct clk cam_ick = {
2208         .name           = "cam_ick",
2209         .ops            = &clkops_omap2_dflt,
2210         .parent         = &l4_ck,
2211         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2212         .clkdm_name     = "core_l4_clkdm",
2213         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2214         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 /*
2219  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2220  * split into two separate clocks, since the parent clocks are different
2221  * and the clockdomains are also different.
2222  */
2223 static struct clk cam_fck = {
2224         .name           = "cam_fck",
2225         .ops            = &clkops_omap2_dflt,
2226         .parent         = &func_96m_ck,
2227         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2228         .clkdm_name     = "core_l3_clkdm",
2229         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2230         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2231         .recalc         = &followparent_recalc,
2232 };
2233
2234 static struct clk mailboxes_ick = {
2235         .name           = "mailboxes_ick",
2236         .ops            = &clkops_omap2_dflt_wait,
2237         .parent         = &l4_ck,
2238         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2239         .clkdm_name     = "core_l4_clkdm",
2240         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2241         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk wdt4_ick = {
2246         .name           = "wdt4_ick",
2247         .ops            = &clkops_omap2_dflt_wait,
2248         .parent         = &l4_ck,
2249         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2250         .clkdm_name     = "core_l4_clkdm",
2251         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2252         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2253         .recalc         = &followparent_recalc,
2254 };
2255
2256 static struct clk wdt4_fck = {
2257         .name           = "wdt4_fck",
2258         .ops            = &clkops_omap2_dflt_wait,
2259         .parent         = &func_32k_ck,
2260         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2261         .clkdm_name     = "core_l4_clkdm",
2262         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2263         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2264         .recalc         = &followparent_recalc,
2265 };
2266
2267 static struct clk wdt3_ick = {
2268         .name           = "wdt3_ick",
2269         .ops            = &clkops_omap2_dflt_wait,
2270         .parent         = &l4_ck,
2271         .flags          = CLOCK_IN_OMAP242X,
2272         .clkdm_name     = "core_l4_clkdm",
2273         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2274         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2275         .recalc         = &followparent_recalc,
2276 };
2277
2278 static struct clk wdt3_fck = {
2279         .name           = "wdt3_fck",
2280         .ops            = &clkops_omap2_dflt_wait,
2281         .parent         = &func_32k_ck,
2282         .flags          = CLOCK_IN_OMAP242X,
2283         .clkdm_name     = "core_l4_clkdm",
2284         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2285         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2286         .recalc         = &followparent_recalc,
2287 };
2288
2289 static struct clk mspro_ick = {
2290         .name           = "mspro_ick",
2291         .ops            = &clkops_omap2_dflt_wait,
2292         .parent         = &l4_ck,
2293         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2294         .clkdm_name     = "core_l4_clkdm",
2295         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2296         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2297         .recalc         = &followparent_recalc,
2298 };
2299
2300 static struct clk mspro_fck = {
2301         .name           = "mspro_fck",
2302         .ops            = &clkops_omap2_dflt_wait,
2303         .parent         = &func_96m_ck,
2304         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2305         .clkdm_name     = "core_l4_clkdm",
2306         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2307         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2308         .recalc         = &followparent_recalc,
2309 };
2310
2311 static struct clk mmc_ick = {
2312         .name           = "mmc_ick",
2313         .ops            = &clkops_omap2_dflt_wait,
2314         .parent         = &l4_ck,
2315         .flags          = CLOCK_IN_OMAP242X,
2316         .clkdm_name     = "core_l4_clkdm",
2317         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2318         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2319         .recalc         = &followparent_recalc,
2320 };
2321
2322 static struct clk mmc_fck = {
2323         .name           = "mmc_fck",
2324         .ops            = &clkops_omap2_dflt_wait,
2325         .parent         = &func_96m_ck,
2326         .flags          = CLOCK_IN_OMAP242X,
2327         .clkdm_name     = "core_l4_clkdm",
2328         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2329         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2330         .recalc         = &followparent_recalc,
2331 };
2332
2333 static struct clk fac_ick = {
2334         .name           = "fac_ick",
2335         .ops            = &clkops_omap2_dflt_wait,
2336         .parent         = &l4_ck,
2337         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2338         .clkdm_name     = "core_l4_clkdm",
2339         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2340         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2341         .recalc         = &followparent_recalc,
2342 };
2343
2344 static struct clk fac_fck = {
2345         .name           = "fac_fck",
2346         .ops            = &clkops_omap2_dflt_wait,
2347         .parent         = &func_12m_ck,
2348         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2349         .clkdm_name     = "core_l4_clkdm",
2350         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2351         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk eac_ick = {
2356         .name           = "eac_ick",
2357         .ops            = &clkops_omap2_dflt_wait,
2358         .parent         = &l4_ck,
2359         .flags          = CLOCK_IN_OMAP242X,
2360         .clkdm_name     = "core_l4_clkdm",
2361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2362         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2363         .recalc         = &followparent_recalc,
2364 };
2365
2366 static struct clk eac_fck = {
2367         .name           = "eac_fck",
2368         .ops            = &clkops_omap2_dflt_wait,
2369         .parent         = &func_96m_ck,
2370         .flags          = CLOCK_IN_OMAP242X,
2371         .clkdm_name     = "core_l4_clkdm",
2372         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2373         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2374         .recalc         = &followparent_recalc,
2375 };
2376
2377 static struct clk hdq_ick = {
2378         .name           = "hdq_ick",
2379         .ops            = &clkops_omap2_dflt_wait,
2380         .parent         = &l4_ck,
2381         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2382         .clkdm_name     = "core_l4_clkdm",
2383         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2384         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk hdq_fck = {
2389         .name           = "hdq_fck",
2390         .ops            = &clkops_omap2_dflt_wait,
2391         .parent         = &func_12m_ck,
2392         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2393         .clkdm_name     = "core_l4_clkdm",
2394         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2395         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2396         .recalc         = &followparent_recalc,
2397 };
2398
2399 static struct clk i2c2_ick = {
2400         .name           = "i2c_ick",
2401         .ops            = &clkops_omap2_dflt_wait,
2402         .id             = 2,
2403         .parent         = &l4_ck,
2404         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2405         .clkdm_name     = "core_l4_clkdm",
2406         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2407         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2408         .recalc         = &followparent_recalc,
2409 };
2410
2411 static struct clk i2c2_fck = {
2412         .name           = "i2c_fck",
2413         .ops            = &clkops_omap2_dflt_wait,
2414         .id             = 2,
2415         .parent         = &func_12m_ck,
2416         .flags          = CLOCK_IN_OMAP242X,
2417         .clkdm_name     = "core_l4_clkdm",
2418         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2419         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2420         .recalc         = &followparent_recalc,
2421 };
2422
2423 static struct clk i2chs2_fck = {
2424         .name           = "i2c_fck",
2425         .ops            = &clkops_omap2_dflt_wait,
2426         .id             = 2,
2427         .parent         = &func_96m_ck,
2428         .flags          = CLOCK_IN_OMAP243X,
2429         .clkdm_name     = "core_l4_clkdm",
2430         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2431         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2432         .recalc         = &followparent_recalc,
2433 };
2434
2435 static struct clk i2c1_ick = {
2436         .name           = "i2c_ick",
2437         .ops            = &clkops_omap2_dflt_wait,
2438         .id             = 1,
2439         .parent         = &l4_ck,
2440         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2441         .clkdm_name     = "core_l4_clkdm",
2442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2443         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2444         .recalc         = &followparent_recalc,
2445 };
2446
2447 static struct clk i2c1_fck = {
2448         .name           = "i2c_fck",
2449         .ops            = &clkops_omap2_dflt_wait,
2450         .id             = 1,
2451         .parent         = &func_12m_ck,
2452         .flags          = CLOCK_IN_OMAP242X,
2453         .clkdm_name     = "core_l4_clkdm",
2454         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2455         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2456         .recalc         = &followparent_recalc,
2457 };
2458
2459 static struct clk i2chs1_fck = {
2460         .name           = "i2c_fck",
2461         .ops            = &clkops_omap2_dflt_wait,
2462         .id             = 1,
2463         .parent         = &func_96m_ck,
2464         .flags          = CLOCK_IN_OMAP243X,
2465         .clkdm_name     = "core_l4_clkdm",
2466         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2467         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2468         .recalc         = &followparent_recalc,
2469 };
2470
2471 static struct clk gpmc_fck = {
2472         .name           = "gpmc_fck",
2473         .ops            = &clkops_null, /* RMK: missing? */
2474         .parent         = &core_l3_ck,
2475         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2476                                 ENABLE_ON_INIT,
2477         .clkdm_name     = "core_l3_clkdm",
2478         .recalc         = &followparent_recalc,
2479 };
2480
2481 static struct clk sdma_fck = {
2482         .name           = "sdma_fck",
2483         .ops            = &clkops_null, /* RMK: missing? */
2484         .parent         = &core_l3_ck,
2485         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2486         .clkdm_name     = "core_l3_clkdm",
2487         .recalc         = &followparent_recalc,
2488 };
2489
2490 static struct clk sdma_ick = {
2491         .name           = "sdma_ick",
2492         .ops            = &clkops_null, /* RMK: missing? */
2493         .parent         = &l4_ck,
2494         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2495         .clkdm_name     = "core_l3_clkdm",
2496         .recalc         = &followparent_recalc,
2497 };
2498
2499 static struct clk vlynq_ick = {
2500         .name           = "vlynq_ick",
2501         .ops            = &clkops_omap2_dflt_wait,
2502         .parent         = &core_l3_ck,
2503         .flags          = CLOCK_IN_OMAP242X,
2504         .clkdm_name     = "core_l3_clkdm",
2505         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2506         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2507         .recalc         = &followparent_recalc,
2508 };
2509
2510 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2511         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2512         { .div = 0 }
2513 };
2514
2515 static const struct clksel_rate vlynq_fck_core_rates[] = {
2516         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2517         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2518         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2519         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2520         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2521         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2522         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2523         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2524         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2525         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2526         { .div = 0 }
2527 };
2528
2529 static const struct clksel vlynq_fck_clksel[] = {
2530         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2531         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2532         { .parent = NULL }
2533 };
2534
2535 static struct clk vlynq_fck = {
2536         .name           = "vlynq_fck",
2537         .ops            = &clkops_omap2_dflt_wait,
2538         .parent         = &func_96m_ck,
2539         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2540         .clkdm_name     = "core_l3_clkdm",
2541         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2542         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2543         .init           = &omap2_init_clksel_parent,
2544         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2545         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2546         .clksel         = vlynq_fck_clksel,
2547         .recalc         = &omap2_clksel_recalc,
2548         .round_rate     = &omap2_clksel_round_rate,
2549         .set_rate       = &omap2_clksel_set_rate
2550 };
2551
2552 static struct clk sdrc_ick = {
2553         .name           = "sdrc_ick",
2554         .ops            = &clkops_omap2_dflt_wait,
2555         .parent         = &l4_ck,
2556         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2557         .clkdm_name     = "core_l4_clkdm",
2558         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2559         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2560         .recalc         = &followparent_recalc,
2561 };
2562
2563 static struct clk des_ick = {
2564         .name           = "des_ick",
2565         .ops            = &clkops_omap2_dflt_wait,
2566         .parent         = &l4_ck,
2567         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2568         .clkdm_name     = "core_l4_clkdm",
2569         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2570         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2571         .recalc         = &followparent_recalc,
2572 };
2573
2574 static struct clk sha_ick = {
2575         .name           = "sha_ick",
2576         .ops            = &clkops_omap2_dflt_wait,
2577         .parent         = &l4_ck,
2578         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2579         .clkdm_name     = "core_l4_clkdm",
2580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2581         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2582         .recalc         = &followparent_recalc,
2583 };
2584
2585 static struct clk rng_ick = {
2586         .name           = "rng_ick",
2587         .ops            = &clkops_omap2_dflt_wait,
2588         .parent         = &l4_ck,
2589         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2590         .clkdm_name     = "core_l4_clkdm",
2591         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2592         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2593         .recalc         = &followparent_recalc,
2594 };
2595
2596 static struct clk aes_ick = {
2597         .name           = "aes_ick",
2598         .ops            = &clkops_omap2_dflt_wait,
2599         .parent         = &l4_ck,
2600         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2601         .clkdm_name     = "core_l4_clkdm",
2602         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2603         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2604         .recalc         = &followparent_recalc,
2605 };
2606
2607 static struct clk pka_ick = {
2608         .name           = "pka_ick",
2609         .ops            = &clkops_omap2_dflt_wait,
2610         .parent         = &l4_ck,
2611         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2612         .clkdm_name     = "core_l4_clkdm",
2613         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2614         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk usb_fck = {
2619         .name           = "usb_fck",
2620         .ops            = &clkops_omap2_dflt_wait,
2621         .parent         = &func_48m_ck,
2622         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2623         .clkdm_name     = "core_l3_clkdm",
2624         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2625         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2626         .recalc         = &followparent_recalc,
2627 };
2628
2629 static struct clk usbhs_ick = {
2630         .name           = "usbhs_ick",
2631         .ops            = &clkops_omap2_dflt_wait,
2632         .parent         = &core_l3_ck,
2633         .flags          = CLOCK_IN_OMAP243X,
2634         .clkdm_name     = "core_l3_clkdm",
2635         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2636         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2637         .recalc         = &followparent_recalc,
2638 };
2639
2640 static struct clk mmchs1_ick = {
2641         .name           = "mmchs_ick",
2642         .ops            = &clkops_omap2_dflt_wait,
2643         .parent         = &l4_ck,
2644         .flags          = CLOCK_IN_OMAP243X,
2645         .clkdm_name     = "core_l4_clkdm",
2646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2647         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2648         .recalc         = &followparent_recalc,
2649 };
2650
2651 static struct clk mmchs1_fck = {
2652         .name           = "mmchs_fck",
2653         .ops            = &clkops_omap2_dflt_wait,
2654         .parent         = &func_96m_ck,
2655         .flags          = CLOCK_IN_OMAP243X,
2656         .clkdm_name     = "core_l3_clkdm",
2657         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2658         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2659         .recalc         = &followparent_recalc,
2660 };
2661
2662 static struct clk mmchs2_ick = {
2663         .name           = "mmchs_ick",
2664         .ops            = &clkops_omap2_dflt_wait,
2665         .id             = 1,
2666         .parent         = &l4_ck,
2667         .flags          = CLOCK_IN_OMAP243X,
2668         .clkdm_name     = "core_l4_clkdm",
2669         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2670         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2671         .recalc         = &followparent_recalc,
2672 };
2673
2674 static struct clk mmchs2_fck = {
2675         .name           = "mmchs_fck",
2676         .ops            = &clkops_omap2_dflt_wait,
2677         .id             = 1,
2678         .parent         = &func_96m_ck,
2679         .flags          = CLOCK_IN_OMAP243X,
2680         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2681         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2682         .recalc         = &followparent_recalc,
2683 };
2684
2685 static struct clk gpio5_ick = {
2686         .name           = "gpio5_ick",
2687         .ops            = &clkops_omap2_dflt_wait,
2688         .parent         = &l4_ck,
2689         .flags          = CLOCK_IN_OMAP243X,
2690         .clkdm_name     = "core_l4_clkdm",
2691         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2692         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2693         .recalc         = &followparent_recalc,
2694 };
2695
2696 static struct clk gpio5_fck = {
2697         .name           = "gpio5_fck",
2698         .ops            = &clkops_omap2_dflt_wait,
2699         .parent         = &func_32k_ck,
2700         .flags          = CLOCK_IN_OMAP243X,
2701         .clkdm_name     = "core_l4_clkdm",
2702         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2703         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2704         .recalc         = &followparent_recalc,
2705 };
2706
2707 static struct clk mdm_intc_ick = {
2708         .name           = "mdm_intc_ick",
2709         .ops            = &clkops_omap2_dflt_wait,
2710         .parent         = &l4_ck,
2711         .flags          = CLOCK_IN_OMAP243X,
2712         .clkdm_name     = "core_l4_clkdm",
2713         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2714         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2715         .recalc         = &followparent_recalc,
2716 };
2717
2718 static struct clk mmchsdb1_fck = {
2719         .name           = "mmchsdb_fck",
2720         .ops            = &clkops_omap2_dflt_wait,
2721         .parent         = &func_32k_ck,
2722         .flags          = CLOCK_IN_OMAP243X,
2723         .clkdm_name     = "core_l4_clkdm",
2724         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2725         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2726         .recalc         = &followparent_recalc,
2727 };
2728
2729 static struct clk mmchsdb2_fck = {
2730         .name           = "mmchsdb_fck",
2731         .ops            = &clkops_omap2_dflt_wait,
2732         .id             = 1,
2733         .parent         = &func_32k_ck,
2734         .flags          = CLOCK_IN_OMAP243X,
2735         .clkdm_name     = "core_l4_clkdm",
2736         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2737         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2738         .recalc         = &followparent_recalc,
2739 };
2740
2741 /*
2742  * This clock is a composite clock which does entire set changes then
2743  * forces a rebalance. It keys on the MPU speed, but it really could
2744  * be any key speed part of a set in the rate table.
2745  *
2746  * to really change a set, you need memory table sets which get changed
2747  * in sram, pre-notifiers & post notifiers, changing the top set, without
2748  * having low level display recalc's won't work... this is why dpm notifiers
2749  * work, isr's off, walk a list of clocks already _off_ and not messing with
2750  * the bus.
2751  *
2752  * This clock should have no parent. It embodies the entire upper level
2753  * active set. A parent will mess up some of the init also.
2754  */
2755 static struct clk virt_prcm_set = {
2756         .name           = "virt_prcm_set",
2757         .ops            = &clkops_null,
2758         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2759                                 DELAYED_APP,
2760         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2761         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2762         .set_rate       = &omap2_select_table_rate,
2763         .round_rate     = &omap2_round_to_table_rate,
2764 };
2765
2766 static struct clk *onchip_24xx_clks[] __initdata = {
2767         /* external root sources */
2768         &func_32k_ck,
2769         &osc_ck,
2770         &sys_ck,
2771         &alt_ck,
2772         /* internal analog sources */
2773         &dpll_ck,
2774         &apll96_ck,
2775         &apll54_ck,
2776         /* internal prcm root sources */
2777         &func_54m_ck,
2778         &core_ck,
2779         &func_96m_ck,
2780         &func_48m_ck,
2781         &func_12m_ck,
2782         &wdt1_osc_ck,
2783         &sys_clkout_src,
2784         &sys_clkout,
2785         &sys_clkout2_src,
2786         &sys_clkout2,
2787         &emul_ck,
2788         /* mpu domain clocks */
2789         &mpu_ck,
2790         /* dsp domain clocks */
2791         &dsp_fck,
2792         &dsp_irate_ick,
2793         &dsp_ick,               /* 242x */
2794         &iva2_1_ick,            /* 243x */
2795         &iva1_ifck,             /* 242x */
2796         &iva1_mpu_int_ifck,     /* 242x */
2797         /* GFX domain clocks */
2798         &gfx_3d_fck,
2799         &gfx_2d_fck,
2800         &gfx_ick,
2801         /* Modem domain clocks */
2802         &mdm_ick,
2803         &mdm_osc_ck,
2804         /* DSS domain clocks */
2805         &dss_ick,
2806         &dss1_fck,
2807         &dss2_fck,
2808         &dss_54m_fck,
2809         /* L3 domain clocks */
2810         &core_l3_ck,
2811         &ssi_ssr_sst_fck,
2812         &usb_l4_ick,
2813         /* L4 domain clocks */
2814         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2815         /* virtual meta-group clock */
2816         &virt_prcm_set,
2817         /* general l4 interface ck, multi-parent functional clk */
2818         &gpt1_ick,
2819         &gpt1_fck,
2820         &gpt2_ick,
2821         &gpt2_fck,
2822         &gpt3_ick,
2823         &gpt3_fck,
2824         &gpt4_ick,
2825         &gpt4_fck,
2826         &gpt5_ick,
2827         &gpt5_fck,
2828         &gpt6_ick,
2829         &gpt6_fck,
2830         &gpt7_ick,
2831         &gpt7_fck,
2832         &gpt8_ick,
2833         &gpt8_fck,
2834         &gpt9_ick,
2835         &gpt9_fck,
2836         &gpt10_ick,
2837         &gpt10_fck,
2838         &gpt11_ick,
2839         &gpt11_fck,
2840         &gpt12_ick,
2841         &gpt12_fck,
2842         &mcbsp1_ick,
2843         &mcbsp1_fck,
2844         &mcbsp2_ick,
2845         &mcbsp2_fck,
2846         &mcbsp3_ick,
2847         &mcbsp3_fck,
2848         &mcbsp4_ick,
2849         &mcbsp4_fck,
2850         &mcbsp5_ick,
2851         &mcbsp5_fck,
2852         &mcspi1_ick,
2853         &mcspi1_fck,
2854         &mcspi2_ick,
2855         &mcspi2_fck,
2856         &mcspi3_ick,
2857         &mcspi3_fck,
2858         &uart1_ick,
2859         &uart1_fck,
2860         &uart2_ick,
2861         &uart2_fck,
2862         &uart3_ick,
2863         &uart3_fck,
2864         &gpios_ick,
2865         &gpios_fck,
2866         &mpu_wdt_ick,
2867         &mpu_wdt_fck,
2868         &sync_32k_ick,
2869         &wdt1_ick,
2870         &omapctrl_ick,
2871         &icr_ick,
2872         &cam_fck,
2873         &cam_ick,
2874         &mailboxes_ick,
2875         &wdt4_ick,
2876         &wdt4_fck,
2877         &wdt3_ick,
2878         &wdt3_fck,
2879         &mspro_ick,
2880         &mspro_fck,
2881         &mmc_ick,
2882         &mmc_fck,
2883         &fac_ick,
2884         &fac_fck,
2885         &eac_ick,
2886         &eac_fck,
2887         &hdq_ick,
2888         &hdq_fck,
2889         &i2c1_ick,
2890         &i2c1_fck,
2891         &i2chs1_fck,
2892         &i2c2_ick,
2893         &i2c2_fck,
2894         &i2chs2_fck,
2895         &gpmc_fck,
2896         &sdma_fck,
2897         &sdma_ick,
2898         &vlynq_ick,
2899         &vlynq_fck,
2900         &sdrc_ick,
2901         &des_ick,
2902         &sha_ick,
2903         &rng_ick,
2904         &aes_ick,
2905         &pka_ick,
2906         &usb_fck,
2907         &usbhs_ick,
2908         &mmchs1_ick,
2909         &mmchs1_fck,
2910         &mmchs2_ick,
2911         &mmchs2_fck,
2912         &gpio5_ick,
2913         &gpio5_fck,
2914         &mdm_intc_ick,
2915         &mmchsdb1_fck,
2916         &mmchsdb2_fck,
2917 };
2918
2919 #endif
2920