arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*-------------------------------------------------------------------------
 604  * 24xx clock tree.
 605  *
 606  * NOTE:In many cases here we are assigning a 'default' parent. In many
 607  *      cases the parent is selectable. The get/set parent calls will also
 608  *      switch sources.
 609  *
 610  *      Many some clocks say always_enabled, but they can be auto idled for
 611  *      power savings. They will always be available upon clock request.
 612  *
 613  *      Several sources are given initial rates which may be wrong, this will
 614  *      be fixed up in the init func.
 615  *
 616  *      Things are broadly separated below by clock domains. It is
 617  *      noteworthy that most periferals have dependencies on multiple clock
 618  *      domains. Many get their interface clocks from the L4 domain, but get
 619  *      functional clocks from fixed sources or other core domain derived
 620  *      clocks.
 621  *-------------------------------------------------------------------------*/
 622
 623 /* Base external input clocks */
 624 static struct clk func_32k_ck = {
 625         .name           = "func_32k_ck",
 626         .rate           = 32000,
 627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 628                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 629         .clkdm          = { .name = "prm_clkdm" },
 630         .recalc         = &propagate_rate,
 631 };
 632
 633 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 634 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 635         .name           = "osc_ck",
 636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 637                                 RATE_PROPAGATES,
 638         .clkdm          = { .name = "prm_clkdm" },
 639         .enable         = &omap2_enable_osc_ck,
 640         .disable        = &omap2_disable_osc_ck,
 641         .recalc         = &omap2_osc_clk_recalc,
 642 };
 643
 644 /* Without modem likely 12MHz, with modem likely 13MHz */
 645 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 646         .name           = "sys_ck",             /* ~ ref_clk also */
 647         .parent         = &osc_ck,
 648         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 649                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 650         .clkdm          = { .name = "prm_clkdm" },
 651         .recalc         = &omap2_sys_clk_recalc,
 652 };
 653
 654 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 655         .name           = "alt_ck",
 656         .rate           = 54000000,
 657         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 658                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 659         .clkdm          = { .name = "prm_clkdm" },
 660         .recalc         = &propagate_rate,
 661 };
 662
 663 /*
 664  * Analog domain root source clocks
 665  */
 666
 667 /* dpll_ck, is broken out in to special cases through clksel */
 668 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 669  * deal with this
 670  */
 671
 672 static struct dpll_data dpll_dd = {
 673         .mult_div1_reg          = CM_CLKSEL1,
 674         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 675         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 676         .control_reg            = CM_CLKEN,
 677         .enable_mask            = OMAP24XX_EN_DPLL_MASK,
 678         .max_multiplier         = 1024,
 679         .min_divider            = 1,
 680         .max_divider            = 16,
 681         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 682 };
 683
 684 /*
 685  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 686  * not just a DPLL
 687  */
 688 static struct clk dpll_ck = {
 689         .name           = "dpll_ck",
 690         .parent         = &sys_ck,              /* Can be func_32k also */
 691         .prcm_mod       = PLL_MOD,
 692         .dpll_data      = &dpll_dd,
 693         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 694                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 695         .clkdm          = { .name = "prm_clkdm" },
 696         .recalc         = &omap2_dpllcore_recalc,
 697         .set_rate       = &omap2_reprogram_dpllcore,
 698 };
 699
 700 static struct clk apll96_ck = {
 701         .name           = "apll96_ck",
 702         .parent         = &sys_ck,
 703         .prcm_mod       = PLL_MOD,
 704         .rate           = 96000000,
 705         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 706                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 707         .clkdm          = { .name = "prm_clkdm" },
 708         .enable_reg     = CM_CLKEN,
 709         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 710         .enable         = &omap2_clk_fixed_enable,
 711         .disable        = &omap2_clk_fixed_disable,
 712         .recalc         = &propagate_rate,
 713 };
 714
 715 static struct clk apll54_ck = {
 716         .name           = "apll54_ck",
 717         .parent         = &sys_ck,
 718         .prcm_mod       = PLL_MOD,
 719         .rate           = 54000000,
 720         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 721                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 722         .clkdm          = { .name = "prm_clkdm" },
 723         .enable_reg     = CM_CLKEN,
 724         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 725         .enable         = &omap2_clk_fixed_enable,
 726         .disable        = &omap2_clk_fixed_disable,
 727         .recalc         = &propagate_rate,
 728 };
 729
 730 /*
 731  * PRCM digital base sources
 732  */
 733
 734 /* func_54m_ck */
 735
 736 static const struct clksel_rate func_54m_apll54_rates[] = {
 737         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 738         { .div = 0 },
 739 };
 740
 741 static const struct clksel_rate func_54m_alt_rates[] = {
 742         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 743         { .div = 0 },
 744 };
 745
 746 static const struct clksel func_54m_clksel[] = {
 747         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 748         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 749         { .parent = NULL },
 750 };
 751
 752 static struct clk func_54m_ck = {
 753         .name           = "func_54m_ck",
 754         .parent         = &apll54_ck,   /* can also be alt_clk */
 755         .prcm_mod       = PLL_MOD,
 756         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 757                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 758         .clkdm          = { .name = "cm_clkdm" },
 759         .init           = &omap2_init_clksel_parent,
 760         .clksel_reg     = CM_CLKSEL1,
 761         .clksel_mask    = OMAP24XX_54M_SOURCE,
 762         .clksel         = func_54m_clksel,
 763         .recalc         = &omap2_clksel_recalc,
 764 };
 765
 766 static struct clk core_ck = {
 767         .name           = "core_ck",
 768         .parent         = &dpll_ck,             /* can also be 32k */
 769         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 770                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 771         .clkdm          = { .name = "cm_clkdm" },
 772         .recalc         = &followparent_recalc,
 773 };
 774
 775 /* func_96m_ck */
 776 static const struct clksel_rate func_96m_apll96_rates[] = {
 777         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 778         { .div = 0 },
 779 };
 780
 781 static const struct clksel_rate func_96m_alt_rates[] = {
 782         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 783         { .div = 0 },
 784 };
 785
 786 static const struct clksel func_96m_clksel[] = {
 787         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 788         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 789         { .parent = NULL }
 790 };
 791
 792 /* The parent of this clock is not selectable on 2420. */
 793 static struct clk func_96m_ck = {
 794         .name           = "func_96m_ck",
 795         .parent         = &apll96_ck,
 796         .prcm_mod       = PLL_MOD,
 797         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 798                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 799         .clkdm          = { .name = "cm_clkdm" },
 800         .init           = &omap2_init_clksel_parent,
 801         .clksel_reg     = CM_CLKSEL1,
 802         .clksel_mask    = OMAP2430_96M_SOURCE,
 803         .clksel         = func_96m_clksel,
 804         .recalc         = &omap2_clksel_recalc,
 805         .round_rate     = &omap2_clksel_round_rate,
 806         .set_rate       = &omap2_clksel_set_rate
 807 };
 808
 809 /* func_48m_ck */
 810
 811 static const struct clksel_rate func_48m_apll96_rates[] = {
 812         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 813         { .div = 0 },
 814 };
 815
 816 static const struct clksel_rate func_48m_alt_rates[] = {
 817         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 818         { .div = 0 },
 819 };
 820
 821 static const struct clksel func_48m_clksel[] = {
 822         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 823         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 824         { .parent = NULL }
 825 };
 826
 827 static struct clk func_48m_ck = {
 828         .name           = "func_48m_ck",
 829         .parent         = &apll96_ck,    /* 96M or Alt */
 830         .prcm_mod       = PLL_MOD,
 831         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 832                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 833         .clkdm          = { .name = "cm_clkdm" },
 834         .init           = &omap2_init_clksel_parent,
 835         .clksel_reg     = CM_CLKSEL1,
 836         .clksel_mask    = OMAP24XX_48M_SOURCE,
 837         .clksel         = func_48m_clksel,
 838         .recalc         = &omap2_clksel_recalc,
 839         .round_rate     = &omap2_clksel_round_rate,
 840         .set_rate       = &omap2_clksel_set_rate
 841 };
 842
 843 static struct clk func_12m_ck = {
 844         .name           = "func_12m_ck",
 845         .parent         = &func_48m_ck,
 846         .fixed_div      = 4,
 847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 848                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 849         .clkdm          = { .name = "cm_clkdm" },
 850         .recalc         = &omap2_fixed_divisor_recalc,
 851 };
 852
 853 /* Secure timer, only available in secure mode */
 854 static struct clk wdt1_osc_ck = {
 855         .name           = "wdt1_osc_ck",
 856         .parent         = &osc_ck,
 857         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 858         .clkdm          = { .name = "prm_clkdm" },
 859         .recalc         = &followparent_recalc,
 860 };
 861
 862 /*
 863  * The common_clkout* clksel_rate structs are common to
 864  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 865  * sys_clkout2_* are 2420-only, so the
 866  * clksel_rate flags fields are inaccurate for those clocks. This is
 867  * harmless since access to those clocks are gated by the struct clk
 868  * flags fields, which mark them as 2420-only.
 869  */
 870 static const struct clksel_rate common_clkout_src_core_rates[] = {
 871         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 872         { .div = 0 }
 873 };
 874
 875 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 876         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 877         { .div = 0 }
 878 };
 879
 880 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 881         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 882         { .div = 0 }
 883 };
 884
 885 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 886         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 887         { .div = 0 }
 888 };
 889
 890 static const struct clksel common_clkout_src_clksel[] = {
 891         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 892         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 893         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 894         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 895         { .parent = NULL }
 896 };
 897
 898 static struct clk sys_clkout_src = {
 899         .name           = "sys_clkout_src",
 900         .parent         = &func_54m_ck,
 901         .prcm_mod       = OMAP24XX_GR_MOD,
 902         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 903                                 RATE_PROPAGATES,
 904         .clkdm          = { .name = "prm_clkdm" },
 905         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 906         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 907         .init           = &omap2_init_clksel_parent,
 908         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 909         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 910         .clksel         = common_clkout_src_clksel,
 911         .recalc         = &omap2_clksel_recalc,
 912         .round_rate     = &omap2_clksel_round_rate,
 913         .set_rate       = &omap2_clksel_set_rate
 914 };
 915
 916 static const struct clksel_rate common_clkout_rates[] = {
 917         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 918         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 919         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 920         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 921         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 922         { .div = 0 },
 923 };
 924
 925 static const struct clksel sys_clkout_clksel[] = {
 926         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 927         { .parent = NULL }
 928 };
 929
 930 static struct clk sys_clkout = {
 931         .name           = "sys_clkout",
 932         .parent         = &sys_clkout_src,
 933         .prcm_mod       = OMAP24XX_GR_MOD,
 934         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 935                                 PARENT_CONTROLS_CLOCK,
 936         .clkdm          = { .name = "prm_clkdm" },
 937         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 938         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 939         .clksel         = sys_clkout_clksel,
 940         .recalc         = &omap2_clksel_recalc,
 941         .round_rate     = &omap2_clksel_round_rate,
 942         .set_rate       = &omap2_clksel_set_rate
 943 };
 944
 945 /* In 2430, new in 2420 ES2 */
 946 static struct clk sys_clkout2_src = {
 947         .name           = "sys_clkout2_src",
 948         .parent         = &func_54m_ck,
 949         .prcm_mod       = OMAP24XX_GR_MOD,
 950         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 951         .clkdm          = { .name = "cm_clkdm" },
 952         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 953         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 954         .init           = &omap2_init_clksel_parent,
 955         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 956         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 957         .clksel         = common_clkout_src_clksel,
 958         .recalc         = &omap2_clksel_recalc,
 959         .round_rate     = &omap2_clksel_round_rate,
 960         .set_rate       = &omap2_clksel_set_rate
 961 };
 962
 963 static const struct clksel sys_clkout2_clksel[] = {
 964         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 965         { .parent = NULL }
 966 };
 967
 968 /* In 2430, new in 2420 ES2 */
 969 static struct clk sys_clkout2 = {
 970         .name           = "sys_clkout2",
 971         .parent         = &sys_clkout2_src,
 972         .prcm_mod       = OMAP24XX_GR_MOD,
 973         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 974         .clkdm          = { .name = "cm_clkdm" },
 975         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 976         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 977         .clksel         = sys_clkout2_clksel,
 978         .recalc         = &omap2_clksel_recalc,
 979         .round_rate     = &omap2_clksel_round_rate,
 980         .set_rate       = &omap2_clksel_set_rate
 981 };
 982
 983 static struct clk emul_ck = {
 984         .name           = "emul_ck",
 985         .parent         = &func_54m_ck,
 986         .prcm_mod       = OMAP24XX_GR_MOD,
 987         .flags          = CLOCK_IN_OMAP242X,
 988         .clkdm          = { .name = "cm_clkdm" },
 989         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET,
 990         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 991         .recalc         = &followparent_recalc,
 992
 993 };
 994
 995 /*
 996  * MPU clock domain
 997  *      Clocks:
 998  *              MPU_FCLK, MPU_ICLK
 999  *              INT_M_FCLK, INT_M_I_CLK
1000  *
1001  * - Individual clocks are hardware managed.
1002  * - Base divider comes from: CM_CLKSEL_MPU
1003  *
1004  */
1005 static const struct clksel_rate mpu_core_rates[] = {
1006         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1007         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1008         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1009         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1010         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1011         { .div = 0 },
1012 };
1013
1014 static const struct clksel mpu_clksel[] = {
1015         { .parent = &core_ck, .rates = mpu_core_rates },
1016         { .parent = NULL }
1017 };
1018
1019 static struct clk mpu_ck = {    /* Control cpu */
1020         .name           = "mpu_ck",
1021         .parent         = &core_ck,
1022         .prcm_mod       = MPU_MOD,
1023         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1024                                 ALWAYS_ENABLED | DELAYED_APP |
1025                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1026         .clkdm          = { .name = "mpu_clkdm" },
1027         .init           = &omap2_init_clksel_parent,
1028         .clksel_reg     = CM_CLKSEL,
1029         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1030         .clksel         = mpu_clksel,
1031         .recalc         = &omap2_clksel_recalc,
1032         .round_rate     = &omap2_clksel_round_rate,
1033         .set_rate       = &omap2_clksel_set_rate
1034 };
1035
1036 /*
1037  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1038  * Clocks:
1039  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1040  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1041  *
1042  * Won't be too specific here. The core clock comes into this block
1043  * it is divided then tee'ed. One branch goes directly to xyz enable
1044  * controls. The other branch gets further divided by 2 then possibly
1045  * routed into a synchronizer and out of clocks abc.
1046  */
1047 static const struct clksel_rate dsp_fck_core_rates[] = {
1048         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1049         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1050         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1051         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1052         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1053         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1054         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1055         { .div = 0 },
1056 };
1057
1058 static const struct clksel dsp_fck_clksel[] = {
1059         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1060         { .parent = NULL }
1061 };
1062
1063 static struct clk dsp_fck = {
1064         .name           = "dsp_fck",
1065         .parent         = &core_ck,
1066         .prcm_mod       = OMAP24XX_DSP_MOD,
1067         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1068                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1069         .clkdm          = { .name = "dsp_clkdm" },
1070         .enable_reg     = CM_FCLKEN,
1071         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1072         .clksel_reg     = CM_CLKSEL,
1073         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1074         .clksel         = dsp_fck_clksel,
1075         .recalc         = &omap2_clksel_recalc,
1076         .round_rate     = &omap2_clksel_round_rate,
1077         .set_rate       = &omap2_clksel_set_rate
1078 };
1079
1080 /* DSP interface clock */
1081 static const struct clksel_rate dsp_irate_ick_rates[] = {
1082         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1083         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1084         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1085         { .div = 0 },
1086 };
1087
1088 static const struct clksel dsp_irate_ick_clksel[] = {
1089         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1090         { .parent = NULL }
1091 };
1092
1093 /* This clock does not exist as such in the TRM. */
1094 static struct clk dsp_irate_ick = {
1095         .name           = "dsp_irate_ick",
1096         .parent         = &dsp_fck,
1097         .prcm_mod       = OMAP24XX_DSP_MOD,
1098         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1099                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1100         .clkdm          = { .name = "dsp_clkdm" },
1101         .clksel_reg     = CM_CLKSEL,
1102         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1103         .clksel         = dsp_irate_ick_clksel,
1104         .recalc         = &omap2_clksel_recalc,
1105         .round_rate     = &omap2_clksel_round_rate,
1106         .set_rate       = &omap2_clksel_set_rate
1107 };
1108
1109 /* 2420 only */
1110 static struct clk dsp_ick = {
1111         .name           = "dsp_ick",     /* apparently ipi and isp */
1112         .parent         = &dsp_irate_ick,
1113         .prcm_mod       = OMAP24XX_DSP_MOD,
1114         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1115         .clkdm          = { .name = "dsp_clkdm" },
1116         .enable_reg     = CM_ICLKEN,
1117         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1118 };
1119
1120 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1121 static struct clk iva2_1_ick = {
1122         .name           = "iva2_1_ick",
1123         .parent         = &dsp_irate_ick,
1124         .prcm_mod       = OMAP24XX_DSP_MOD,
1125         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1126         .clkdm          = { .name = "dsp_clkdm" },
1127         .enable_reg     = CM_FCLKEN,
1128         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1129 };
1130
1131 /*
1132  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1133  * the C54x, but which is contained in the DSP powerdomain.  Does not
1134  * exist on later OMAPs.
1135  */
1136 static struct clk iva1_ifck = {
1137         .name           = "iva1_ifck",
1138         .parent         = &core_ck,
1139         .prcm_mod       = OMAP24XX_DSP_MOD,
1140         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1141                                 RATE_PROPAGATES | DELAYED_APP,
1142         .clkdm          = { .name = "iva1_clkdm" },
1143         .enable_reg     = CM_FCLKEN,
1144         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1145         .clksel_reg     = CM_CLKSEL,
1146         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1147         .clksel         = dsp_fck_clksel,
1148         .recalc         = &omap2_clksel_recalc,
1149         .round_rate     = &omap2_clksel_round_rate,
1150         .set_rate       = &omap2_clksel_set_rate
1151 };
1152
1153 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1154 static struct clk iva1_mpu_int_ifck = {
1155         .name           = "iva1_mpu_int_ifck",
1156         .parent         = &iva1_ifck,
1157         .prcm_mod       = OMAP24XX_DSP_MOD,
1158         .flags          = CLOCK_IN_OMAP242X,
1159         .clkdm          = { .name = "iva1_clkdm" },
1160         .enable_reg     = CM_FCLKEN,
1161         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1162         .fixed_div      = 2,
1163         .recalc         = &omap2_fixed_divisor_recalc,
1164 };
1165
1166 /*
1167  * L3 clock domain
1168  * L3 clocks are used for both interface and functional clocks to
1169  * multiple entities. Some of these clocks are completely managed
1170  * by hardware, and some others allow software control. Hardware
1171  * managed ones general are based on directly CLK_REQ signals and
1172  * various auto idle settings. The functional spec sets many of these
1173  * as 'tie-high' for their enables.
1174  *
1175  * I-CLOCKS:
1176  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1177  *      CAM, HS-USB.
1178  * F-CLOCK
1179  *      SSI.
1180  *
1181  * GPMC memories and SDRC have timing and clock sensitive registers which
1182  * may very well need notification when the clock changes. Currently for low
1183  * operating points, these are taken care of in sleep.S.
1184  */
1185 static const struct clksel_rate core_l3_core_rates[] = {
1186         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1187         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1188         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1189         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1190         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1191         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1192         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1193         { .div = 0 }
1194 };
1195
1196 static const struct clksel core_l3_clksel[] = {
1197         { .parent = &core_ck, .rates = core_l3_core_rates },
1198         { .parent = NULL }
1199 };
1200
1201 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1202         .name           = "core_l3_ck",
1203         .parent         = &core_ck,
1204         .prcm_mod       = CORE_MOD,
1205         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1206                                 ALWAYS_ENABLED | DELAYED_APP |
1207                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1208         .clkdm          = { .name = "core_l3_clkdm" },
1209         .clksel_reg     = CM_CLKSEL1,
1210         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1211         .clksel         = core_l3_clksel,
1212         .recalc         = &omap2_clksel_recalc,
1213         .round_rate     = &omap2_clksel_round_rate,
1214         .set_rate       = &omap2_clksel_set_rate
1215 };
1216
1217 /* usb_l4_ick */
1218 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1219         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1220         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1221         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1222         { .div = 0 }
1223 };
1224
1225 static const struct clksel usb_l4_ick_clksel[] = {
1226         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1227         { .parent = NULL },
1228 };
1229
1230 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1231 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1232         .name           = "usb_l4_ick",
1233         .parent         = &core_l3_ck,
1234         .prcm_mod       = CORE_MOD,
1235         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1236                                 DELAYED_APP | CONFIG_PARTICIPANT | WAIT_READY,
1237         .clkdm          = { .name = "core_l4_clkdm" },
1238         .enable_reg     = CM_ICLKEN2,
1239         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1240         .idlest_bit     = OMAP24XX_ST_USB_SHIFT,
1241         .clksel_reg     = CM_CLKSEL1,
1242         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1243         .clksel         = usb_l4_ick_clksel,
1244         .recalc         = &omap2_clksel_recalc,
1245         .round_rate     = &omap2_clksel_round_rate,
1246         .set_rate       = &omap2_clksel_set_rate
1247 };
1248
1249 /*
1250  * L4 clock management domain
1251  *
1252  * This domain contains lots of interface clocks from the L4 interface, some
1253  * functional clocks.   Fixed APLL functional source clocks are managed in
1254  * this domain.
1255  */
1256 static const struct clksel_rate l4_core_l3_rates[] = {
1257         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1258         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1259         { .div = 0 }
1260 };
1261
1262 static const struct clksel l4_clksel[] = {
1263         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1264         { .parent = NULL }
1265 };
1266
1267 static struct clk l4_ck = {             /* used both as an ick and fck */
1268         .name           = "l4_ck",
1269         .parent         = &core_l3_ck,
1270         .prcm_mod       = CORE_MOD,
1271         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1272                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1273         .clkdm          = { .name = "core_l4_clkdm" },
1274         .clksel_reg     = CM_CLKSEL1,
1275         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1276         .clksel         = l4_clksel,
1277         .recalc         = &omap2_clksel_recalc,
1278         .round_rate     = &omap2_clksel_round_rate,
1279         .set_rate       = &omap2_clksel_set_rate
1280 };
1281
1282 /*
1283  * SSI is in L3 management domain, its direct parent is core not l3,
1284  * many core power domain entities are grouped into the L3 clock
1285  * domain.
1286  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1287  *
1288  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1289  */
1290 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1291         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1292         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1293         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1294         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1295         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1296         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1297         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1298         { .div = 0 }
1299 };
1300
1301 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1302         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1303         { .parent = NULL }
1304 };
1305
1306 static struct clk ssi_ssr_sst_fck = {
1307         .name           = "ssi_fck",
1308         .parent         = &core_ck,
1309         .prcm_mod       = CORE_MOD,
1310         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY |
1311                                 DELAYED_APP,
1312         .clkdm          = { .name = "core_l3_clkdm" },
1313         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1314         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1315         .idlest_bit     = OMAP24XX_ST_SSI_SHIFT,
1316         .clksel_reg     = CM_CLKSEL1,
1317         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1318         .clksel         = ssi_ssr_sst_fck_clksel,
1319         .recalc         = &omap2_clksel_recalc,
1320         .round_rate     = &omap2_clksel_round_rate,
1321         .set_rate       = &omap2_clksel_set_rate
1322 };
1323
1324 /*
1325  * Presumably this is the same as SSI_ICLK.
1326  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1327  */
1328 static struct clk ssi_l4_ick = {
1329         .name           = "ssi_l4_ick",
1330         .parent         = &l4_ck,
1331         .prcm_mod       = CORE_MOD,
1332         .clkdm          = { .name = "core_l4_clkdm" },
1333         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1334         .enable_reg     = CM_ICLKEN2,
1335         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1336         .idlest_bit     = OMAP24XX_ST_SSI_SHIFT,
1337         .recalc         = &followparent_recalc,
1338 };
1339
1340
1341 /*
1342  * GFX clock domain
1343  *      Clocks:
1344  * GFX_FCLK, GFX_ICLK
1345  * GFX_CG1(2d), GFX_CG2(3d)
1346  *
1347  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1348  * The 2d and 3d clocks run at a hardware determined
1349  * divided value of fclk.
1350  *
1351  */
1352 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1353
1354 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1355 static const struct clksel gfx_fck_clksel[] = {
1356         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1357         { .parent = NULL },
1358 };
1359
1360 static struct clk gfx_3d_fck = {
1361         .name           = "gfx_3d_fck",
1362         .parent         = &core_l3_ck,
1363         .prcm_mod       = GFX_MOD,
1364         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1365         .clkdm          = { .name = "gfx_clkdm" },
1366         .enable_reg     = CM_FCLKEN,
1367         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1368         .clksel_reg     = CM_CLKSEL,
1369         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1370         .clksel         = gfx_fck_clksel,
1371         .recalc         = &omap2_clksel_recalc,
1372         .round_rate     = &omap2_clksel_round_rate,
1373         .set_rate       = &omap2_clksel_set_rate
1374 };
1375
1376 static struct clk gfx_2d_fck = {
1377         .name           = "gfx_2d_fck",
1378         .parent         = &core_l3_ck,
1379         .prcm_mod       = GFX_MOD,
1380         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1381         .clkdm          = { .name = "gfx_clkdm" },
1382         .enable_reg     = CM_FCLKEN,
1383         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1384         .clksel_reg     = CM_CLKSEL,
1385         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1386         .clksel         = gfx_fck_clksel,
1387         .recalc         = &omap2_clksel_recalc,
1388         .round_rate     = &omap2_clksel_round_rate,
1389         .set_rate       = &omap2_clksel_set_rate
1390 };
1391
1392 static struct clk gfx_ick = {
1393         .name           = "gfx_ick",            /* From l3 */
1394         .parent         = &core_l3_ck,
1395         .prcm_mod       = GFX_MOD,
1396         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1397         .clkdm          = { .name = "gfx_clkdm" },
1398         .enable_reg     = CM_ICLKEN,
1399         .enable_bit     = OMAP_EN_GFX_SHIFT,
1400         .recalc         = &followparent_recalc,
1401 };
1402
1403 /*
1404  * Modem clock domain (2430)
1405  *      CLOCKS:
1406  *              MDM_OSC_CLK
1407  *              MDM_ICLK
1408  * These clocks are usable in chassis mode only.
1409  */
1410 static const struct clksel_rate mdm_ick_core_rates[] = {
1411         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1412         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1413         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1414         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1415         { .div = 0 }
1416 };
1417
1418 static const struct clksel mdm_ick_clksel[] = {
1419         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1420         { .parent = NULL }
1421 };
1422
1423 static struct clk mdm_ick = {           /* used both as a ick and fck */
1424         .name           = "mdm_ick",
1425         .parent         = &core_ck,
1426         .prcm_mod       = OMAP2430_MDM_MOD,
1427         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1428         .clkdm          = { .name = "mdm_clkdm" },
1429         .enable_reg     = CM_ICLKEN,
1430         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1431         .clksel_reg     = CM_CLKSEL,
1432         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1433         .clksel         = mdm_ick_clksel,
1434         .recalc         = &omap2_clksel_recalc,
1435         .round_rate     = &omap2_clksel_round_rate,
1436         .set_rate       = &omap2_clksel_set_rate
1437 };
1438
1439 static struct clk mdm_osc_ck = {
1440         .name           = "mdm_osc_ck",
1441         .parent         = &osc_ck,
1442         .prcm_mod       = OMAP2430_MDM_MOD,
1443         .flags          = CLOCK_IN_OMAP243X,
1444         .clkdm          = { .name = "mdm_clkdm" },
1445         .enable_reg     = CM_FCLKEN,
1446         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1447         .recalc         = &followparent_recalc,
1448 };
1449
1450 /*
1451  * DSS clock domain
1452  * CLOCKs:
1453  * DSS_L4_ICLK, DSS_L3_ICLK,
1454  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1455  *
1456  * DSS is both initiator and target.
1457  */
1458 /* XXX Add RATE_NOT_VALIDATED */
1459
1460 static const struct clksel_rate dss1_fck_sys_rates[] = {
1461         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1462         { .div = 0 }
1463 };
1464
1465 static const struct clksel_rate dss1_fck_core_rates[] = {
1466         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1467         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1468         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1469         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1470         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1471         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1472         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1473         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1474         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1475         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1476         { .div = 0 }
1477 };
1478
1479 static const struct clksel dss1_fck_clksel[] = {
1480         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1481         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1482         { .parent = NULL },
1483 };
1484
1485 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1486         .name           = "dss_ick",
1487         .parent         = &l4_ck,       /* really both l3 and l4 */
1488         .prcm_mod       = CORE_MOD,
1489         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1490         .clkdm          = { .name = "dss_clkdm" },
1491         .enable_reg     = CM_ICLKEN1,
1492         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1493         .recalc         = &followparent_recalc,
1494 };
1495
1496 static struct clk dss1_fck = {
1497         .name           = "dss1_fck",
1498         .parent         = &core_ck,             /* Core or sys */
1499         .prcm_mod       = CORE_MOD,
1500         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1501                                 DELAYED_APP,
1502         .clkdm          = { .name = "dss_clkdm" },
1503         .enable_reg     = CM_FCLKEN1,
1504         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1505         .init           = &omap2_init_clksel_parent,
1506         .clksel_reg     = CM_CLKSEL1,
1507         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1508         .clksel         = dss1_fck_clksel,
1509         .recalc         = &omap2_clksel_recalc,
1510         .round_rate     = &omap2_clksel_round_rate,
1511         .set_rate       = &omap2_clksel_set_rate
1512 };
1513
1514 static const struct clksel_rate dss2_fck_sys_rates[] = {
1515         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1516         { .div = 0 }
1517 };
1518
1519 static const struct clksel_rate dss2_fck_48m_rates[] = {
1520         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1521         { .div = 0 }
1522 };
1523
1524 static const struct clksel dss2_fck_clksel[] = {
1525         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1526         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1527         { .parent = NULL }
1528 };
1529
1530 static struct clk dss2_fck = {          /* Alt clk used in power management */
1531         .name           = "dss2_fck",
1532         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1533         .prcm_mod       = CORE_MOD,
1534         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1535                                 DELAYED_APP,
1536         .clkdm          = { .name = "dss_clkdm" },
1537         .enable_reg     = CM_FCLKEN1,
1538         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1539         .init           = &omap2_init_clksel_parent,
1540         .clksel_reg     = CM_CLKSEL1,
1541         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1542         .clksel         = dss2_fck_clksel,
1543         .recalc         = &followparent_recalc,
1544 };
1545
1546 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1547         .name           = "dss_54m_fck",        /* 54m tv clk */
1548         .parent         = &func_54m_ck,
1549         .prcm_mod       = CORE_MOD,
1550         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1551         .clkdm          = { .name = "dss_clkdm" },
1552         .enable_reg     = CM_FCLKEN1,
1553         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1554         .recalc         = &followparent_recalc,
1555 };
1556
1557 /*
1558  * CORE power domain ICLK & FCLK defines.
1559  * Many of the these can have more than one possible parent. Entries
1560  * here will likely have an L4 interface parent, and may have multiple
1561  * functional clock parents.
1562  */
1563 static const struct clksel_rate gpt_alt_rates[] = {
1564         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1565         { .div = 0 }
1566 };
1567
1568 static const struct clksel omap24xx_gpt_clksel[] = {
1569         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1570         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1571         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1572         { .parent = NULL },
1573 };
1574
1575 static struct clk gpt1_ick = {
1576         .name           = "gpt1_ick",
1577         .parent         = &l4_ck,
1578         .prcm_mod       = WKUP_MOD,
1579         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1580         .clkdm          = { .name = "core_l4_clkdm" },
1581         .enable_reg     = CM_ICLKEN,
1582         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1583         .idlest_bit     = OMAP24XX_ST_GPT1_SHIFT,
1584         .recalc         = &followparent_recalc,
1585 };
1586
1587 static struct clk gpt1_fck = {
1588         .name           = "gpt1_fck",
1589         .parent         = &func_32k_ck,
1590         .prcm_mod       = WKUP_MOD,
1591         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1592         .clkdm          = { .name = "core_l4_clkdm" },
1593         .enable_reg     = CM_FCLKEN,
1594         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1595         .init           = &omap2_init_clksel_parent,
1596         .clksel_reg     = CM_CLKSEL1,
1597         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1598         .clksel         = omap24xx_gpt_clksel,
1599         .recalc         = &omap2_clksel_recalc,
1600         .round_rate     = &omap2_clksel_round_rate,
1601         .set_rate       = &omap2_clksel_set_rate
1602 };
1603
1604 static struct clk gpt2_ick = {
1605         .name           = "gpt2_ick",
1606         .parent         = &l4_ck,
1607         .prcm_mod       = CORE_MOD,
1608         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1609         .clkdm          = { .name = "core_l4_clkdm" },
1610         .enable_reg     = CM_ICLKEN1,
1611         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1612         .idlest_bit     = OMAP24XX_ST_GPT2_SHIFT,
1613         .recalc         = &followparent_recalc,
1614 };
1615
1616 static struct clk gpt2_fck = {
1617         .name           = "gpt2_fck",
1618         .parent         = &func_32k_ck,
1619         .prcm_mod       = CORE_MOD,
1620         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621         .clkdm          = { .name = "core_l4_clkdm" },
1622         .enable_reg     = CM_FCLKEN1,
1623         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1624         .init           = &omap2_init_clksel_parent,
1625         .clksel_reg     = CM_CLKSEL2,
1626         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1627         .clksel         = omap24xx_gpt_clksel,
1628         .recalc         = &omap2_clksel_recalc,
1629 };
1630
1631 static struct clk gpt3_ick = {
1632         .name           = "gpt3_ick",
1633         .parent         = &l4_ck,
1634         .prcm_mod       = CORE_MOD,
1635         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1636         .clkdm          = { .name = "core_l4_clkdm" },
1637         .enable_reg     = CM_ICLKEN1,
1638         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1639         .idlest_bit     = OMAP24XX_ST_GPT3_SHIFT,
1640         .recalc         = &followparent_recalc,
1641 };
1642
1643 static struct clk gpt3_fck = {
1644         .name           = "gpt3_fck",
1645         .parent         = &func_32k_ck,
1646         .prcm_mod       = CORE_MOD,
1647         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1648         .clkdm          = { .name = "core_l4_clkdm" },
1649         .enable_reg     = CM_FCLKEN1,
1650         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1651         .init           = &omap2_init_clksel_parent,
1652         .clksel_reg     = CM_CLKSEL2,
1653         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1654         .clksel         = omap24xx_gpt_clksel,
1655         .recalc         = &omap2_clksel_recalc,
1656 };
1657
1658 static struct clk gpt4_ick = {
1659         .name           = "gpt4_ick",
1660         .parent         = &l4_ck,
1661         .prcm_mod       = CORE_MOD,
1662         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1663         .clkdm          = { .name = "core_l4_clkdm" },
1664         .enable_reg     = CM_ICLKEN1,
1665         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1666         .idlest_bit     = OMAP24XX_ST_GPT4_SHIFT,
1667         .recalc         = &followparent_recalc,
1668 };
1669
1670 static struct clk gpt4_fck = {
1671         .name           = "gpt4_fck",
1672         .parent         = &func_32k_ck,
1673         .prcm_mod       = CORE_MOD,
1674         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1675         .clkdm          = { .name = "core_l4_clkdm" },
1676         .enable_reg     = CM_FCLKEN1,
1677         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1678         .init           = &omap2_init_clksel_parent,
1679         .clksel_reg     = CM_CLKSEL2,
1680         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1681         .clksel         = omap24xx_gpt_clksel,
1682         .recalc         = &omap2_clksel_recalc,
1683 };
1684
1685 static struct clk gpt5_ick = {
1686         .name           = "gpt5_ick",
1687         .parent         = &l4_ck,
1688         .prcm_mod       = CORE_MOD,
1689         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1690         .clkdm          = { .name = "core_l4_clkdm" },
1691         .enable_reg     = CM_ICLKEN1,
1692         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1693         .idlest_bit     = OMAP24XX_ST_GPT5_SHIFT,
1694         .recalc         = &followparent_recalc,
1695 };
1696
1697 static struct clk gpt5_fck = {
1698         .name           = "gpt5_fck",
1699         .parent         = &func_32k_ck,
1700         .prcm_mod       = CORE_MOD,
1701         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702         .clkdm          = { .name = "core_l4_clkdm" },
1703         .enable_reg     = CM_FCLKEN1,
1704         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1705         .init           = &omap2_init_clksel_parent,
1706         .clksel_reg     = CM_CLKSEL2,
1707         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1708         .clksel         = omap24xx_gpt_clksel,
1709         .recalc         = &omap2_clksel_recalc,
1710 };
1711
1712 static struct clk gpt6_ick = {
1713         .name           = "gpt6_ick",
1714         .parent         = &l4_ck,
1715         .prcm_mod       = CORE_MOD,
1716         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1717         .clkdm          = { .name = "core_l4_clkdm" },
1718         .enable_reg     = CM_ICLKEN1,
1719         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1720         .idlest_bit     = OMAP24XX_ST_GPT6_SHIFT,
1721         .recalc         = &followparent_recalc,
1722 };
1723
1724 static struct clk gpt6_fck = {
1725         .name           = "gpt6_fck",
1726         .parent         = &func_32k_ck,
1727         .prcm_mod       = CORE_MOD,
1728         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1729         .clkdm          = { .name = "core_l4_clkdm" },
1730         .enable_reg     = CM_FCLKEN1,
1731         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1732         .init           = &omap2_init_clksel_parent,
1733         .clksel_reg     = CM_CLKSEL2,
1734         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1735         .clksel         = omap24xx_gpt_clksel,
1736         .recalc         = &omap2_clksel_recalc,
1737 };
1738
1739 static struct clk gpt7_ick = {
1740         .name           = "gpt7_ick",
1741         .parent         = &l4_ck,
1742         .prcm_mod       = CORE_MOD,
1743         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1744         .clkdm          = { .name = "core_l4_clkdm" },
1745         .enable_reg     = CM_ICLKEN1,
1746         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1747         .idlest_bit     = OMAP24XX_ST_GPT7_SHIFT,
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 static struct clk gpt7_fck = {
1752         .name           = "gpt7_fck",
1753         .parent         = &func_32k_ck,
1754         .prcm_mod       = CORE_MOD,
1755         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1756         .clkdm          = { .name = "core_l4_clkdm" },
1757         .enable_reg     = CM_FCLKEN1,
1758         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1759         .init           = &omap2_init_clksel_parent,
1760         .clksel_reg     = CM_CLKSEL2,
1761         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1762         .clksel         = omap24xx_gpt_clksel,
1763         .recalc         = &omap2_clksel_recalc,
1764 };
1765
1766 static struct clk gpt8_ick = {
1767         .name           = "gpt8_ick",
1768         .parent         = &l4_ck,
1769         .prcm_mod       = CORE_MOD,
1770         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1771         .clkdm          = { .name = "core_l4_clkdm" },
1772         .enable_reg     = CM_ICLKEN1,
1773         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1774         .idlest_bit     = OMAP24XX_ST_GPT8_SHIFT,
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 static struct clk gpt8_fck = {
1779         .name           = "gpt8_fck",
1780         .parent         = &func_32k_ck,
1781         .prcm_mod       = CORE_MOD,
1782         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1783         .clkdm          = { .name = "core_l4_clkdm" },
1784         .enable_reg     = CM_FCLKEN1,
1785         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1786         .init           = &omap2_init_clksel_parent,
1787         .clksel_reg     = CM_CLKSEL2,
1788         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1789         .clksel         = omap24xx_gpt_clksel,
1790         .recalc         = &omap2_clksel_recalc,
1791 };
1792
1793 static struct clk gpt9_ick = {
1794         .name           = "gpt9_ick",
1795         .parent         = &l4_ck,
1796         .prcm_mod       = CORE_MOD,
1797         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1798         .clkdm          = { .name = "core_l4_clkdm" },
1799         .enable_reg     = CM_ICLKEN1,
1800         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1801         .idlest_bit     = OMAP24XX_ST_GPT9_SHIFT,
1802         .recalc         = &followparent_recalc,
1803 };
1804
1805 static struct clk gpt9_fck = {
1806         .name           = "gpt9_fck",
1807         .parent         = &func_32k_ck,
1808         .prcm_mod       = CORE_MOD,
1809         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1810         .clkdm          = { .name = "core_l4_clkdm" },
1811         .enable_reg     = CM_FCLKEN1,
1812         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1813         .init           = &omap2_init_clksel_parent,
1814         .clksel_reg     = CM_CLKSEL2,
1815         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1816         .clksel         = omap24xx_gpt_clksel,
1817         .recalc         = &omap2_clksel_recalc,
1818 };
1819
1820 static struct clk gpt10_ick = {
1821         .name           = "gpt10_ick",
1822         .parent         = &l4_ck,
1823         .prcm_mod       = CORE_MOD,
1824         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1825         .clkdm          = { .name = "core_l4_clkdm" },
1826         .enable_reg     = CM_ICLKEN1,
1827         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1828         .idlest_bit     = OMAP24XX_ST_GPT10_SHIFT,
1829         .recalc         = &followparent_recalc,
1830 };
1831
1832 static struct clk gpt10_fck = {
1833         .name           = "gpt10_fck",
1834         .parent         = &func_32k_ck,
1835         .prcm_mod       = CORE_MOD,
1836         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1837         .clkdm          = { .name = "core_l4_clkdm" },
1838         .enable_reg     = CM_FCLKEN1,
1839         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1840         .init           = &omap2_init_clksel_parent,
1841         .clksel_reg     = CM_CLKSEL2,
1842         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1843         .clksel         = omap24xx_gpt_clksel,
1844         .recalc         = &omap2_clksel_recalc,
1845 };
1846
1847 static struct clk gpt11_ick = {
1848         .name           = "gpt11_ick",
1849         .parent         = &l4_ck,
1850         .prcm_mod       = CORE_MOD,
1851         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1852         .clkdm          = { .name = "core_l4_clkdm" },
1853         .enable_reg     = CM_ICLKEN1,
1854         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1855         .idlest_bit     = OMAP24XX_ST_GPT11_SHIFT,
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk gpt11_fck = {
1860         .name           = "gpt11_fck",
1861         .parent         = &func_32k_ck,
1862         .prcm_mod       = CORE_MOD,
1863         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1864         .clkdm          = { .name = "core_l4_clkdm" },
1865         .enable_reg     = CM_FCLKEN1,
1866         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1867         .init           = &omap2_init_clksel_parent,
1868         .clksel_reg     = CM_CLKSEL2,
1869         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1870         .clksel         = omap24xx_gpt_clksel,
1871         .recalc         = &omap2_clksel_recalc,
1872 };
1873
1874 static struct clk gpt12_ick = {
1875         .name           = "gpt12_ick",
1876         .parent         = &l4_ck,
1877         .prcm_mod       = CORE_MOD,
1878         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1879         .clkdm          = { .name = "core_l4_clkdm" },
1880         .enable_reg     = CM_ICLKEN1,
1881         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1882         .idlest_bit     = OMAP24XX_ST_GPT12_SHIFT,
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk gpt12_fck = {
1887         .name           = "gpt12_fck",
1888         .parent         = &func_32k_ck,
1889         .prcm_mod       = CORE_MOD,
1890         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1891         .clkdm          = { .name = "core_l4_clkdm" },
1892         .enable_reg     = CM_FCLKEN1,
1893         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1894         .init           = &omap2_init_clksel_parent,
1895         .clksel_reg     = CM_CLKSEL2,
1896         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1897         .clksel         = omap24xx_gpt_clksel,
1898         .recalc         = &omap2_clksel_recalc,
1899 };
1900
1901 static struct clk mcbsp1_ick = {
1902         .name           = "mcbsp_ick",
1903         .id             = 1,
1904         .parent         = &l4_ck,
1905         .prcm_mod       = CORE_MOD,
1906         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1907         .clkdm          = { .name = "core_l4_clkdm" },
1908         .enable_reg     = CM_ICLKEN1,
1909         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1910         .idlest_bit     = OMAP24XX_ST_MCBSP1_SHIFT,
1911         .recalc         = &followparent_recalc,
1912 };
1913
1914 static struct clk mcbsp1_fck = {
1915         .name           = "mcbsp_fck",
1916         .id             = 1,
1917         .parent         = &func_96m_ck,
1918         .prcm_mod       = CORE_MOD,
1919         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1920         .clkdm          = { .name = "core_l4_clkdm" },
1921         .enable_reg     = CM_FCLKEN1,
1922         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1923         .recalc         = &followparent_recalc,
1924 };
1925
1926 static struct clk mcbsp2_ick = {
1927         .name           = "mcbsp_ick",
1928         .id             = 2,
1929         .parent         = &l4_ck,
1930         .prcm_mod       = CORE_MOD,
1931         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1932         .clkdm          = { .name = "core_l4_clkdm" },
1933         .enable_reg     = CM_ICLKEN1,
1934         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1935         .idlest_bit     = OMAP24XX_ST_MCBSP2_SHIFT,
1936         .recalc         = &followparent_recalc,
1937 };
1938
1939 static struct clk mcbsp2_fck = {
1940         .name           = "mcbsp_fck",
1941         .id             = 2,
1942         .parent         = &func_96m_ck,
1943         .prcm_mod       = CORE_MOD,
1944         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1945         .clkdm          = { .name = "core_l4_clkdm" },
1946         .enable_reg     = CM_FCLKEN1,
1947         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1948         .recalc         = &followparent_recalc,
1949 };
1950
1951 static struct clk mcbsp3_ick = {
1952         .name           = "mcbsp_ick",
1953         .id             = 3,
1954         .parent         = &l4_ck,
1955         .prcm_mod       = CORE_MOD,
1956         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1957         .clkdm          = { .name = "core_l4_clkdm" },
1958         .enable_reg     = CM_ICLKEN2,
1959         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1960         .idlest_bit     = OMAP2430_ST_MCBSP3_SHIFT,
1961         .recalc         = &followparent_recalc,
1962 };
1963
1964 static struct clk mcbsp3_fck = {
1965         .name           = "mcbsp_fck",
1966         .id             = 3,
1967         .parent         = &func_96m_ck,
1968         .prcm_mod       = CORE_MOD,
1969         .flags          = CLOCK_IN_OMAP243X,
1970         .clkdm          = { .name = "core_l4_clkdm" },
1971         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1972         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk mcbsp4_ick = {
1977         .name           = "mcbsp_ick",
1978         .id             = 4,
1979         .parent         = &l4_ck,
1980         .prcm_mod       = CORE_MOD,
1981         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1982         .clkdm          = { .name = "core_l4_clkdm" },
1983         .enable_reg     = CM_ICLKEN2,
1984         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1985         .idlest_bit     = OMAP2430_ST_MCBSP4_SHIFT,
1986         .recalc         = &followparent_recalc,
1987 };
1988
1989 static struct clk mcbsp4_fck = {
1990         .name           = "mcbsp_fck",
1991         .id             = 4,
1992         .parent         = &func_96m_ck,
1993         .prcm_mod       = CORE_MOD,
1994         .flags          = CLOCK_IN_OMAP243X,
1995         .clkdm          = { .name = "core_l4_clkdm" },
1996         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1997         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1998         .recalc         = &followparent_recalc,
1999 };
2000
2001 static struct clk mcbsp5_ick = {
2002         .name           = "mcbsp_ick",
2003         .id             = 5,
2004         .parent         = &l4_ck,
2005         .prcm_mod       = CORE_MOD,
2006         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2007         .clkdm          = { .name = "core_l4_clkdm" },
2008         .enable_reg     = CM_ICLKEN2,
2009         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2010         .idlest_bit     = OMAP2430_ST_MCBSP5_SHIFT,
2011         .recalc         = &followparent_recalc,
2012 };
2013
2014 static struct clk mcbsp5_fck = {
2015         .name           = "mcbsp_fck",
2016         .id             = 5,
2017         .parent         = &func_96m_ck,
2018         .prcm_mod       = CORE_MOD,
2019         .flags          = CLOCK_IN_OMAP243X,
2020         .clkdm          = { .name = "core_l4_clkdm" },
2021         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2022         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2023         .recalc         = &followparent_recalc,
2024 };
2025
2026 static struct clk mcspi1_ick = {
2027         .name           = "mcspi_ick",
2028         .id             = 1,
2029         .parent         = &l4_ck,
2030         .prcm_mod       = CORE_MOD,
2031         .clkdm          = { .name = "core_l4_clkdm" },
2032         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2033         .enable_reg     = CM_ICLKEN1,
2034         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2035         .idlest_bit     = OMAP24XX_ST_MCSPI1_SHIFT,
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk mcspi1_fck = {
2040         .name           = "mcspi_fck",
2041         .id             = 1,
2042         .parent         = &func_48m_ck,
2043         .prcm_mod       = CORE_MOD,
2044         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2045         .clkdm          = { .name = "core_l4_clkdm" },
2046         .enable_reg     = CM_FCLKEN1,
2047         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2048         .recalc         = &followparent_recalc,
2049 };
2050
2051 static struct clk mcspi2_ick = {
2052         .name           = "mcspi_ick",
2053         .id             = 2,
2054         .parent         = &l4_ck,
2055         .prcm_mod       = CORE_MOD,
2056         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2057         .clkdm          = { .name = "core_l4_clkdm" },
2058         .enable_reg     = CM_ICLKEN1,
2059         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2060         .idlest_bit     = OMAP24XX_ST_MCSPI2_SHIFT,
2061         .recalc         = &followparent_recalc,
2062 };
2063
2064 static struct clk mcspi2_fck = {
2065         .name           = "mcspi_fck",
2066         .id             = 2,
2067         .parent         = &func_48m_ck,
2068         .prcm_mod       = CORE_MOD,
2069         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2070         .clkdm          = { .name = "core_l4_clkdm" },
2071         .enable_reg     = CM_FCLKEN1,
2072         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2073         .recalc         = &followparent_recalc,
2074 };
2075
2076 static struct clk mcspi3_ick = {
2077         .name           = "mcspi_ick",
2078         .id             = 3,
2079         .parent         = &l4_ck,
2080         .prcm_mod       = CORE_MOD,
2081         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2082         .clkdm          = { .name = "core_l4_clkdm" },
2083         .enable_reg     = CM_ICLKEN2,
2084         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2085         .idlest_bit     = OMAP2430_ST_MCSPI3_SHIFT,
2086         .recalc         = &followparent_recalc,
2087 };
2088
2089 static struct clk mcspi3_fck = {
2090         .name           = "mcspi_fck",
2091         .id             = 3,
2092         .parent         = &func_48m_ck,
2093         .prcm_mod       = CORE_MOD,
2094         .flags          = CLOCK_IN_OMAP243X,
2095         .clkdm          = { .name = "core_l4_clkdm" },
2096         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2097         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2098         .recalc         = &followparent_recalc,
2099 };
2100
2101 static struct clk uart1_ick = {
2102         .name           = "uart1_ick",
2103         .parent         = &l4_ck,
2104         .prcm_mod       = CORE_MOD,
2105         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2106         .clkdm          = { .name = "core_l4_clkdm" },
2107         .enable_reg     = CM_ICLKEN1,
2108         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2109         .idlest_bit     = OMAP24XX_ST_UART1_SHIFT,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk uart1_fck = {
2114         .name           = "uart1_fck",
2115         .parent         = &func_48m_ck,
2116         .prcm_mod       = CORE_MOD,
2117         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2118         .clkdm          = { .name = "core_l4_clkdm" },
2119         .enable_reg     = CM_FCLKEN1,
2120         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 static struct clk uart2_ick = {
2125         .name           = "uart2_ick",
2126         .parent         = &l4_ck,
2127         .prcm_mod       = CORE_MOD,
2128         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2129         .clkdm          = { .name = "core_l4_clkdm" },
2130         .enable_reg     = CM_ICLKEN1,
2131         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2132         .idlest_bit     = OMAP24XX_ST_UART2_SHIFT,
2133         .recalc         = &followparent_recalc,
2134 };
2135
2136 static struct clk uart2_fck = {
2137         .name           = "uart2_fck",
2138         .parent         = &func_48m_ck,
2139         .prcm_mod       = CORE_MOD,
2140         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2141         .clkdm          = { .name = "core_l4_clkdm" },
2142         .enable_reg     = CM_FCLKEN1,
2143         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2144         .recalc         = &followparent_recalc,
2145 };
2146
2147 static struct clk uart3_ick = {
2148         .name           = "uart3_ick",
2149         .parent         = &l4_ck,
2150         .prcm_mod       = CORE_MOD,
2151         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2152         .clkdm          = { .name = "core_l4_clkdm" },
2153         .enable_reg     = CM_ICLKEN2,
2154         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2155         .idlest_bit     = OMAP24XX_ST_UART3_SHIFT,
2156         .recalc         = &followparent_recalc,
2157 };
2158
2159 static struct clk uart3_fck = {
2160         .name           = "uart3_fck",
2161         .parent         = &func_48m_ck,
2162         .prcm_mod       = CORE_MOD,
2163         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2164         .clkdm          = { .name = "core_l4_clkdm" },
2165         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2166         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2167         .recalc         = &followparent_recalc,
2168 };
2169
2170 static struct clk gpios_ick = {
2171         .name           = "gpios_ick",
2172         .parent         = &l4_ck,
2173         .prcm_mod       = WKUP_MOD,
2174         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2175         .clkdm          = { .name = "core_l4_clkdm" },
2176         .enable_reg     = CM_ICLKEN,
2177         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2178         .idlest_bit     = OMAP24XX_ST_GPIOS_SHIFT,
2179         .recalc         = &followparent_recalc,
2180 };
2181
2182 static struct clk gpios_fck = {
2183         .name           = "gpios_fck",
2184         .parent         = &func_32k_ck,
2185         .prcm_mod       = WKUP_MOD,
2186         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2187         .clkdm          = { .name = "prm_clkdm" },
2188         .enable_reg     = CM_FCLKEN,
2189         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2190         .idlest_bit     = OMAP24XX_ST_GPIOS_SHIFT,
2191         .recalc         = &followparent_recalc,
2192 };
2193
2194 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2195 static struct clk mpu_wdt_ick = {
2196         .name           = "mpu_wdt_ick",
2197         .parent         = &l4_ck,
2198         .prcm_mod       = WKUP_MOD,
2199         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2200         .clkdm          = { .name = "prm_clkdm" },
2201         .enable_reg     = CM_ICLKEN,
2202         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2203         .idlest_bit     = OMAP24XX_ST_MPU_WDT_SHIFT,
2204         .recalc         = &followparent_recalc,
2205 };
2206
2207 /* aka WDT2 */
2208 static struct clk mpu_wdt_fck = {
2209         .name           = "mpu_wdt_fck",
2210         .parent         = &func_32k_ck,
2211         .prcm_mod       = WKUP_MOD,
2212         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2213         .clkdm          = { .name = "prm_clkdm" },
2214         .enable_reg     = CM_FCLKEN,
2215         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2216         .idlest_bit     = OMAP24XX_ST_MPU_WDT_SHIFT,
2217         .recalc         = &followparent_recalc,
2218 };
2219
2220 static struct clk sync_32k_ick = {
2221         .name           = "sync_32k_ick",
2222         .parent         = &l4_ck,
2223         .prcm_mod       = WKUP_MOD,
2224         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2225                                 ENABLE_ON_INIT | WAIT_READY,
2226         .clkdm          = { .name = "core_l4_clkdm" },
2227         .enable_reg     = CM_ICLKEN,
2228         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2229         .idlest_bit     = OMAP24XX_ST_32KSYNC_SHIFT,
2230         .recalc         = &followparent_recalc,
2231 };
2232
2233 /* REVISIT: parent is really wu_l4_iclk */
2234 static struct clk wdt1_ick = {
2235         .name           = "wdt1_ick",
2236         .parent         = &l4_ck,
2237         .prcm_mod       = WKUP_MOD,
2238         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2239         .clkdm          = { .name = "prm_clkdm" },
2240         .enable_reg     = CM_ICLKEN,
2241         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2242         .idlest_bit     = OMAP24XX_ST_WDT1_SHIFT,
2243         .recalc         = &followparent_recalc,
2244 };
2245
2246 static struct clk omapctrl_ick = {
2247         .name           = "omapctrl_ick",
2248         .parent         = &l4_ck,
2249         .prcm_mod       = WKUP_MOD,
2250         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2251                                 ENABLE_ON_INIT,
2252         .clkdm          = { .name = "core_l4_clkdm" },
2253         .enable_reg     = CM_ICLKEN,
2254         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2255         .idlest_bit     = OMAP24XX_ST_OMAPCTRL_SHIFT,
2256         .recalc         = &followparent_recalc,
2257 };
2258
2259 static struct clk icr_ick = {
2260         .name           = "icr_ick",
2261         .parent         = &l4_ck,
2262         .prcm_mod       = WKUP_MOD,
2263         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2264         .clkdm          = { .name = "core_l4_clkdm" },
2265         .enable_reg     = CM_ICLKEN,
2266         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2267         .idlest_bit     = OMAP2430_ST_ICR_SHIFT,
2268         .recalc         = &followparent_recalc,
2269 };
2270
2271 static struct clk cam_ick = {
2272         .name           = "cam_ick",
2273         .parent         = &l4_ck,
2274         .prcm_mod       = CORE_MOD,
2275         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2276         .clkdm          = { .name = "core_l4_clkdm" },
2277         .enable_reg     = CM_ICLKEN1,
2278         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2279         .recalc         = &followparent_recalc,
2280 };
2281
2282 /*
2283  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2284  * split into two separate clocks, since the parent clocks are different
2285  * and the clockdomains are also different.
2286  */
2287 static struct clk cam_fck = {
2288         .name           = "cam_fck",
2289         .parent         = &func_96m_ck,
2290         .prcm_mod       = CORE_MOD,
2291         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2292         .clkdm          = { .name = "core_l3_clkdm" },
2293         .enable_reg     = CM_FCLKEN1,
2294         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2295         .recalc         = &followparent_recalc,
2296 };
2297
2298 static struct clk mailboxes_ick = {
2299         .name           = "mailboxes_ick",
2300         .parent         = &l4_ck,
2301         .prcm_mod       = CORE_MOD,
2302         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2303         .clkdm          = { .name = "core_l4_clkdm" },
2304         .enable_reg     = CM_ICLKEN1,
2305         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2306         .idlest_bit     = OMAP24XX_ST_MAILBOXES_SHIFT,
2307         .recalc         = &followparent_recalc,
2308 };
2309
2310 static struct clk wdt4_ick = {
2311         .name           = "wdt4_ick",
2312         .parent         = &l4_ck,
2313         .prcm_mod       = CORE_MOD,
2314         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2315         .clkdm          = { .name = "core_l4_clkdm" },
2316         .enable_reg     = CM_ICLKEN1,
2317         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2318         .idlest_bit     = OMAP24XX_ST_WDT4_SHIFT,
2319         .recalc         = &followparent_recalc,
2320 };
2321
2322 static struct clk wdt4_fck = {
2323         .name           = "wdt4_fck",
2324         .parent         = &func_32k_ck,
2325         .prcm_mod       = CORE_MOD,
2326         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2327         .clkdm          = { .name = "core_l4_clkdm" },
2328         .enable_reg     = CM_FCLKEN1,
2329         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2330         .recalc         = &followparent_recalc,
2331 };
2332
2333 static struct clk wdt3_ick = {
2334         .name           = "wdt3_ick",
2335         .parent         = &l4_ck,
2336         .prcm_mod       = CORE_MOD,
2337         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2338         .clkdm          = { .name = "core_l4_clkdm" },
2339         .enable_reg     = CM_ICLKEN1,
2340         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2341         .idlest_bit     = OMAP2420_ST_WDT3_SHIFT,
2342         .recalc         = &followparent_recalc,
2343 };
2344
2345 static struct clk wdt3_fck = {
2346         .name           = "wdt3_fck",
2347         .parent         = &func_32k_ck,
2348         .prcm_mod       = CORE_MOD,
2349         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2350         .clkdm          = { .name = "core_l4_clkdm" },
2351         .enable_reg     = CM_FCLKEN1,
2352         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2353         .enable_bit     = OMAP2420_ST_WDT3_SHIFT,
2354         .recalc         = &followparent_recalc,
2355 };
2356
2357 static struct clk mspro_ick = {
2358         .name           = "mspro_ick",
2359         .parent         = &l4_ck,
2360         .prcm_mod       = CORE_MOD,
2361         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2362         .clkdm          = { .name = "core_l4_clkdm" },
2363         .enable_reg     = CM_ICLKEN1,
2364         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2365         .idlest_bit     = OMAP24XX_ST_MSPRO_SHIFT,
2366         .recalc         = &followparent_recalc,
2367 };
2368
2369 static struct clk mspro_fck = {
2370         .name           = "mspro_fck",
2371         .parent         = &func_96m_ck,
2372         .prcm_mod       = CORE_MOD,
2373         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2374         .clkdm          = { .name = "core_l4_clkdm" },
2375         .enable_reg     = CM_FCLKEN1,
2376         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2377         .idlest_bit     = OMAP24XX_ST_MSPRO_SHIFT,
2378         .recalc         = &followparent_recalc,
2379 };
2380
2381 static struct clk mmc_ick = {
2382         .name           = "mmc_ick",
2383         .parent         = &l4_ck,
2384         .prcm_mod       = CORE_MOD,
2385         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2386         .clkdm          = { .name = "core_l4_clkdm" },
2387         .enable_reg     = CM_ICLKEN1,
2388         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2389         .idlest_bit     = OMAP2420_ST_MMC_SHIFT,
2390         .recalc         = &followparent_recalc,
2391 };
2392
2393 static struct clk mmc_fck = {
2394         .name           = "mmc_fck",
2395         .parent         = &func_96m_ck,
2396         .prcm_mod       = CORE_MOD,
2397         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2398         .clkdm          = { .name = "core_l4_clkdm" },
2399         .enable_reg     = CM_FCLKEN1,
2400         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2401         .idlest_bit     = OMAP2420_ST_MMC_SHIFT,
2402         .recalc         = &followparent_recalc,
2403 };
2404
2405 static struct clk fac_ick = {
2406         .name           = "fac_ick",
2407         .parent         = &l4_ck,
2408         .prcm_mod       = CORE_MOD,
2409         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2410         .clkdm          = { .name = "core_l4_clkdm" },
2411         .enable_reg     = CM_ICLKEN1,
2412         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2413         .idlest_bit     = OMAP24XX_ST_FAC_SHIFT,
2414         .recalc         = &followparent_recalc,
2415 };
2416
2417 static struct clk fac_fck = {
2418         .name           = "fac_fck",
2419         .parent         = &func_12m_ck,
2420         .prcm_mod       = CORE_MOD,
2421         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2422         .clkdm          = { .name = "core_l4_clkdm" },
2423         .enable_reg     = CM_FCLKEN1,
2424         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2425         .idlest_bit     = OMAP24XX_ST_FAC_SHIFT,
2426         .recalc         = &followparent_recalc,
2427 };
2428
2429 static struct clk eac_ick = {
2430         .name           = "eac_ick",
2431         .parent         = &l4_ck,
2432         .prcm_mod       = CORE_MOD,
2433         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2434         .clkdm          = { .name = "core_l4_clkdm" },
2435         .enable_reg     = CM_ICLKEN1,
2436         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2437         .idlest_bit     = OMAP2420_ST_EAC_SHIFT,
2438         .recalc         = &followparent_recalc,
2439 };
2440
2441 static struct clk eac_fck = {
2442         .name           = "eac_fck",
2443         .parent         = &func_96m_ck,
2444         .prcm_mod       = CORE_MOD,
2445         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2446         .clkdm          = { .name = "core_l4_clkdm" },
2447         .enable_reg     = CM_FCLKEN1,
2448         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2449         .idlest_bit     = OMAP2420_ST_EAC_SHIFT,
2450         .recalc         = &followparent_recalc,
2451 };
2452
2453 static struct clk hdq_ick = {
2454         .name           = "hdq_ick",
2455         .parent         = &l4_ck,
2456         .prcm_mod       = CORE_MOD,
2457         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2458         .clkdm          = { .name = "core_l4_clkdm" },
2459         .enable_reg     = CM_ICLKEN1,
2460         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2461         .idlest_bit     = OMAP24XX_ST_HDQ_SHIFT,
2462         .recalc         = &followparent_recalc,
2463 };
2464
2465 static struct clk hdq_fck = {
2466         .name           = "hdq_fck",
2467         .parent         = &func_12m_ck,
2468         .prcm_mod       = CORE_MOD,
2469         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2470         .clkdm          = { .name = "core_l4_clkdm" },
2471         .enable_reg     = CM_FCLKEN1,
2472         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2473         .idlest_bit     = OMAP24XX_ST_HDQ_SHIFT,
2474         .recalc         = &followparent_recalc,
2475 };
2476
2477 static struct clk i2c2_ick = {
2478         .name           = "i2c_ick",
2479         .id             = 2,
2480         .parent         = &l4_ck,
2481         .prcm_mod       = CORE_MOD,
2482         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2483         .clkdm          = { .name = "core_l4_clkdm" },
2484         .enable_reg     = CM_ICLKEN1,
2485         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2486         .idlest_bit     = OMAP2420_ST_I2C2_SHIFT,
2487         .recalc         = &followparent_recalc,
2488 };
2489
2490 static struct clk i2c2_fck = {
2491         .name           = "i2c_fck",
2492         .id             = 2,
2493         .parent         = &func_12m_ck,
2494         .prcm_mod       = CORE_MOD,
2495         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2496         .clkdm          = { .name = "core_l4_clkdm" },
2497         .enable_reg     = CM_FCLKEN1,
2498         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2499         .idlest_bit     = OMAP2420_ST_I2C2_SHIFT,
2500         .recalc         = &followparent_recalc,
2501 };
2502
2503 static struct clk i2chs2_fck = {
2504         .name           = "i2c_fck",
2505         .id             = 2,
2506         .parent         = &func_96m_ck,
2507         .prcm_mod       = CORE_MOD,
2508         .flags          = CLOCK_IN_OMAP243X,
2509         .clkdm          = { .name = "core_l4_clkdm" },
2510         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2511         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2512         .recalc         = &followparent_recalc,
2513 };
2514
2515 static struct clk i2c1_ick = {
2516         .name           = "i2c_ick",
2517         .id             = 1,
2518         .parent         = &l4_ck,
2519         .prcm_mod       = CORE_MOD,
2520         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2521         .clkdm          = { .name = "core_l4_clkdm" },
2522         .enable_reg     = CM_ICLKEN1,
2523         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2524         .idlest_bit     = OMAP2420_ST_I2C1_SHIFT,
2525         .recalc         = &followparent_recalc,
2526 };
2527
2528 static struct clk i2c1_fck = {
2529         .name           = "i2c_fck",
2530         .id             = 1,
2531         .parent         = &func_12m_ck,
2532         .prcm_mod       = CORE_MOD,
2533         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2534         .clkdm          = { .name = "core_l4_clkdm" },
2535         .enable_reg     = CM_FCLKEN1,
2536         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2537         .idlest_bit     = OMAP2420_ST_I2C1_SHIFT,
2538         .recalc         = &followparent_recalc,
2539 };
2540
2541 static struct clk i2chs1_fck = {
2542         .name           = "i2c_fck",
2543         .id             = 1,
2544         .parent         = &func_96m_ck,
2545         .prcm_mod       = CORE_MOD,
2546         .flags          = CLOCK_IN_OMAP243X,
2547         .clkdm          = { .name = "core_l4_clkdm" },
2548         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2549         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2550         .recalc         = &followparent_recalc,
2551 };
2552
2553 static struct clk gpmc_fck = {
2554         .name           = "gpmc_fck",
2555         .parent         = &core_l3_ck,
2556         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2557                                 ENABLE_ON_INIT,
2558         .clkdm          = { .name = "core_l3_clkdm" },
2559         .recalc         = &followparent_recalc,
2560 };
2561
2562 static struct clk sdma_fck = {
2563         .name           = "sdma_fck",
2564         .parent         = &core_l3_ck,
2565         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2566         .clkdm          = { .name = "core_l3_clkdm" },
2567         .recalc         = &followparent_recalc,
2568 };
2569
2570 static struct clk sdma_ick = {
2571         .name           = "sdma_ick",
2572         .parent         = &l4_ck,
2573         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2574         .clkdm          = { .name = "core_l3_clkdm" },
2575         .recalc         = &followparent_recalc,
2576 };
2577
2578 static struct clk vlynq_ick = {
2579         .name           = "vlynq_ick",
2580         .parent         = &core_l3_ck,
2581         .prcm_mod       = CORE_MOD,
2582         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2583         .clkdm          = { .name = "core_l3_clkdm" },
2584         .enable_reg     = CM_ICLKEN1,
2585         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2586         .idlest_bit     = OMAP2420_ST_VLYNQ_SHIFT,
2587         .recalc         = &followparent_recalc,
2588 };
2589
2590 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2591         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2592         { .div = 0 }
2593 };
2594
2595 static const struct clksel_rate vlynq_fck_core_rates[] = {
2596         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2597         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2598         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2599         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2600         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2601         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2602         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2603         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2604         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2605         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2606         { .div = 0 }
2607 };
2608
2609 static const struct clksel vlynq_fck_clksel[] = {
2610         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2611         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2612         { .parent = NULL }
2613 };
2614
2615 static struct clk vlynq_fck = {
2616         .name           = "vlynq_fck",
2617         .parent         = &func_96m_ck,
2618         .prcm_mod       = CORE_MOD,
2619         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | WAIT_READY,
2620         .clkdm          = { .name = "core_l3_clkdm" },
2621         .enable_reg     = CM_FCLKEN1,
2622         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2623         .idlest_bit     = OMAP2420_ST_VLYNQ_SHIFT,
2624         .init           = &omap2_init_clksel_parent,
2625         .clksel_reg     = CM_CLKSEL1,
2626         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2627         .clksel         = vlynq_fck_clksel,
2628         .recalc         = &omap2_clksel_recalc,
2629         .round_rate     = &omap2_clksel_round_rate,
2630         .set_rate       = &omap2_clksel_set_rate
2631 };
2632
2633 static struct clk sdrc_ick = {
2634         .name           = "sdrc_ick",
2635         .parent         = &l4_ck,
2636         .prcm_mod       = CORE_MOD,
2637         .flags          = CLOCK_IN_OMAP243X | WAIT_READY | ENABLE_ON_INIT,
2638         .clkdm          = { .name = "core_l4_clkdm" },
2639         .enable_reg     = CM_ICLKEN3,
2640         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2641         .idlest_bit     = OMAP2430_ST_SDRC_SHIFT,
2642         .recalc         = &followparent_recalc,
2643 };
2644
2645 static struct clk des_ick = {
2646         .name           = "des_ick",
2647         .parent         = &l4_ck,
2648         .prcm_mod       = CORE_MOD,
2649         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2650         .clkdm          = { .name = "core_l4_clkdm" },
2651         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2652         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2653         .idlest_bit     = OMAP24XX_ST_DES_SHIFT,
2654         .recalc         = &followparent_recalc,
2655 };
2656
2657 static struct clk sha_ick = {
2658         .name           = "sha_ick",
2659         .parent         = &l4_ck,
2660         .prcm_mod       = CORE_MOD,
2661         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2662         .clkdm          = { .name = "core_l4_clkdm" },
2663         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2664         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2665         .idlest_bit     = OMAP24XX_ST_SHA_SHIFT,
2666         .recalc         = &followparent_recalc,
2667 };
2668
2669 static struct clk rng_ick = {
2670         .name           = "rng_ick",
2671         .parent         = &l4_ck,
2672         .prcm_mod       = CORE_MOD,
2673         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2674         .clkdm          = { .name = "core_l4_clkdm" },
2675         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2676         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2677         .idlest_bit     = OMAP24XX_ST_RNG_SHIFT,
2678         .recalc         = &followparent_recalc,
2679 };
2680
2681 static struct clk aes_ick = {
2682         .name           = "aes_ick",
2683         .parent         = &l4_ck,
2684         .prcm_mod       = CORE_MOD,
2685         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2686         .clkdm          = { .name = "core_l4_clkdm" },
2687         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2688         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2689         .idlest_bit     = OMAP24XX_ST_AES_SHIFT,
2690         .recalc         = &followparent_recalc,
2691 };
2692
2693 static struct clk pka_ick = {
2694         .name           = "pka_ick",
2695         .parent         = &l4_ck,
2696         .prcm_mod       = CORE_MOD,
2697         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2698         .clkdm          = { .name = "core_l4_clkdm" },
2699         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2700         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2701         .idlest_bit     = OMAP24XX_ST_PKA_SHIFT,
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk usb_fck = {
2706         .name           = "usb_fck",
2707         .parent         = &func_48m_ck,
2708         .prcm_mod       = CORE_MOD,
2709         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2710         .clkdm          = { .name = "core_l3_clkdm" },
2711         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2712         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2713         .idlest_bit     = OMAP24XX_ST_USB_SHIFT,
2714         .recalc         = &followparent_recalc,
2715 };
2716
2717 static struct clk usbhs_ick = {
2718         .name           = "usbhs_ick",
2719         .parent         = &core_l3_ck,
2720         .prcm_mod       = CORE_MOD,
2721         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2722         .clkdm          = { .name = "core_l3_clkdm" },
2723         .enable_reg     = CM_ICLKEN2,
2724         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2725         .idlest_bit     = OMAP2430_ST_USBHS_SHIFT,
2726         .recalc         = &followparent_recalc,
2727 };
2728
2729 static struct clk mmchs1_ick = {
2730         .name           = "mmchs_ick",
2731         .parent         = &l4_ck,
2732         .prcm_mod       = CORE_MOD,
2733         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2734         .clkdm          = { .name = "core_l4_clkdm" },
2735         .enable_reg     = CM_ICLKEN2,
2736         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2737         .idlest_bit     = OMAP2430_ST_MMCHS1_SHIFT,
2738         .recalc         = &followparent_recalc,
2739 };
2740
2741 static struct clk mmchs1_fck = {
2742         .name           = "mmchs_fck",
2743         .parent         = &func_96m_ck,
2744         .prcm_mod       = CORE_MOD,
2745         .flags          = CLOCK_IN_OMAP243X,
2746         .clkdm          = { .name = "core_l3_clkdm" },
2747         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2748         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2749         .recalc         = &followparent_recalc,
2750 };
2751
2752 static struct clk mmchs2_ick = {
2753         .name           = "mmchs_ick",
2754         .id             = 1,
2755         .parent         = &l4_ck,
2756         .prcm_mod       = CORE_MOD,
2757         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2758         .clkdm          = { .name = "core_l4_clkdm" },
2759         .enable_reg     = CM_ICLKEN2,
2760         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2761         .idlest_bit     = OMAP2430_ST_MMCHS2_SHIFT,
2762         .recalc         = &followparent_recalc,
2763 };
2764
2765 static struct clk mmchs2_fck = {
2766         .name           = "mmchs_fck",
2767         .id             = 1,
2768         .parent         = &func_96m_ck,
2769         .prcm_mod       = CORE_MOD,
2770         .flags          = CLOCK_IN_OMAP243X,
2771         .clkdm          = { .name = "core_l4_clkdm" },
2772         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2773         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2774         .recalc         = &followparent_recalc,
2775 };
2776
2777 static struct clk gpio5_ick = {
2778         .name           = "gpio5_ick",
2779         .parent         = &l4_ck,
2780         .prcm_mod       = CORE_MOD,
2781         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2782         .clkdm          = { .name = "core_l4_clkdm" },
2783         .enable_reg     = CM_ICLKEN2,
2784         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2785         .idlest_bit     = OMAP2430_ST_GPIO5_SHIFT,
2786         .recalc         = &followparent_recalc,
2787 };
2788
2789 static struct clk gpio5_fck = {
2790         .name           = "gpio5_fck",
2791         .parent         = &func_32k_ck,
2792         .prcm_mod       = CORE_MOD,
2793         .flags          = CLOCK_IN_OMAP243X,
2794         .clkdm          = { .name = "core_l4_clkdm" },
2795         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2796         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2797         .recalc         = &followparent_recalc,
2798 };
2799
2800 static struct clk mdm_intc_ick = {
2801         .name           = "mdm_intc_ick",
2802         .parent         = &l4_ck,
2803         .prcm_mod       = CORE_MOD,
2804         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2805         .clkdm          = { .name = "core_l4_clkdm" },
2806         .enable_reg     = CM_ICLKEN2,
2807         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2808         .idlest_bit     = OMAP2430_ST_MDM_INTC_SHIFT,
2809         .recalc         = &followparent_recalc,
2810 };
2811
2812 static struct clk mmchsdb1_fck = {
2813         .name           = "mmchsdb_fck",
2814         .parent         = &func_32k_ck,
2815         .prcm_mod       = CORE_MOD,
2816         .flags          = CLOCK_IN_OMAP243X,
2817         .clkdm          = { .name = "core_l4_clkdm" },
2818         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2819         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2820         .recalc         = &followparent_recalc,
2821 };
2822
2823 static struct clk mmchsdb2_fck = {
2824         .name           = "mmchsdb_fck",
2825         .id             = 1,
2826         .parent         = &func_32k_ck,
2827         .prcm_mod       = CORE_MOD,
2828         .flags          = CLOCK_IN_OMAP243X,
2829         .clkdm          = { .name = "core_l4_clkdm" },
2830         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2831         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2832         .recalc         = &followparent_recalc,
2833 };
2834
2835 /*
2836  * This clock is a composite clock which does entire set changes then
2837  * forces a rebalance. It keys on the MPU speed, but it really could
2838  * be any key speed part of a set in the rate table.
2839  *
2840  * to really change a set, you need memory table sets which get changed
2841  * in sram, pre-notifiers & post notifiers, changing the top set, without
2842  * having low level display recalc's won't work... this is why dpm notifiers
2843  * work, isr's off, walk a list of clocks already _off_ and not messing with
2844  * the bus.
2845  *
2846  * This clock should have no parent. It embodies the entire upper level
2847  * active set. A parent will mess up some of the init also.
2848  */
2849 static struct clk virt_prcm_set = {
2850         .name           = "virt_prcm_set",
2851         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2852                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2853         .clkdm          = { .name = "virt_opp_clkdm" },
2854         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2855         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2856         .set_rate       = &omap2_select_table_rate,
2857         .round_rate     = &omap2_round_to_table_rate,
2858 };
2859
2860 static struct clk *onchip_24xx_clks[] __initdata = {
2861         /* external root sources */
2862         &func_32k_ck,
2863         &osc_ck,
2864         &sys_ck,
2865         &alt_ck,
2866         /* internal analog sources */
2867         &dpll_ck,
2868         &apll96_ck,
2869         &apll54_ck,
2870         /* internal prcm root sources */
2871         &func_54m_ck,
2872         &core_ck,
2873         &func_96m_ck,
2874         &func_48m_ck,
2875         &func_12m_ck,
2876         &wdt1_osc_ck,
2877         &sys_clkout_src,
2878         &sys_clkout,
2879         &sys_clkout2_src,
2880         &sys_clkout2,
2881         &emul_ck,
2882         /* mpu domain clocks */
2883         &mpu_ck,
2884         /* dsp domain clocks */
2885         &dsp_fck,
2886         &dsp_irate_ick,
2887         &dsp_ick,               /* 242x */
2888         &iva2_1_ick,            /* 243x */
2889         &iva1_ifck,             /* 242x */
2890         &iva1_mpu_int_ifck,     /* 242x */
2891         /* GFX domain clocks */
2892         &gfx_3d_fck,
2893         &gfx_2d_fck,
2894         &gfx_ick,
2895         /* Modem domain clocks */
2896         &mdm_ick,
2897         &mdm_osc_ck,
2898         /* DSS domain clocks */
2899         &dss_ick,
2900         &dss1_fck,
2901         &dss2_fck,
2902         &dss_54m_fck,
2903         /* L3 domain clocks */
2904         &core_l3_ck,
2905         &ssi_ssr_sst_fck,
2906         &usb_l4_ick,
2907         /* L4 domain clocks */
2908         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2909         &ssi_l4_ick,
2910         /* virtual meta-group clock */
2911         &virt_prcm_set,
2912         /* general l4 interface ck, multi-parent functional clk */
2913         &gpt1_ick,
2914         &gpt1_fck,
2915         &gpt2_ick,
2916         &gpt2_fck,
2917         &gpt3_ick,
2918         &gpt3_fck,
2919         &gpt4_ick,
2920         &gpt4_fck,
2921         &gpt5_ick,
2922         &gpt5_fck,
2923         &gpt6_ick,
2924         &gpt6_fck,
2925         &gpt7_ick,
2926         &gpt7_fck,
2927         &gpt8_ick,
2928         &gpt8_fck,
2929         &gpt9_ick,
2930         &gpt9_fck,
2931         &gpt10_ick,
2932         &gpt10_fck,
2933         &gpt11_ick,
2934         &gpt11_fck,
2935         &gpt12_ick,
2936         &gpt12_fck,
2937         &mcbsp1_ick,
2938         &mcbsp1_fck,
2939         &mcbsp2_ick,
2940         &mcbsp2_fck,
2941         &mcbsp3_ick,
2942         &mcbsp3_fck,
2943         &mcbsp4_ick,
2944         &mcbsp4_fck,
2945         &mcbsp5_ick,
2946         &mcbsp5_fck,
2947         &mcspi1_ick,
2948         &mcspi1_fck,
2949         &mcspi2_ick,
2950         &mcspi2_fck,
2951         &mcspi3_ick,
2952         &mcspi3_fck,
2953         &uart1_ick,
2954         &uart1_fck,
2955         &uart2_ick,
2956         &uart2_fck,
2957         &uart3_ick,
2958         &uart3_fck,
2959         &gpios_ick,
2960         &gpios_fck,
2961         &mpu_wdt_ick,
2962         &mpu_wdt_fck,
2963         &sync_32k_ick,
2964         &wdt1_ick,
2965         &omapctrl_ick,
2966         &icr_ick,
2967         &cam_fck,
2968         &cam_ick,
2969         &mailboxes_ick,
2970         &wdt4_ick,
2971         &wdt4_fck,
2972         &wdt3_ick,
2973         &wdt3_fck,
2974         &mspro_ick,
2975         &mspro_fck,
2976         &mmc_ick,
2977         &mmc_fck,
2978         &fac_ick,
2979         &fac_fck,
2980         &eac_ick,
2981         &eac_fck,
2982         &hdq_ick,
2983         &hdq_fck,
2984         &i2c1_ick,
2985         &i2c1_fck,
2986         &i2chs1_fck,
2987         &i2c2_ick,
2988         &i2c2_fck,
2989         &i2chs2_fck,
2990         &gpmc_fck,
2991         &sdma_fck,
2992         &sdma_ick,
2993         &vlynq_ick,
2994         &vlynq_fck,
2995         &sdrc_ick,
2996         &des_ick,
2997         &sha_ick,
2998         &rng_ick,
2999         &aes_ick,
3000         &pka_ick,
3001         &usb_fck,
3002         &usbhs_ick,
3003         &mmchs1_ick,
3004         &mmchs1_fck,
3005         &mmchs2_ick,
3006         &mmchs2_fck,
3007         &gpio5_ick,
3008         &gpio5_fck,
3009         &mdm_intc_ick,
3010         &mmchsdb1_fck,
3011         &mmchsdb2_fck,
3012 };
3013
3014 #endif
3015