2 * linux/arch/arm/mach-omap2/clock24xx.h
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
23 #include "prm-regbits-24xx.h"
24 #include "cm-regbits-24xx.h"
27 static void omap2_table_mpu_recalc(struct clk *clk);
28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30 static void omap2_sys_clk_recalc(struct clk *clk);
31 static void omap2_osc_clk_recalc(struct clk *clk);
32 static void omap2_sys_clk_recalc(struct clk *clk);
33 static void omap2_dpllcore_recalc(struct clk *clk);
34 static int omap2_clk_fixed_enable(struct clk *clk);
35 static void omap2_clk_fixed_disable(struct clk *clk);
36 static int omap2_enable_osc_ck(struct clk *clk);
37 static void omap2_disable_osc_ck(struct clk *clk);
38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
42 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
45 unsigned long xtal_speed; /* crystal rate */
46 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
47 unsigned long mpu_speed; /* speed of MPU */
48 unsigned long cm_clksel_mpu; /* mpu divider */
49 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
50 unsigned long cm_clksel_gfx; /* gfx dividers */
51 unsigned long cm_clksel1_core; /* major subsystem dividers */
52 unsigned long cm_clksel1_pll; /* m,n */
53 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
54 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
55 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
60 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
61 * These configurations are characterized by voltage and speed for clocks.
62 * The device is only validated for certain combinations. One way to express
63 * these combinations is via the 'ratio's' which the clocks operate with
64 * respect to each other. These ratio sets are for a given voltage/DPLL
65 * setting. All configurations can be described by a DPLL setting and a ratio
66 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
68 * 2430 differs from 2420 in that there are no more phase synchronizers used.
69 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
70 * 2430 (iva2.1, NOdsp, mdm)
73 /* Core fields for cm_clksel, not ratio governed */
74 #define RX_CLKSEL_DSS1 (0x10 << 8)
75 #define RX_CLKSEL_DSS2 (0x0 << 13)
76 #define RX_CLKSEL_SSI (0x5 << 20)
78 /*-------------------------------------------------------------------------
80 *-------------------------------------------------------------------------*/
82 /* 2430 Ratio's, 2430-Ratio Config 1 */
83 #define R1_CLKSEL_L3 (4 << 0)
84 #define R1_CLKSEL_L4 (2 << 5)
85 #define R1_CLKSEL_USB (4 << 25)
86 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
87 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
88 R1_CLKSEL_L4 | R1_CLKSEL_L3
89 #define R1_CLKSEL_MPU (2 << 0)
90 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
91 #define R1_CLKSEL_DSP (2 << 0)
92 #define R1_CLKSEL_DSP_IF (2 << 5)
93 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
94 #define R1_CLKSEL_GFX (2 << 0)
95 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
96 #define R1_CLKSEL_MDM (4 << 0)
97 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
99 /* 2430-Ratio Config 2 */
100 #define R2_CLKSEL_L3 (6 << 0)
101 #define R2_CLKSEL_L4 (2 << 5)
102 #define R2_CLKSEL_USB (2 << 25)
103 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
104 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
105 R2_CLKSEL_L4 | R2_CLKSEL_L3
106 #define R2_CLKSEL_MPU (2 << 0)
107 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
108 #define R2_CLKSEL_DSP (2 << 0)
109 #define R2_CLKSEL_DSP_IF (3 << 5)
110 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
111 #define R2_CLKSEL_GFX (2 << 0)
112 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
113 #define R2_CLKSEL_MDM (6 << 0)
114 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
116 /* 2430-Ratio Bootm (BYPASS) */
117 #define RB_CLKSEL_L3 (1 << 0)
118 #define RB_CLKSEL_L4 (1 << 5)
119 #define RB_CLKSEL_USB (1 << 25)
120 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
121 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
122 RB_CLKSEL_L4 | RB_CLKSEL_L3
123 #define RB_CLKSEL_MPU (1 << 0)
124 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
125 #define RB_CLKSEL_DSP (1 << 0)
126 #define RB_CLKSEL_DSP_IF (1 << 5)
127 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
128 #define RB_CLKSEL_GFX (1 << 0)
129 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
130 #define RB_CLKSEL_MDM (1 << 0)
131 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
133 /* 2420 Ratio Equivalents */
134 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
135 #define RXX_CLKSEL_SSI (0x8 << 20)
137 /* 2420-PRCM III 532MHz core */
138 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
139 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
140 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
141 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
142 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
143 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
145 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
146 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
147 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
148 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
149 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
150 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
151 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
152 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
153 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
155 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
156 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
158 /* 2420-PRCM II 600MHz core */
159 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
160 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
161 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
162 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
163 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
164 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
165 RII_CLKSEL_L4 | RII_CLKSEL_L3
166 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
167 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
168 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
169 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
170 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
171 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
172 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
173 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
174 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
176 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
177 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
179 /* 2420-PRCM I 660MHz core */
180 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
181 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
182 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
183 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
184 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
185 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
186 RI_CLKSEL_L4 | RI_CLKSEL_L3
187 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
188 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
189 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
190 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
191 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
192 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
193 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
194 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
195 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
197 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
198 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
200 /* 2420-PRCM VII (boot) */
201 #define RVII_CLKSEL_L3 (1 << 0)
202 #define RVII_CLKSEL_L4 (1 << 5)
203 #define RVII_CLKSEL_DSS1 (1 << 8)
204 #define RVII_CLKSEL_DSS2 (0 << 13)
205 #define RVII_CLKSEL_VLYNQ (1 << 15)
206 #define RVII_CLKSEL_SSI (1 << 20)
207 #define RVII_CLKSEL_USB (1 << 25)
209 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
210 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
211 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
213 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
214 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
216 #define RVII_CLKSEL_DSP (1 << 0)
217 #define RVII_CLKSEL_DSP_IF (1 << 5)
218 #define RVII_SYNC_DSP (0 << 7)
219 #define RVII_CLKSEL_IVA (1 << 8)
220 #define RVII_SYNC_IVA (0 << 13)
221 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
222 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
224 #define RVII_CLKSEL_GFX (1 << 0)
225 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
227 /*-------------------------------------------------------------------------
228 * 2430 Target modes: Along with each configuration the CPU has several
229 * modes which goes along with them. Modes mainly are the addition of
230 * describe DPLL combinations to go along with a ratio.
231 *-------------------------------------------------------------------------*/
233 /* Hardware governed */
234 #define MX_48M_SRC (0 << 3)
235 #define MX_54M_SRC (0 << 5)
236 #define MX_APLLS_CLIKIN_12 (3 << 23)
237 #define MX_APLLS_CLIKIN_13 (2 << 23)
238 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
241 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
242 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
244 #define M5A_DPLL_MULT_12 (133 << 12)
245 #define M5A_DPLL_DIV_12 (5 << 8)
246 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
247 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
249 #define M5A_DPLL_MULT_13 (61 << 12)
250 #define M5A_DPLL_DIV_13 (2 << 8)
251 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
252 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
254 #define M5A_DPLL_MULT_19 (55 << 12)
255 #define M5A_DPLL_DIV_19 (3 << 8)
256 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
257 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
259 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
260 #define M5B_DPLL_MULT_12 (50 << 12)
261 #define M5B_DPLL_DIV_12 (2 << 8)
262 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
263 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
265 #define M5B_DPLL_MULT_13 (200 << 12)
266 #define M5B_DPLL_DIV_13 (12 << 8)
268 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
269 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
271 #define M5B_DPLL_MULT_19 (125 << 12)
272 #define M5B_DPLL_DIV_19 (31 << 8)
273 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
274 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
277 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
279 #define M4_DPLL_MULT_12 (133 << 12)
280 #define M4_DPLL_DIV_12 (3 << 8)
281 #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
282 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
285 #define M4_DPLL_MULT_13 (399 << 12)
286 #define M4_DPLL_DIV_13 (12 << 8)
287 #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
288 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
291 #define M4_DPLL_MULT_19 (145 << 12)
292 #define M4_DPLL_DIV_19 (6 << 8)
293 #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
294 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
298 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
300 #define M3_DPLL_MULT_12 (55 << 12)
301 #define M3_DPLL_DIV_12 (1 << 8)
302 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
303 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
305 #define M3_DPLL_MULT_13 (76 << 12)
306 #define M3_DPLL_DIV_13 (2 << 8)
307 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
308 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
310 #define M3_DPLL_MULT_19 (17 << 12)
311 #define M3_DPLL_DIV_19 (0 << 8)
312 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
313 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
317 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
319 #define M2_DPLL_MULT_12 (55 << 12)
320 #define M2_DPLL_DIV_12 (1 << 8)
321 #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
322 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
326 * relock time issue */
327 /* Core frequency changed from 330/165 to 329/164 MHz*/
328 #define M2_DPLL_MULT_13 (76 << 12)
329 #define M2_DPLL_DIV_13 (2 << 8)
330 #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
331 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
334 #define M2_DPLL_MULT_19 (17 << 12)
335 #define M2_DPLL_DIV_19 (0 << 8)
336 #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
337 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
341 #define MB_DPLL_MULT (1 << 12)
342 #define MB_DPLL_DIV (0 << 8)
343 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
344 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
346 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
347 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
349 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
350 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
353 * 2430 - chassis (sedna)
354 * 165 (ratio1) same as above #2
356 * 133 (ratio2) same as above #4
357 * 110 (ratio2) same as above #3
362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
363 #define MI_DPLL_MULT_12 (55 << 12)
364 #define MI_DPLL_DIV_12 (1 << 8)
365 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
366 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
370 * 2420 Equivalent - mode registers
371 * PRCM II , target DPLL = 2*300MHz = 600MHz
373 #define MII_DPLL_MULT_12 (50 << 12)
374 #define MII_DPLL_DIV_12 (1 << 8)
375 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
376 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
378 #define MII_DPLL_MULT_13 (300 << 12)
379 #define MII_DPLL_DIV_13 (12 << 8)
380 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
381 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
384 /* PRCM III target DPLL = 2*266 = 532MHz*/
385 #define MIII_DPLL_MULT_12 (133 << 12)
386 #define MIII_DPLL_DIV_12 (5 << 8)
387 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
388 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
390 #define MIII_DPLL_MULT_13 (266 << 12)
391 #define MIII_DPLL_DIV_13 (12 << 8)
392 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
393 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
396 /* PRCM VII (boot bypass) */
397 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
398 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
400 /* High and low operation value */
401 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
402 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
404 /* MPU speed defines */
405 #define S12M 12000000
406 #define S13M 13000000
407 #define S19M 19200000
408 #define S26M 26000000
409 #define S100M 100000000
410 #define S133M 133000000
411 #define S150M 150000000
412 #define S164M 164000000
413 #define S165M 165000000
414 #define S199M 199000000
415 #define S200M 200000000
416 #define S266M 266000000
417 #define S300M 300000000
418 #define S329M 329000000
419 #define S330M 330000000
420 #define S399M 399000000
421 #define S400M 400000000
422 #define S532M 532000000
423 #define S600M 600000000
424 #define S658M 658000000
425 #define S660M 660000000
426 #define S798M 798000000
428 /*-------------------------------------------------------------------------
429 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
430 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
431 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
432 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
434 * Filling in table based on H4 boards and 2430-SDPs variants available.
435 * There are quite a few more rates combinations which could be defined.
437 * When multiple values are defined the start up will try and choose the
438 * fastest one. If a 'fast' value is defined, then automatically, the /2
439 * one should be included as it can be used. Generally having more that
440 * one fast set does not make sense, as static timings need to be changed
441 * to change the set. The exception is the bypass setting which is
442 * availble for low power bypass.
444 * Note: This table needs to be sorted, fastest to slowest.
445 *-------------------------------------------------------------------------*/
446 static struct prcm_config rate_table[] = {
448 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
449 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
450 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
451 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
455 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
456 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
457 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
458 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
461 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
462 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
463 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
464 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
467 /* PRCM III - FAST */
468 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
469 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
470 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
471 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
474 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
475 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
476 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
477 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
481 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
482 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
483 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
484 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
487 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
488 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
489 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
490 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
493 /* PRCM III - SLOW */
494 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
495 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
496 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
497 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
500 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
501 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
502 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
503 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
506 /* PRCM-VII (boot-bypass) */
507 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
508 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
509 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
510 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
513 /* PRCM-VII (boot-bypass) */
514 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
515 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
516 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
517 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
520 /* PRCM #4 - ratio2 (ES2.1) - FAST */
521 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
522 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
523 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
524 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
525 SDRC_RFR_CTRL_133MHz,
528 /* PRCM #2 - ratio1 (ES2) - FAST */
529 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
530 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
531 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
532 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
533 SDRC_RFR_CTRL_165MHz,
536 /* PRCM #5a - ratio1 - FAST */
537 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
538 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
539 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
540 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
541 SDRC_RFR_CTRL_133MHz,
544 /* PRCM #5b - ratio1 - FAST */
545 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
546 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
547 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
548 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
549 SDRC_RFR_CTRL_100MHz,
552 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
553 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
554 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
555 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
556 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
557 SDRC_RFR_CTRL_133MHz,
560 /* PRCM #2 - ratio1 (ES2) - SLOW */
561 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
562 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
563 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
564 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
565 SDRC_RFR_CTRL_165MHz,
568 /* PRCM #5a - ratio1 - SLOW */
569 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
570 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
571 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
572 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
573 SDRC_RFR_CTRL_133MHz,
576 /* PRCM #5b - ratio1 - SLOW*/
577 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
578 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
579 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
580 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
581 SDRC_RFR_CTRL_100MHz,
584 /* PRCM-boot/bypass */
585 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
586 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
587 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
588 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
589 SDRC_RFR_CTRL_BYPASS,
592 /* PRCM-boot/bypass */
593 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
594 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
595 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
596 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
597 SDRC_RFR_CTRL_BYPASS,
600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
603 /*-------------------------------------------------------------------------
606 * NOTE:In many cases here we are assigning a 'default' parent. In many
607 * cases the parent is selectable. The get/set parent calls will also
610 * Many some clocks say always_enabled, but they can be auto idled for
611 * power savings. They will always be available upon clock request.
613 * Several sources are given initial rates which may be wrong, this will
614 * be fixed up in the init func.
616 * Things are broadly separated below by clock domains. It is
617 * noteworthy that most periferals have dependencies on multiple clock
618 * domains. Many get their interface clocks from the L4 domain, but get
619 * functional clocks from fixed sources or other core domain derived
621 *-------------------------------------------------------------------------*/
623 /* Base external input clocks */
624 static struct clk func_32k_ck = {
625 .name = "func_32k_ck",
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
629 .clkdm = { .name = "prm_clkdm" },
630 .recalc = &propagate_rate,
633 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
638 .clkdm = { .name = "prm_clkdm" },
639 .enable = &omap2_enable_osc_ck,
640 .disable = &omap2_disable_osc_ck,
641 .recalc = &omap2_osc_clk_recalc,
644 /* Without modem likely 12MHz, with modem likely 13MHz */
645 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
646 .name = "sys_ck", /* ~ ref_clk also */
648 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
649 ALWAYS_ENABLED | RATE_PROPAGATES,
650 .clkdm = { .name = "prm_clkdm" },
651 .recalc = &omap2_sys_clk_recalc,
654 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
658 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
659 .clkdm = { .name = "prm_clkdm" },
660 .recalc = &propagate_rate,
664 * Analog domain root source clocks
667 /* dpll_ck, is broken out in to special cases through clksel */
668 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
672 static struct dpll_data dpll_dd = {
673 .mult_div1_reg = CM_CLKSEL1,
674 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
675 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
676 .idlest_reg = CM_IDLEST,
677 .idlest_mask = OMAP24XX_ST_CORE_CLK_MASK,
678 .max_multiplier = 1024,
680 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
684 * XXX Cannot add round_rate here yet, as this is still a composite clock,
687 static struct clk dpll_ck = {
689 .parent = &sys_ck, /* Can be func_32k also */
691 .dpll_data = &dpll_dd,
692 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
693 RATE_PROPAGATES | ALWAYS_ENABLED,
694 .clkdm = { .name = "prm_clkdm" },
695 .recalc = &omap2_dpllcore_recalc,
696 .set_rate = &omap2_reprogram_dpllcore,
699 static struct clk apll96_ck = {
704 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
705 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
706 .clkdm = { .name = "prm_clkdm" },
707 .enable_reg = CM_CLKEN,
708 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
709 .enable = &omap2_clk_fixed_enable,
710 .disable = &omap2_clk_fixed_disable,
711 .recalc = &propagate_rate,
714 static struct clk apll54_ck = {
719 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
720 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
721 .clkdm = { .name = "prm_clkdm" },
722 .enable_reg = CM_CLKEN,
723 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
724 .enable = &omap2_clk_fixed_enable,
725 .disable = &omap2_clk_fixed_disable,
726 .recalc = &propagate_rate,
730 * PRCM digital base sources
735 static const struct clksel_rate func_54m_apll54_rates[] = {
736 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
740 static const struct clksel_rate func_54m_alt_rates[] = {
741 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
745 static const struct clksel func_54m_clksel[] = {
746 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
747 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
751 static struct clk func_54m_ck = {
752 .name = "func_54m_ck",
753 .parent = &apll54_ck, /* can also be alt_clk */
755 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
756 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
757 .clkdm = { .name = "cm_clkdm" },
758 .init = &omap2_init_clksel_parent,
759 .clksel_reg = CM_CLKSEL1,
760 .clksel_mask = OMAP24XX_54M_SOURCE,
761 .clksel = func_54m_clksel,
762 .recalc = &omap2_clksel_recalc,
765 static struct clk core_ck = {
767 .parent = &dpll_ck, /* can also be 32k */
768 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
769 ALWAYS_ENABLED | RATE_PROPAGATES,
770 .clkdm = { .name = "cm_clkdm" },
771 .recalc = &followparent_recalc,
775 static const struct clksel_rate func_96m_apll96_rates[] = {
776 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
780 static const struct clksel_rate func_96m_alt_rates[] = {
781 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
785 static const struct clksel func_96m_clksel[] = {
786 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
787 { .parent = &alt_ck, .rates = func_96m_alt_rates },
791 /* The parent of this clock is not selectable on 2420. */
792 static struct clk func_96m_ck = {
793 .name = "func_96m_ck",
794 .parent = &apll96_ck,
796 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
797 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
798 .clkdm = { .name = "cm_clkdm" },
799 .init = &omap2_init_clksel_parent,
800 .clksel_reg = CM_CLKSEL1,
801 .clksel_mask = OMAP2430_96M_SOURCE,
802 .clksel = func_96m_clksel,
803 .recalc = &omap2_clksel_recalc,
804 .round_rate = &omap2_clksel_round_rate,
805 .set_rate = &omap2_clksel_set_rate
810 static const struct clksel_rate func_48m_apll96_rates[] = {
811 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
815 static const struct clksel_rate func_48m_alt_rates[] = {
816 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
820 static const struct clksel func_48m_clksel[] = {
821 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
822 { .parent = &alt_ck, .rates = func_48m_alt_rates },
826 static struct clk func_48m_ck = {
827 .name = "func_48m_ck",
828 .parent = &apll96_ck, /* 96M or Alt */
830 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
831 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
832 .clkdm = { .name = "cm_clkdm" },
833 .init = &omap2_init_clksel_parent,
834 .clksel_reg = CM_CLKSEL1,
835 .clksel_mask = OMAP24XX_48M_SOURCE,
836 .clksel = func_48m_clksel,
837 .recalc = &omap2_clksel_recalc,
838 .round_rate = &omap2_clksel_round_rate,
839 .set_rate = &omap2_clksel_set_rate
842 static struct clk func_12m_ck = {
843 .name = "func_12m_ck",
844 .parent = &func_48m_ck,
846 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
847 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
848 .clkdm = { .name = "cm_clkdm" },
849 .recalc = &omap2_fixed_divisor_recalc,
852 /* Secure timer, only available in secure mode */
853 static struct clk wdt1_osc_ck = {
854 .name = "wdt1_osc_ck",
856 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
857 .clkdm = { .name = "prm_clkdm" },
858 .recalc = &followparent_recalc,
862 * The common_clkout* clksel_rate structs are common to
863 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
864 * sys_clkout2_* are 2420-only, so the
865 * clksel_rate flags fields are inaccurate for those clocks. This is
866 * harmless since access to those clocks are gated by the struct clk
867 * flags fields, which mark them as 2420-only.
869 static const struct clksel_rate common_clkout_src_core_rates[] = {
870 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
874 static const struct clksel_rate common_clkout_src_sys_rates[] = {
875 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
879 static const struct clksel_rate common_clkout_src_96m_rates[] = {
880 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
884 static const struct clksel_rate common_clkout_src_54m_rates[] = {
885 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
889 static const struct clksel common_clkout_src_clksel[] = {
890 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
891 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
892 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
893 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
897 static struct clk sys_clkout_src = {
898 .name = "sys_clkout_src",
899 .parent = &func_54m_ck,
900 .prcm_mod = OMAP24XX_GR_MOD,
901 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
903 .clkdm = { .name = "prm_clkdm" },
904 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
905 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
906 .init = &omap2_init_clksel_parent,
907 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
908 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
909 .clksel = common_clkout_src_clksel,
910 .recalc = &omap2_clksel_recalc,
911 .round_rate = &omap2_clksel_round_rate,
912 .set_rate = &omap2_clksel_set_rate
915 static const struct clksel_rate common_clkout_rates[] = {
916 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
917 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
918 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
919 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
920 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
924 static const struct clksel sys_clkout_clksel[] = {
925 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
929 static struct clk sys_clkout = {
930 .name = "sys_clkout",
931 .parent = &sys_clkout_src,
932 .prcm_mod = OMAP24XX_GR_MOD,
933 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
934 PARENT_CONTROLS_CLOCK,
935 .clkdm = { .name = "prm_clkdm" },
936 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
937 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
938 .clksel = sys_clkout_clksel,
939 .recalc = &omap2_clksel_recalc,
940 .round_rate = &omap2_clksel_round_rate,
941 .set_rate = &omap2_clksel_set_rate
944 /* In 2430, new in 2420 ES2 */
945 static struct clk sys_clkout2_src = {
946 .name = "sys_clkout2_src",
947 .parent = &func_54m_ck,
948 .prcm_mod = OMAP24XX_GR_MOD,
949 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
950 .clkdm = { .name = "cm_clkdm" },
951 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
952 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
953 .init = &omap2_init_clksel_parent,
954 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
955 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
956 .clksel = common_clkout_src_clksel,
957 .recalc = &omap2_clksel_recalc,
958 .round_rate = &omap2_clksel_round_rate,
959 .set_rate = &omap2_clksel_set_rate
962 static const struct clksel sys_clkout2_clksel[] = {
963 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
967 /* In 2430, new in 2420 ES2 */
968 static struct clk sys_clkout2 = {
969 .name = "sys_clkout2",
970 .parent = &sys_clkout2_src,
971 .prcm_mod = OMAP24XX_GR_MOD,
972 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
973 .clkdm = { .name = "cm_clkdm" },
974 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
975 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
976 .clksel = sys_clkout2_clksel,
977 .recalc = &omap2_clksel_recalc,
978 .round_rate = &omap2_clksel_round_rate,
979 .set_rate = &omap2_clksel_set_rate
982 static struct clk emul_ck = {
984 .parent = &func_54m_ck,
985 .prcm_mod = OMAP24XX_GR_MOD,
986 .flags = CLOCK_IN_OMAP242X,
987 .clkdm = { .name = "cm_clkdm" },
988 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET,
989 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
990 .recalc = &followparent_recalc,
998 * INT_M_FCLK, INT_M_I_CLK
1000 * - Individual clocks are hardware managed.
1001 * - Base divider comes from: CM_CLKSEL_MPU
1004 static const struct clksel_rate mpu_core_rates[] = {
1005 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1006 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1007 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1008 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1009 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1013 static const struct clksel mpu_clksel[] = {
1014 { .parent = &core_ck, .rates = mpu_core_rates },
1018 static struct clk mpu_ck = { /* Control cpu */
1021 .prcm_mod = MPU_MOD,
1022 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1023 ALWAYS_ENABLED | DELAYED_APP |
1024 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1025 .clkdm = { .name = "mpu_clkdm" },
1026 .init = &omap2_init_clksel_parent,
1027 .clksel_reg = CM_CLKSEL,
1028 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
1029 .clksel = mpu_clksel,
1030 .recalc = &omap2_clksel_recalc,
1031 .round_rate = &omap2_clksel_round_rate,
1032 .set_rate = &omap2_clksel_set_rate
1036 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1038 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1039 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1041 * Won't be too specific here. The core clock comes into this block
1042 * it is divided then tee'ed. One branch goes directly to xyz enable
1043 * controls. The other branch gets further divided by 2 then possibly
1044 * routed into a synchronizer and out of clocks abc.
1046 static const struct clksel_rate dsp_fck_core_rates[] = {
1047 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1048 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1049 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1050 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1051 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1052 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1053 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1057 static const struct clksel dsp_fck_clksel[] = {
1058 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1062 static struct clk dsp_fck = {
1065 .prcm_mod = OMAP24XX_DSP_MOD,
1066 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1067 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1068 .clkdm = { .name = "dsp_clkdm" },
1069 .enable_reg = CM_FCLKEN,
1070 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1071 .clksel_reg = CM_CLKSEL,
1072 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1073 .clksel = dsp_fck_clksel,
1074 .recalc = &omap2_clksel_recalc,
1075 .round_rate = &omap2_clksel_round_rate,
1076 .set_rate = &omap2_clksel_set_rate
1079 /* DSP interface clock */
1080 static const struct clksel_rate dsp_irate_ick_rates[] = {
1081 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1082 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1083 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1087 static const struct clksel dsp_irate_ick_clksel[] = {
1088 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1092 /* This clock does not exist as such in the TRM. */
1093 static struct clk dsp_irate_ick = {
1094 .name = "dsp_irate_ick",
1096 .prcm_mod = OMAP24XX_DSP_MOD,
1097 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1098 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1099 .clkdm = { .name = "dsp_clkdm" },
1100 .clksel_reg = CM_CLKSEL,
1101 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1102 .clksel = dsp_irate_ick_clksel,
1103 .recalc = &omap2_clksel_recalc,
1104 .round_rate = &omap2_clksel_round_rate,
1105 .set_rate = &omap2_clksel_set_rate
1109 static struct clk dsp_ick = {
1110 .name = "dsp_ick", /* apparently ipi and isp */
1111 .parent = &dsp_irate_ick,
1112 .prcm_mod = OMAP24XX_DSP_MOD,
1113 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1114 .clkdm = { .name = "dsp_clkdm" },
1115 .enable_reg = CM_ICLKEN,
1116 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1119 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1120 static struct clk iva2_1_ick = {
1121 .name = "iva2_1_ick",
1122 .parent = &dsp_irate_ick,
1123 .prcm_mod = OMAP24XX_DSP_MOD,
1124 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1125 .clkdm = { .name = "dsp_clkdm" },
1126 .enable_reg = CM_FCLKEN,
1127 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1131 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1132 * the C54x, but which is contained in the DSP powerdomain. Does not
1133 * exist on later OMAPs.
1135 static struct clk iva1_ifck = {
1136 .name = "iva1_ifck",
1138 .prcm_mod = OMAP24XX_DSP_MOD,
1139 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1140 RATE_PROPAGATES | DELAYED_APP,
1141 .clkdm = { .name = "iva1_clkdm" },
1142 .enable_reg = CM_FCLKEN,
1143 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1144 .clksel_reg = CM_CLKSEL,
1145 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1146 .clksel = dsp_fck_clksel,
1147 .recalc = &omap2_clksel_recalc,
1148 .round_rate = &omap2_clksel_round_rate,
1149 .set_rate = &omap2_clksel_set_rate
1152 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1153 static struct clk iva1_mpu_int_ifck = {
1154 .name = "iva1_mpu_int_ifck",
1155 .parent = &iva1_ifck,
1156 .prcm_mod = OMAP24XX_DSP_MOD,
1157 .flags = CLOCK_IN_OMAP242X,
1158 .clkdm = { .name = "iva1_clkdm" },
1159 .enable_reg = CM_FCLKEN,
1160 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1162 .recalc = &omap2_fixed_divisor_recalc,
1167 * L3 clocks are used for both interface and functional clocks to
1168 * multiple entities. Some of these clocks are completely managed
1169 * by hardware, and some others allow software control. Hardware
1170 * managed ones general are based on directly CLK_REQ signals and
1171 * various auto idle settings. The functional spec sets many of these
1172 * as 'tie-high' for their enables.
1175 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1180 * GPMC memories and SDRC have timing and clock sensitive registers which
1181 * may very well need notification when the clock changes. Currently for low
1182 * operating points, these are taken care of in sleep.S.
1184 static const struct clksel_rate core_l3_core_rates[] = {
1185 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1186 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1187 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1188 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1189 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1190 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1191 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1195 static const struct clksel core_l3_clksel[] = {
1196 { .parent = &core_ck, .rates = core_l3_core_rates },
1200 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1201 .name = "core_l3_ck",
1203 .prcm_mod = CORE_MOD,
1204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1205 ALWAYS_ENABLED | DELAYED_APP |
1206 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1207 .clkdm = { .name = "core_l3_clkdm" },
1208 .clksel_reg = CM_CLKSEL1,
1209 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1210 .clksel = core_l3_clksel,
1211 .recalc = &omap2_clksel_recalc,
1212 .round_rate = &omap2_clksel_round_rate,
1213 .set_rate = &omap2_clksel_set_rate
1217 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1218 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1219 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1220 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1224 static const struct clksel usb_l4_ick_clksel[] = {
1225 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1229 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1230 static struct clk usb_l4_ick = { /* FS-USB interface clock */
1231 .name = "usb_l4_ick",
1232 .parent = &core_l3_ck,
1233 .prcm_mod = CORE_MOD,
1234 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1235 DELAYED_APP | CONFIG_PARTICIPANT,
1236 .clkdm = { .name = "core_l4_clkdm" },
1237 .enable_reg = CM_ICLKEN2,
1238 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1239 .clksel_reg = CM_CLKSEL1,
1240 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1241 .clksel = usb_l4_ick_clksel,
1242 .recalc = &omap2_clksel_recalc,
1243 .round_rate = &omap2_clksel_round_rate,
1244 .set_rate = &omap2_clksel_set_rate
1248 * L4 clock management domain
1250 * This domain contains lots of interface clocks from the L4 interface, some
1251 * functional clocks. Fixed APLL functional source clocks are managed in
1254 static const struct clksel_rate l4_core_l3_rates[] = {
1255 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1256 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1260 static const struct clksel l4_clksel[] = {
1261 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1265 static struct clk l4_ck = { /* used both as an ick and fck */
1267 .parent = &core_l3_ck,
1268 .prcm_mod = CORE_MOD,
1269 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1270 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1271 .clkdm = { .name = "core_l4_clkdm" },
1272 .clksel_reg = CM_CLKSEL1,
1273 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1274 .clksel = l4_clksel,
1275 .recalc = &omap2_clksel_recalc,
1276 .round_rate = &omap2_clksel_round_rate,
1277 .set_rate = &omap2_clksel_set_rate
1281 * SSI is in L3 management domain, its direct parent is core not l3,
1282 * many core power domain entities are grouped into the L3 clock
1284 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1286 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1288 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1289 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1290 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1291 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1292 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1293 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1294 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1295 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1299 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1300 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1304 static struct clk ssi_ssr_sst_fck = {
1307 .prcm_mod = CORE_MOD,
1308 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1310 .clkdm = { .name = "core_l3_clkdm" },
1311 .enable_reg = OMAP24XX_CM_FCLKEN2,
1312 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1313 .clksel_reg = CM_CLKSEL1,
1314 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1315 .clksel = ssi_ssr_sst_fck_clksel,
1316 .recalc = &omap2_clksel_recalc,
1317 .round_rate = &omap2_clksel_round_rate,
1318 .set_rate = &omap2_clksel_set_rate
1322 * Presumably this is the same as SSI_ICLK.
1323 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1325 static struct clk ssi_l4_ick = {
1326 .name = "ssi_l4_ick",
1328 .prcm_mod = CORE_MOD,
1329 .clkdm = { .name = "core_l4_clkdm" },
1330 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1331 .enable_reg = CM_ICLKEN2,
1332 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1333 .recalc = &followparent_recalc,
1340 * GFX_FCLK, GFX_ICLK
1341 * GFX_CG1(2d), GFX_CG2(3d)
1343 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1344 * The 2d and 3d clocks run at a hardware determined
1345 * divided value of fclk.
1348 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1350 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1351 static const struct clksel gfx_fck_clksel[] = {
1352 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1356 static struct clk gfx_3d_fck = {
1357 .name = "gfx_3d_fck",
1358 .parent = &core_l3_ck,
1359 .prcm_mod = GFX_MOD,
1360 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1361 .clkdm = { .name = "gfx_clkdm" },
1362 .enable_reg = CM_FCLKEN,
1363 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1364 .clksel_reg = CM_CLKSEL,
1365 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1366 .clksel = gfx_fck_clksel,
1367 .recalc = &omap2_clksel_recalc,
1368 .round_rate = &omap2_clksel_round_rate,
1369 .set_rate = &omap2_clksel_set_rate
1372 static struct clk gfx_2d_fck = {
1373 .name = "gfx_2d_fck",
1374 .parent = &core_l3_ck,
1375 .prcm_mod = GFX_MOD,
1376 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1377 .clkdm = { .name = "gfx_clkdm" },
1378 .enable_reg = CM_FCLKEN,
1379 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1380 .clksel_reg = CM_CLKSEL,
1381 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1382 .clksel = gfx_fck_clksel,
1383 .recalc = &omap2_clksel_recalc,
1384 .round_rate = &omap2_clksel_round_rate,
1385 .set_rate = &omap2_clksel_set_rate
1388 static struct clk gfx_ick = {
1389 .name = "gfx_ick", /* From l3 */
1390 .parent = &core_l3_ck,
1391 .prcm_mod = GFX_MOD,
1392 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1393 .clkdm = { .name = "gfx_clkdm" },
1394 .enable_reg = CM_ICLKEN,
1395 .enable_bit = OMAP_EN_GFX_SHIFT,
1396 .recalc = &followparent_recalc,
1400 * Modem clock domain (2430)
1404 * These clocks are usable in chassis mode only.
1406 static const struct clksel_rate mdm_ick_core_rates[] = {
1407 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1408 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1409 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1410 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1414 static const struct clksel mdm_ick_clksel[] = {
1415 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1419 static struct clk mdm_ick = { /* used both as a ick and fck */
1422 .prcm_mod = OMAP2430_MDM_MOD,
1423 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1424 .clkdm = { .name = "mdm_clkdm" },
1425 .enable_reg = CM_ICLKEN,
1426 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1427 .clksel_reg = CM_CLKSEL,
1428 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1429 .clksel = mdm_ick_clksel,
1430 .recalc = &omap2_clksel_recalc,
1431 .round_rate = &omap2_clksel_round_rate,
1432 .set_rate = &omap2_clksel_set_rate
1435 static struct clk mdm_osc_ck = {
1436 .name = "mdm_osc_ck",
1438 .prcm_mod = OMAP2430_MDM_MOD,
1439 .flags = CLOCK_IN_OMAP243X,
1440 .clkdm = { .name = "mdm_clkdm" },
1441 .enable_reg = CM_FCLKEN,
1442 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1443 .recalc = &followparent_recalc,
1449 * DSS_L4_ICLK, DSS_L3_ICLK,
1450 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1452 * DSS is both initiator and target.
1454 /* XXX Add RATE_NOT_VALIDATED */
1456 static const struct clksel_rate dss1_fck_sys_rates[] = {
1457 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1461 static const struct clksel_rate dss1_fck_core_rates[] = {
1462 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1463 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1464 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1465 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1466 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1467 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1468 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1469 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1470 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1471 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1475 static const struct clksel dss1_fck_clksel[] = {
1476 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1477 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1481 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1483 .parent = &l4_ck, /* really both l3 and l4 */
1484 .prcm_mod = CORE_MOD,
1485 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1486 .clkdm = { .name = "dss_clkdm" },
1487 .enable_reg = CM_ICLKEN1,
1488 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1489 .recalc = &followparent_recalc,
1492 static struct clk dss1_fck = {
1494 .parent = &core_ck, /* Core or sys */
1495 .prcm_mod = CORE_MOD,
1496 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1498 .clkdm = { .name = "dss_clkdm" },
1499 .enable_reg = CM_FCLKEN1,
1500 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1501 .init = &omap2_init_clksel_parent,
1502 .clksel_reg = CM_CLKSEL1,
1503 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1504 .clksel = dss1_fck_clksel,
1505 .recalc = &omap2_clksel_recalc,
1506 .round_rate = &omap2_clksel_round_rate,
1507 .set_rate = &omap2_clksel_set_rate
1510 static const struct clksel_rate dss2_fck_sys_rates[] = {
1511 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1515 static const struct clksel_rate dss2_fck_48m_rates[] = {
1516 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1520 static const struct clksel dss2_fck_clksel[] = {
1521 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1522 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1526 static struct clk dss2_fck = { /* Alt clk used in power management */
1528 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1529 .prcm_mod = CORE_MOD,
1530 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1532 .clkdm = { .name = "dss_clkdm" },
1533 .enable_reg = CM_FCLKEN1,
1534 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1535 .init = &omap2_init_clksel_parent,
1536 .clksel_reg = CM_CLKSEL1,
1537 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1538 .clksel = dss2_fck_clksel,
1539 .recalc = &followparent_recalc,
1542 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1543 .name = "dss_54m_fck", /* 54m tv clk */
1544 .parent = &func_54m_ck,
1545 .prcm_mod = CORE_MOD,
1546 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1547 .clkdm = { .name = "dss_clkdm" },
1548 .enable_reg = CM_FCLKEN1,
1549 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1550 .recalc = &followparent_recalc,
1554 * CORE power domain ICLK & FCLK defines.
1555 * Many of the these can have more than one possible parent. Entries
1556 * here will likely have an L4 interface parent, and may have multiple
1557 * functional clock parents.
1559 static const struct clksel_rate gpt_alt_rates[] = {
1560 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1564 static const struct clksel omap24xx_gpt_clksel[] = {
1565 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1566 { .parent = &sys_ck, .rates = gpt_sys_rates },
1567 { .parent = &alt_ck, .rates = gpt_alt_rates },
1571 static struct clk gpt1_ick = {
1574 .prcm_mod = WKUP_MOD,
1575 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1576 .clkdm = { .name = "core_l4_clkdm" },
1577 .enable_reg = CM_ICLKEN,
1578 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1579 .recalc = &followparent_recalc,
1582 static struct clk gpt1_fck = {
1584 .parent = &func_32k_ck,
1585 .prcm_mod = WKUP_MOD,
1586 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1587 .clkdm = { .name = "core_l4_clkdm" },
1588 .enable_reg = CM_FCLKEN,
1589 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1590 .init = &omap2_init_clksel_parent,
1591 .clksel_reg = CM_CLKSEL1,
1592 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1593 .clksel = omap24xx_gpt_clksel,
1594 .recalc = &omap2_clksel_recalc,
1595 .round_rate = &omap2_clksel_round_rate,
1596 .set_rate = &omap2_clksel_set_rate
1599 static struct clk gpt2_ick = {
1602 .prcm_mod = CORE_MOD,
1603 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1604 .clkdm = { .name = "core_l4_clkdm" },
1605 .enable_reg = CM_ICLKEN1,
1606 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1607 .recalc = &followparent_recalc,
1610 static struct clk gpt2_fck = {
1612 .parent = &func_32k_ck,
1613 .prcm_mod = CORE_MOD,
1614 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1615 .clkdm = { .name = "core_l4_clkdm" },
1616 .enable_reg = CM_FCLKEN1,
1617 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1618 .init = &omap2_init_clksel_parent,
1619 .clksel_reg = CM_CLKSEL2,
1620 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1621 .clksel = omap24xx_gpt_clksel,
1622 .recalc = &omap2_clksel_recalc,
1625 static struct clk gpt3_ick = {
1628 .prcm_mod = CORE_MOD,
1629 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1630 .clkdm = { .name = "core_l4_clkdm" },
1631 .enable_reg = CM_ICLKEN1,
1632 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1633 .recalc = &followparent_recalc,
1636 static struct clk gpt3_fck = {
1638 .parent = &func_32k_ck,
1639 .prcm_mod = CORE_MOD,
1640 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1641 .clkdm = { .name = "core_l4_clkdm" },
1642 .enable_reg = CM_FCLKEN1,
1643 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1644 .init = &omap2_init_clksel_parent,
1645 .clksel_reg = CM_CLKSEL2,
1646 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1647 .clksel = omap24xx_gpt_clksel,
1648 .recalc = &omap2_clksel_recalc,
1651 static struct clk gpt4_ick = {
1654 .prcm_mod = CORE_MOD,
1655 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1656 .clkdm = { .name = "core_l4_clkdm" },
1657 .enable_reg = CM_ICLKEN1,
1658 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1659 .recalc = &followparent_recalc,
1662 static struct clk gpt4_fck = {
1664 .parent = &func_32k_ck,
1665 .prcm_mod = CORE_MOD,
1666 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1667 .clkdm = { .name = "core_l4_clkdm" },
1668 .enable_reg = CM_FCLKEN1,
1669 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1670 .init = &omap2_init_clksel_parent,
1671 .clksel_reg = CM_CLKSEL2,
1672 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1673 .clksel = omap24xx_gpt_clksel,
1674 .recalc = &omap2_clksel_recalc,
1677 static struct clk gpt5_ick = {
1680 .prcm_mod = CORE_MOD,
1681 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1682 .clkdm = { .name = "core_l4_clkdm" },
1683 .enable_reg = CM_ICLKEN1,
1684 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1685 .recalc = &followparent_recalc,
1688 static struct clk gpt5_fck = {
1690 .parent = &func_32k_ck,
1691 .prcm_mod = CORE_MOD,
1692 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1693 .clkdm = { .name = "core_l4_clkdm" },
1694 .enable_reg = CM_FCLKEN1,
1695 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1696 .init = &omap2_init_clksel_parent,
1697 .clksel_reg = CM_CLKSEL2,
1698 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1699 .clksel = omap24xx_gpt_clksel,
1700 .recalc = &omap2_clksel_recalc,
1703 static struct clk gpt6_ick = {
1706 .prcm_mod = CORE_MOD,
1707 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1708 .clkdm = { .name = "core_l4_clkdm" },
1709 .enable_reg = CM_ICLKEN1,
1710 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1711 .recalc = &followparent_recalc,
1714 static struct clk gpt6_fck = {
1716 .parent = &func_32k_ck,
1717 .prcm_mod = CORE_MOD,
1718 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1719 .clkdm = { .name = "core_l4_clkdm" },
1720 .enable_reg = CM_FCLKEN1,
1721 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1722 .init = &omap2_init_clksel_parent,
1723 .clksel_reg = CM_CLKSEL2,
1724 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1725 .clksel = omap24xx_gpt_clksel,
1726 .recalc = &omap2_clksel_recalc,
1729 static struct clk gpt7_ick = {
1732 .prcm_mod = CORE_MOD,
1733 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734 .clkdm = { .name = "core_l4_clkdm" },
1735 .enable_reg = CM_ICLKEN1,
1736 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1737 .recalc = &followparent_recalc,
1740 static struct clk gpt7_fck = {
1742 .parent = &func_32k_ck,
1743 .prcm_mod = CORE_MOD,
1744 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1745 .clkdm = { .name = "core_l4_clkdm" },
1746 .enable_reg = CM_FCLKEN1,
1747 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1748 .init = &omap2_init_clksel_parent,
1749 .clksel_reg = CM_CLKSEL2,
1750 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1751 .clksel = omap24xx_gpt_clksel,
1752 .recalc = &omap2_clksel_recalc,
1755 static struct clk gpt8_ick = {
1758 .prcm_mod = CORE_MOD,
1759 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1760 .clkdm = { .name = "core_l4_clkdm" },
1761 .enable_reg = CM_ICLKEN1,
1762 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1763 .recalc = &followparent_recalc,
1766 static struct clk gpt8_fck = {
1768 .parent = &func_32k_ck,
1769 .prcm_mod = CORE_MOD,
1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1771 .clkdm = { .name = "core_l4_clkdm" },
1772 .enable_reg = CM_FCLKEN1,
1773 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1774 .init = &omap2_init_clksel_parent,
1775 .clksel_reg = CM_CLKSEL2,
1776 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1777 .clksel = omap24xx_gpt_clksel,
1778 .recalc = &omap2_clksel_recalc,
1781 static struct clk gpt9_ick = {
1784 .prcm_mod = CORE_MOD,
1785 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1786 .clkdm = { .name = "core_l4_clkdm" },
1787 .enable_reg = CM_ICLKEN1,
1788 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1789 .recalc = &followparent_recalc,
1792 static struct clk gpt9_fck = {
1794 .parent = &func_32k_ck,
1795 .prcm_mod = CORE_MOD,
1796 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1797 .clkdm = { .name = "core_l4_clkdm" },
1798 .enable_reg = CM_FCLKEN1,
1799 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1800 .init = &omap2_init_clksel_parent,
1801 .clksel_reg = CM_CLKSEL2,
1802 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1803 .clksel = omap24xx_gpt_clksel,
1804 .recalc = &omap2_clksel_recalc,
1807 static struct clk gpt10_ick = {
1808 .name = "gpt10_ick",
1810 .prcm_mod = CORE_MOD,
1811 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1812 .clkdm = { .name = "core_l4_clkdm" },
1813 .enable_reg = CM_ICLKEN1,
1814 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1815 .recalc = &followparent_recalc,
1818 static struct clk gpt10_fck = {
1819 .name = "gpt10_fck",
1820 .parent = &func_32k_ck,
1821 .prcm_mod = CORE_MOD,
1822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1823 .clkdm = { .name = "core_l4_clkdm" },
1824 .enable_reg = CM_FCLKEN1,
1825 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1826 .init = &omap2_init_clksel_parent,
1827 .clksel_reg = CM_CLKSEL2,
1828 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1829 .clksel = omap24xx_gpt_clksel,
1830 .recalc = &omap2_clksel_recalc,
1833 static struct clk gpt11_ick = {
1834 .name = "gpt11_ick",
1836 .prcm_mod = CORE_MOD,
1837 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1838 .clkdm = { .name = "core_l4_clkdm" },
1839 .enable_reg = CM_ICLKEN1,
1840 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1841 .recalc = &followparent_recalc,
1844 static struct clk gpt11_fck = {
1845 .name = "gpt11_fck",
1846 .parent = &func_32k_ck,
1847 .prcm_mod = CORE_MOD,
1848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1849 .clkdm = { .name = "core_l4_clkdm" },
1850 .enable_reg = CM_FCLKEN1,
1851 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1852 .init = &omap2_init_clksel_parent,
1853 .clksel_reg = CM_CLKSEL2,
1854 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1855 .clksel = omap24xx_gpt_clksel,
1856 .recalc = &omap2_clksel_recalc,
1859 static struct clk gpt12_ick = {
1860 .name = "gpt12_ick",
1862 .prcm_mod = CORE_MOD,
1863 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1864 .clkdm = { .name = "core_l4_clkdm" },
1865 .enable_reg = CM_ICLKEN1,
1866 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1867 .recalc = &followparent_recalc,
1870 static struct clk gpt12_fck = {
1871 .name = "gpt12_fck",
1872 .parent = &func_32k_ck,
1873 .prcm_mod = CORE_MOD,
1874 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1875 .clkdm = { .name = "core_l4_clkdm" },
1876 .enable_reg = CM_FCLKEN1,
1877 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1878 .init = &omap2_init_clksel_parent,
1879 .clksel_reg = CM_CLKSEL2,
1880 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1881 .clksel = omap24xx_gpt_clksel,
1882 .recalc = &omap2_clksel_recalc,
1885 static struct clk mcbsp1_ick = {
1886 .name = "mcbsp_ick",
1889 .prcm_mod = CORE_MOD,
1890 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1891 .clkdm = { .name = "core_l4_clkdm" },
1892 .enable_reg = CM_ICLKEN1,
1893 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1894 .recalc = &followparent_recalc,
1897 static struct clk mcbsp1_fck = {
1898 .name = "mcbsp_fck",
1900 .parent = &func_96m_ck,
1901 .prcm_mod = CORE_MOD,
1902 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1903 .clkdm = { .name = "core_l4_clkdm" },
1904 .enable_reg = CM_FCLKEN1,
1905 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1906 .recalc = &followparent_recalc,
1909 static struct clk mcbsp2_ick = {
1910 .name = "mcbsp_ick",
1913 .prcm_mod = CORE_MOD,
1914 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1915 .clkdm = { .name = "core_l4_clkdm" },
1916 .enable_reg = CM_ICLKEN1,
1917 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1918 .recalc = &followparent_recalc,
1921 static struct clk mcbsp2_fck = {
1922 .name = "mcbsp_fck",
1924 .parent = &func_96m_ck,
1925 .prcm_mod = CORE_MOD,
1926 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1927 .clkdm = { .name = "core_l4_clkdm" },
1928 .enable_reg = CM_FCLKEN1,
1929 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1930 .recalc = &followparent_recalc,
1933 static struct clk mcbsp3_ick = {
1934 .name = "mcbsp_ick",
1937 .prcm_mod = CORE_MOD,
1938 .flags = CLOCK_IN_OMAP243X,
1939 .clkdm = { .name = "core_l4_clkdm" },
1940 .enable_reg = CM_ICLKEN2,
1941 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1942 .recalc = &followparent_recalc,
1945 static struct clk mcbsp3_fck = {
1946 .name = "mcbsp_fck",
1948 .parent = &func_96m_ck,
1949 .prcm_mod = CORE_MOD,
1950 .flags = CLOCK_IN_OMAP243X,
1951 .clkdm = { .name = "core_l4_clkdm" },
1952 .enable_reg = OMAP24XX_CM_FCLKEN2,
1953 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1954 .recalc = &followparent_recalc,
1957 static struct clk mcbsp4_ick = {
1958 .name = "mcbsp_ick",
1961 .prcm_mod = CORE_MOD,
1962 .flags = CLOCK_IN_OMAP243X,
1963 .clkdm = { .name = "core_l4_clkdm" },
1964 .enable_reg = CM_ICLKEN2,
1965 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1966 .recalc = &followparent_recalc,
1969 static struct clk mcbsp4_fck = {
1970 .name = "mcbsp_fck",
1972 .parent = &func_96m_ck,
1973 .prcm_mod = CORE_MOD,
1974 .flags = CLOCK_IN_OMAP243X,
1975 .clkdm = { .name = "core_l4_clkdm" },
1976 .enable_reg = OMAP24XX_CM_FCLKEN2,
1977 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1978 .recalc = &followparent_recalc,
1981 static struct clk mcbsp5_ick = {
1982 .name = "mcbsp_ick",
1985 .prcm_mod = CORE_MOD,
1986 .flags = CLOCK_IN_OMAP243X,
1987 .clkdm = { .name = "core_l4_clkdm" },
1988 .enable_reg = CM_ICLKEN2,
1989 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1990 .recalc = &followparent_recalc,
1993 static struct clk mcbsp5_fck = {
1994 .name = "mcbsp_fck",
1996 .parent = &func_96m_ck,
1997 .prcm_mod = CORE_MOD,
1998 .flags = CLOCK_IN_OMAP243X,
1999 .clkdm = { .name = "core_l4_clkdm" },
2000 .enable_reg = OMAP24XX_CM_FCLKEN2,
2001 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
2002 .recalc = &followparent_recalc,
2005 static struct clk mcspi1_ick = {
2006 .name = "mcspi_ick",
2009 .prcm_mod = CORE_MOD,
2010 .clkdm = { .name = "core_l4_clkdm" },
2011 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2012 .enable_reg = CM_ICLKEN1,
2013 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2014 .recalc = &followparent_recalc,
2017 static struct clk mcspi1_fck = {
2018 .name = "mcspi_fck",
2020 .parent = &func_48m_ck,
2021 .prcm_mod = CORE_MOD,
2022 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2023 .clkdm = { .name = "core_l4_clkdm" },
2024 .enable_reg = CM_FCLKEN1,
2025 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2026 .recalc = &followparent_recalc,
2029 static struct clk mcspi2_ick = {
2030 .name = "mcspi_ick",
2033 .prcm_mod = CORE_MOD,
2034 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2035 .clkdm = { .name = "core_l4_clkdm" },
2036 .enable_reg = CM_ICLKEN1,
2037 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2038 .recalc = &followparent_recalc,
2041 static struct clk mcspi2_fck = {
2042 .name = "mcspi_fck",
2044 .parent = &func_48m_ck,
2045 .prcm_mod = CORE_MOD,
2046 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2047 .clkdm = { .name = "core_l4_clkdm" },
2048 .enable_reg = CM_FCLKEN1,
2049 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2050 .recalc = &followparent_recalc,
2053 static struct clk mcspi3_ick = {
2054 .name = "mcspi_ick",
2057 .prcm_mod = CORE_MOD,
2058 .flags = CLOCK_IN_OMAP243X,
2059 .clkdm = { .name = "core_l4_clkdm" },
2060 .enable_reg = CM_ICLKEN2,
2061 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
2062 .recalc = &followparent_recalc,
2065 static struct clk mcspi3_fck = {
2066 .name = "mcspi_fck",
2068 .parent = &func_48m_ck,
2069 .prcm_mod = CORE_MOD,
2070 .flags = CLOCK_IN_OMAP243X,
2071 .clkdm = { .name = "core_l4_clkdm" },
2072 .enable_reg = OMAP24XX_CM_FCLKEN2,
2073 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
2074 .recalc = &followparent_recalc,
2077 static struct clk uart1_ick = {
2078 .name = "uart1_ick",
2080 .prcm_mod = CORE_MOD,
2081 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2082 .clkdm = { .name = "core_l4_clkdm" },
2083 .enable_reg = CM_ICLKEN1,
2084 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2085 .recalc = &followparent_recalc,
2088 static struct clk uart1_fck = {
2089 .name = "uart1_fck",
2090 .parent = &func_48m_ck,
2091 .prcm_mod = CORE_MOD,
2092 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2093 .clkdm = { .name = "core_l4_clkdm" },
2094 .enable_reg = CM_FCLKEN1,
2095 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2096 .recalc = &followparent_recalc,
2099 static struct clk uart2_ick = {
2100 .name = "uart2_ick",
2102 .prcm_mod = CORE_MOD,
2103 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2104 .clkdm = { .name = "core_l4_clkdm" },
2105 .enable_reg = CM_ICLKEN1,
2106 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2107 .recalc = &followparent_recalc,
2110 static struct clk uart2_fck = {
2111 .name = "uart2_fck",
2112 .parent = &func_48m_ck,
2113 .prcm_mod = CORE_MOD,
2114 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2115 .clkdm = { .name = "core_l4_clkdm" },
2116 .enable_reg = CM_FCLKEN1,
2117 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2118 .recalc = &followparent_recalc,
2121 static struct clk uart3_ick = {
2122 .name = "uart3_ick",
2124 .prcm_mod = CORE_MOD,
2125 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2126 .clkdm = { .name = "core_l4_clkdm" },
2127 .enable_reg = CM_ICLKEN2,
2128 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2129 .recalc = &followparent_recalc,
2132 static struct clk uart3_fck = {
2133 .name = "uart3_fck",
2134 .parent = &func_48m_ck,
2135 .prcm_mod = CORE_MOD,
2136 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2137 .clkdm = { .name = "core_l4_clkdm" },
2138 .enable_reg = OMAP24XX_CM_FCLKEN2,
2139 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2140 .recalc = &followparent_recalc,
2143 static struct clk gpios_ick = {
2144 .name = "gpios_ick",
2146 .prcm_mod = WKUP_MOD,
2147 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2148 .clkdm = { .name = "core_l4_clkdm" },
2149 .enable_reg = CM_ICLKEN,
2150 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2151 .recalc = &followparent_recalc,
2154 static struct clk gpios_fck = {
2155 .name = "gpios_fck",
2156 .parent = &func_32k_ck,
2157 .prcm_mod = WKUP_MOD,
2158 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2159 .clkdm = { .name = "prm_clkdm" },
2160 .enable_reg = CM_FCLKEN,
2161 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2162 .recalc = &followparent_recalc,
2165 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2166 static struct clk mpu_wdt_ick = {
2167 .name = "mpu_wdt_ick",
2169 .prcm_mod = WKUP_MOD,
2170 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2171 .clkdm = { .name = "prm_clkdm" },
2172 .enable_reg = CM_ICLKEN,
2173 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2174 .recalc = &followparent_recalc,
2178 static struct clk mpu_wdt_fck = {
2179 .name = "mpu_wdt_fck",
2180 .parent = &func_32k_ck,
2181 .prcm_mod = WKUP_MOD,
2182 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2183 .clkdm = { .name = "prm_clkdm" },
2184 .enable_reg = CM_FCLKEN,
2185 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2186 .recalc = &followparent_recalc,
2189 static struct clk sync_32k_ick = {
2190 .name = "sync_32k_ick",
2192 .prcm_mod = WKUP_MOD,
2193 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2195 .clkdm = { .name = "core_l4_clkdm" },
2196 .enable_reg = CM_ICLKEN,
2197 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2198 .recalc = &followparent_recalc,
2201 /* REVISIT: parent is really wu_l4_iclk */
2202 static struct clk wdt1_ick = {
2205 .prcm_mod = WKUP_MOD,
2206 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2207 .clkdm = { .name = "prm_clkdm" },
2208 .enable_reg = CM_ICLKEN,
2209 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2210 .recalc = &followparent_recalc,
2213 static struct clk omapctrl_ick = {
2214 .name = "omapctrl_ick",
2216 .prcm_mod = WKUP_MOD,
2217 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2219 .clkdm = { .name = "core_l4_clkdm" },
2220 .enable_reg = CM_ICLKEN,
2221 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2222 .recalc = &followparent_recalc,
2225 static struct clk icr_ick = {
2228 .prcm_mod = WKUP_MOD,
2229 .flags = CLOCK_IN_OMAP243X,
2230 .clkdm = { .name = "core_l4_clkdm" },
2231 .enable_reg = CM_ICLKEN,
2232 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2233 .recalc = &followparent_recalc,
2236 static struct clk cam_ick = {
2239 .prcm_mod = CORE_MOD,
2240 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2241 .clkdm = { .name = "core_l4_clkdm" },
2242 .enable_reg = CM_ICLKEN1,
2243 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2244 .recalc = &followparent_recalc,
2248 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2249 * split into two separate clocks, since the parent clocks are different
2250 * and the clockdomains are also different.
2252 static struct clk cam_fck = {
2254 .parent = &func_96m_ck,
2255 .prcm_mod = CORE_MOD,
2256 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2257 .clkdm = { .name = "core_l3_clkdm" },
2258 .enable_reg = CM_FCLKEN1,
2259 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2260 .recalc = &followparent_recalc,
2263 static struct clk mailboxes_ick = {
2264 .name = "mailboxes_ick",
2266 .prcm_mod = CORE_MOD,
2267 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2268 .clkdm = { .name = "core_l4_clkdm" },
2269 .enable_reg = CM_ICLKEN1,
2270 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2271 .recalc = &followparent_recalc,
2274 static struct clk wdt4_ick = {
2277 .prcm_mod = CORE_MOD,
2278 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2279 .clkdm = { .name = "core_l4_clkdm" },
2280 .enable_reg = CM_ICLKEN1,
2281 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2282 .recalc = &followparent_recalc,
2285 static struct clk wdt4_fck = {
2287 .parent = &func_32k_ck,
2288 .prcm_mod = CORE_MOD,
2289 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2290 .clkdm = { .name = "core_l4_clkdm" },
2291 .enable_reg = CM_FCLKEN1,
2292 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2293 .recalc = &followparent_recalc,
2296 static struct clk wdt3_ick = {
2299 .prcm_mod = CORE_MOD,
2300 .flags = CLOCK_IN_OMAP242X,
2301 .clkdm = { .name = "core_l4_clkdm" },
2302 .enable_reg = CM_ICLKEN1,
2303 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2304 .recalc = &followparent_recalc,
2307 static struct clk wdt3_fck = {
2309 .parent = &func_32k_ck,
2310 .prcm_mod = CORE_MOD,
2311 .flags = CLOCK_IN_OMAP242X,
2312 .clkdm = { .name = "core_l4_clkdm" },
2313 .enable_reg = CM_FCLKEN1,
2314 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2315 .recalc = &followparent_recalc,
2318 static struct clk mspro_ick = {
2319 .name = "mspro_ick",
2321 .prcm_mod = CORE_MOD,
2322 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2323 .clkdm = { .name = "core_l4_clkdm" },
2324 .enable_reg = CM_ICLKEN1,
2325 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2326 .recalc = &followparent_recalc,
2329 static struct clk mspro_fck = {
2330 .name = "mspro_fck",
2331 .parent = &func_96m_ck,
2332 .prcm_mod = CORE_MOD,
2333 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2334 .clkdm = { .name = "core_l4_clkdm" },
2335 .enable_reg = CM_FCLKEN1,
2336 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2337 .recalc = &followparent_recalc,
2340 static struct clk mmc_ick = {
2343 .prcm_mod = CORE_MOD,
2344 .flags = CLOCK_IN_OMAP242X,
2345 .clkdm = { .name = "core_l4_clkdm" },
2346 .enable_reg = CM_ICLKEN1,
2347 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2348 .recalc = &followparent_recalc,
2351 static struct clk mmc_fck = {
2353 .parent = &func_96m_ck,
2354 .prcm_mod = CORE_MOD,
2355 .flags = CLOCK_IN_OMAP242X,
2356 .clkdm = { .name = "core_l4_clkdm" },
2357 .enable_reg = CM_FCLKEN1,
2358 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2359 .recalc = &followparent_recalc,
2362 static struct clk fac_ick = {
2365 .prcm_mod = CORE_MOD,
2366 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2367 .clkdm = { .name = "core_l4_clkdm" },
2368 .enable_reg = CM_ICLKEN1,
2369 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2370 .recalc = &followparent_recalc,
2373 static struct clk fac_fck = {
2375 .parent = &func_12m_ck,
2376 .prcm_mod = CORE_MOD,
2377 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2378 .clkdm = { .name = "core_l4_clkdm" },
2379 .enable_reg = CM_FCLKEN1,
2380 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2381 .recalc = &followparent_recalc,
2384 static struct clk eac_ick = {
2387 .prcm_mod = CORE_MOD,
2388 .flags = CLOCK_IN_OMAP242X,
2389 .clkdm = { .name = "core_l4_clkdm" },
2390 .enable_reg = CM_ICLKEN1,
2391 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2392 .recalc = &followparent_recalc,
2395 static struct clk eac_fck = {
2397 .parent = &func_96m_ck,
2398 .prcm_mod = CORE_MOD,
2399 .flags = CLOCK_IN_OMAP242X,
2400 .clkdm = { .name = "core_l4_clkdm" },
2401 .enable_reg = CM_FCLKEN1,
2402 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2403 .recalc = &followparent_recalc,
2406 static struct clk hdq_ick = {
2409 .prcm_mod = CORE_MOD,
2410 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2411 .clkdm = { .name = "core_l4_clkdm" },
2412 .enable_reg = CM_ICLKEN1,
2413 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2414 .recalc = &followparent_recalc,
2417 static struct clk hdq_fck = {
2419 .parent = &func_12m_ck,
2420 .prcm_mod = CORE_MOD,
2421 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2422 .clkdm = { .name = "core_l4_clkdm" },
2423 .enable_reg = CM_FCLKEN1,
2424 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2425 .recalc = &followparent_recalc,
2428 static struct clk i2c2_ick = {
2432 .prcm_mod = CORE_MOD,
2433 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2434 .clkdm = { .name = "core_l4_clkdm" },
2435 .enable_reg = CM_ICLKEN1,
2436 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2437 .recalc = &followparent_recalc,
2440 static struct clk i2c2_fck = {
2443 .parent = &func_12m_ck,
2444 .prcm_mod = CORE_MOD,
2445 .flags = CLOCK_IN_OMAP242X,
2446 .clkdm = { .name = "core_l4_clkdm" },
2447 .enable_reg = CM_FCLKEN1,
2448 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2449 .recalc = &followparent_recalc,
2452 static struct clk i2chs2_fck = {
2453 .name = "i2chs_fck",
2455 .parent = &func_96m_ck,
2456 .prcm_mod = CORE_MOD,
2457 .flags = CLOCK_IN_OMAP243X,
2458 .clkdm = { .name = "core_l4_clkdm" },
2459 .enable_reg = OMAP24XX_CM_FCLKEN2,
2460 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2461 .recalc = &followparent_recalc,
2464 static struct clk i2c1_ick = {
2468 .prcm_mod = CORE_MOD,
2469 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2470 .clkdm = { .name = "core_l4_clkdm" },
2471 .enable_reg = CM_ICLKEN1,
2472 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2473 .recalc = &followparent_recalc,
2476 static struct clk i2c1_fck = {
2479 .parent = &func_12m_ck,
2480 .prcm_mod = CORE_MOD,
2481 .flags = CLOCK_IN_OMAP242X,
2482 .clkdm = { .name = "core_l4_clkdm" },
2483 .enable_reg = CM_FCLKEN1,
2484 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2485 .recalc = &followparent_recalc,
2488 static struct clk i2chs1_fck = {
2489 .name = "i2chs_fck",
2491 .parent = &func_96m_ck,
2492 .prcm_mod = CORE_MOD,
2493 .flags = CLOCK_IN_OMAP243X,
2494 .clkdm = { .name = "core_l4_clkdm" },
2495 .enable_reg = OMAP24XX_CM_FCLKEN2,
2496 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2497 .recalc = &followparent_recalc,
2500 static struct clk gpmc_fck = {
2502 .parent = &core_l3_ck,
2503 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2505 .clkdm = { .name = "core_l3_clkdm" },
2506 .recalc = &followparent_recalc,
2509 static struct clk sdma_fck = {
2511 .parent = &core_l3_ck,
2512 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2513 .clkdm = { .name = "core_l3_clkdm" },
2514 .recalc = &followparent_recalc,
2517 static struct clk sdma_ick = {
2520 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2521 .clkdm = { .name = "core_l3_clkdm" },
2522 .recalc = &followparent_recalc,
2525 static struct clk vlynq_ick = {
2526 .name = "vlynq_ick",
2527 .parent = &core_l3_ck,
2528 .prcm_mod = CORE_MOD,
2529 .flags = CLOCK_IN_OMAP242X,
2530 .clkdm = { .name = "core_l3_clkdm" },
2531 .enable_reg = CM_ICLKEN1,
2532 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2533 .recalc = &followparent_recalc,
2536 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2537 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2541 static const struct clksel_rate vlynq_fck_core_rates[] = {
2542 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2543 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2544 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2545 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2546 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2547 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2548 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2549 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2550 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2551 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2555 static const struct clksel vlynq_fck_clksel[] = {
2556 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2557 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2561 static struct clk vlynq_fck = {
2562 .name = "vlynq_fck",
2563 .parent = &func_96m_ck,
2564 .prcm_mod = CORE_MOD,
2565 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
2566 .clkdm = { .name = "core_l3_clkdm" },
2567 .enable_reg = CM_FCLKEN1,
2568 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2569 .init = &omap2_init_clksel_parent,
2570 .clksel_reg = CM_CLKSEL1,
2571 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2572 .clksel = vlynq_fck_clksel,
2573 .recalc = &omap2_clksel_recalc,
2574 .round_rate = &omap2_clksel_round_rate,
2575 .set_rate = &omap2_clksel_set_rate
2578 static struct clk sdrc_ick = {
2581 .prcm_mod = CORE_MOD,
2582 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2583 .clkdm = { .name = "core_l4_clkdm" },
2584 .enable_reg = CM_ICLKEN3,
2585 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2586 .recalc = &followparent_recalc,
2589 static struct clk des_ick = {
2592 .prcm_mod = CORE_MOD,
2593 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2594 .clkdm = { .name = "core_l4_clkdm" },
2595 .enable_reg = OMAP24XX_CM_ICLKEN4,
2596 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2597 .recalc = &followparent_recalc,
2600 static struct clk sha_ick = {
2603 .prcm_mod = CORE_MOD,
2604 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2605 .clkdm = { .name = "core_l4_clkdm" },
2606 .enable_reg = OMAP24XX_CM_ICLKEN4,
2607 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2608 .recalc = &followparent_recalc,
2611 static struct clk rng_ick = {
2614 .prcm_mod = CORE_MOD,
2615 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2616 .clkdm = { .name = "core_l4_clkdm" },
2617 .enable_reg = OMAP24XX_CM_ICLKEN4,
2618 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2619 .recalc = &followparent_recalc,
2622 static struct clk aes_ick = {
2625 .prcm_mod = CORE_MOD,
2626 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2627 .clkdm = { .name = "core_l4_clkdm" },
2628 .enable_reg = OMAP24XX_CM_ICLKEN4,
2629 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2630 .recalc = &followparent_recalc,
2633 static struct clk pka_ick = {
2636 .prcm_mod = CORE_MOD,
2637 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2638 .clkdm = { .name = "core_l4_clkdm" },
2639 .enable_reg = OMAP24XX_CM_ICLKEN4,
2640 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2641 .recalc = &followparent_recalc,
2644 static struct clk usb_fck = {
2646 .parent = &func_48m_ck,
2647 .prcm_mod = CORE_MOD,
2648 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2649 .clkdm = { .name = "core_l3_clkdm" },
2650 .enable_reg = OMAP24XX_CM_FCLKEN2,
2651 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2652 .recalc = &followparent_recalc,
2655 static struct clk usbhs_ick = {
2656 .name = "usbhs_ick",
2657 .parent = &core_l3_ck,
2658 .prcm_mod = CORE_MOD,
2659 .flags = CLOCK_IN_OMAP243X,
2660 .clkdm = { .name = "core_l3_clkdm" },
2661 .enable_reg = CM_ICLKEN2,
2662 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2663 .recalc = &followparent_recalc,
2666 static struct clk mmchs1_ick = {
2667 .name = "mmchs_ick",
2670 .prcm_mod = CORE_MOD,
2671 .flags = CLOCK_IN_OMAP243X,
2672 .clkdm = { .name = "core_l4_clkdm" },
2673 .enable_reg = CM_ICLKEN2,
2674 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2675 .recalc = &followparent_recalc,
2678 static struct clk mmchs1_fck = {
2679 .name = "mmchs_fck",
2681 .parent = &func_96m_ck,
2682 .prcm_mod = CORE_MOD,
2683 .flags = CLOCK_IN_OMAP243X,
2684 .clkdm = { .name = "core_l3_clkdm" },
2685 .enable_reg = OMAP24XX_CM_FCLKEN2,
2686 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2687 .recalc = &followparent_recalc,
2690 static struct clk mmchs2_ick = {
2691 .name = "mmchs_ick",
2694 .prcm_mod = CORE_MOD,
2695 .flags = CLOCK_IN_OMAP243X,
2696 .clkdm = { .name = "core_l4_clkdm" },
2697 .enable_reg = CM_ICLKEN2,
2698 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2699 .recalc = &followparent_recalc,
2702 static struct clk mmchs2_fck = {
2703 .name = "mmchs_fck",
2705 .parent = &func_96m_ck,
2706 .prcm_mod = CORE_MOD,
2707 .flags = CLOCK_IN_OMAP243X,
2708 .clkdm = { .name = "core_l4_clkdm" },
2709 .enable_reg = OMAP24XX_CM_FCLKEN2,
2710 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2711 .recalc = &followparent_recalc,
2714 static struct clk gpio5_ick = {
2715 .name = "gpio5_ick",
2717 .prcm_mod = CORE_MOD,
2718 .flags = CLOCK_IN_OMAP243X,
2719 .clkdm = { .name = "core_l4_clkdm" },
2720 .enable_reg = CM_ICLKEN2,
2721 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2722 .recalc = &followparent_recalc,
2725 static struct clk gpio5_fck = {
2726 .name = "gpio5_fck",
2727 .parent = &func_32k_ck,
2728 .prcm_mod = CORE_MOD,
2729 .flags = CLOCK_IN_OMAP243X,
2730 .clkdm = { .name = "core_l4_clkdm" },
2731 .enable_reg = OMAP24XX_CM_FCLKEN2,
2732 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2733 .recalc = &followparent_recalc,
2736 static struct clk mdm_intc_ick = {
2737 .name = "mdm_intc_ick",
2739 .prcm_mod = CORE_MOD,
2740 .flags = CLOCK_IN_OMAP243X,
2741 .clkdm = { .name = "core_l4_clkdm" },
2742 .enable_reg = CM_ICLKEN2,
2743 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2744 .recalc = &followparent_recalc,
2747 static struct clk mmchsdb1_fck = {
2748 .name = "mmchsdb_fck",
2750 .parent = &func_32k_ck,
2751 .prcm_mod = CORE_MOD,
2752 .flags = CLOCK_IN_OMAP243X,
2753 .clkdm = { .name = "core_l4_clkdm" },
2754 .enable_reg = OMAP24XX_CM_FCLKEN2,
2755 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2756 .recalc = &followparent_recalc,
2759 static struct clk mmchsdb2_fck = {
2760 .name = "mmchsdb_fck",
2762 .parent = &func_32k_ck,
2763 .prcm_mod = CORE_MOD,
2764 .flags = CLOCK_IN_OMAP243X,
2765 .clkdm = { .name = "core_l4_clkdm" },
2766 .enable_reg = OMAP24XX_CM_FCLKEN2,
2767 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2768 .recalc = &followparent_recalc,
2772 * This clock is a composite clock which does entire set changes then
2773 * forces a rebalance. It keys on the MPU speed, but it really could
2774 * be any key speed part of a set in the rate table.
2776 * to really change a set, you need memory table sets which get changed
2777 * in sram, pre-notifiers & post notifiers, changing the top set, without
2778 * having low level display recalc's won't work... this is why dpm notifiers
2779 * work, isr's off, walk a list of clocks already _off_ and not messing with
2782 * This clock should have no parent. It embodies the entire upper level
2783 * active set. A parent will mess up some of the init also.
2785 static struct clk virt_prcm_set = {
2786 .name = "virt_prcm_set",
2787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2788 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2789 .clkdm = { .name = "virt_opp_clkdm" },
2790 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2791 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2792 .set_rate = &omap2_select_table_rate,
2793 .round_rate = &omap2_round_to_table_rate,
2796 static struct clk *onchip_24xx_clks[] __initdata = {
2797 /* external root sources */
2802 /* internal analog sources */
2806 /* internal prcm root sources */
2818 /* mpu domain clocks */
2820 /* dsp domain clocks */
2823 &dsp_ick, /* 242x */
2824 &iva2_1_ick, /* 243x */
2825 &iva1_ifck, /* 242x */
2826 &iva1_mpu_int_ifck, /* 242x */
2827 /* GFX domain clocks */
2831 /* Modem domain clocks */
2834 /* DSS domain clocks */
2839 /* L3 domain clocks */
2843 /* L4 domain clocks */
2844 &l4_ck, /* used as both core_l4 and wu_l4 */
2846 /* virtual meta-group clock */
2848 /* general l4 interface ck, multi-parent functional clk */