arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*-------------------------------------------------------------------------
 604  * 24xx clock tree.
 605  *
 606  * NOTE:In many cases here we are assigning a 'default' parent. In many
 607  *      cases the parent is selectable. The get/set parent calls will also
 608  *      switch sources.
 609  *
 610  *      Many some clocks say always_enabled, but they can be auto idled for
 611  *      power savings. They will always be available upon clock request.
 612  *
 613  *      Several sources are given initial rates which may be wrong, this will
 614  *      be fixed up in the init func.
 615  *
 616  *      Things are broadly separated below by clock domains. It is
 617  *      noteworthy that most periferals have dependencies on multiple clock
 618  *      domains. Many get their interface clocks from the L4 domain, but get
 619  *      functional clocks from fixed sources or other core domain derived
 620  *      clocks.
 621  *-------------------------------------------------------------------------*/
 622
 623 /* Base external input clocks */
 624 static struct clk func_32k_ck = {
 625         .name           = "func_32k_ck",
 626         .rate           = 32000,
 627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 628                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 629         .clkdm          = { .name = "prm_clkdm" },
 630 };
 631
 632 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 633 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 634         .name           = "osc_ck",
 635         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 636                                 RATE_PROPAGATES,
 637         .clkdm          = { .name = "prm_clkdm" },
 638         .enable         = &omap2_enable_osc_ck,
 639         .disable        = &omap2_disable_osc_ck,
 640         .recalc         = &omap2_osc_clk_recalc,
 641 };
 642
 643 /* Without modem likely 12MHz, with modem likely 13MHz */
 644 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 645         .name           = "sys_ck",             /* ~ ref_clk also */
 646         .parent         = &osc_ck,
 647         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 648                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 649         .clkdm          = { .name = "prm_clkdm" },
 650         .recalc         = &omap2_sys_clk_recalc,
 651 };
 652
 653 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 654         .name           = "alt_ck",
 655         .rate           = 54000000,
 656         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 657                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 658         .clkdm          = { .name = "prm_clkdm" },
 659 };
 660
 661 /*
 662  * Analog domain root source clocks
 663  */
 664
 665 /* dpll_ck, is broken out in to special cases through clksel */
 666 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 667  * deal with this
 668  */
 669
 670 static struct dpll_data dpll_dd = {
 671         .mult_div1_reg          = CM_CLKSEL1,
 672         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 673         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 674         .control_reg            = CM_CLKEN,
 675         .enable_mask            = OMAP24XX_EN_DPLL_MASK,
 676         .max_multiplier         = 1024,
 677         .min_divider            = 1,
 678         .max_divider            = 16,
 679         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 680 };
 681
 682 /*
 683  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 684  * not just a DPLL
 685  */
 686 static struct clk dpll_ck = {
 687         .name           = "dpll_ck",
 688         .parent         = &sys_ck,              /* Can be func_32k also */
 689         .prcm_mod       = PLL_MOD,
 690         .dpll_data      = &dpll_dd,
 691         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 692                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 693         .clkdm          = { .name = "prm_clkdm" },
 694         .recalc         = &omap2_dpllcore_recalc,
 695         .set_rate       = &omap2_reprogram_dpllcore,
 696 };
 697
 698 static struct clk apll96_ck = {
 699         .name           = "apll96_ck",
 700         .parent         = &sys_ck,
 701         .prcm_mod       = PLL_MOD,
 702         .rate           = 96000000,
 703         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 704                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 705         .clkdm          = { .name = "prm_clkdm" },
 706         .enable_reg     = CM_CLKEN,
 707         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 708         .enable         = &omap2_clk_fixed_enable,
 709         .disable        = &omap2_clk_fixed_disable,
 710 };
 711
 712 static struct clk apll54_ck = {
 713         .name           = "apll54_ck",
 714         .parent         = &sys_ck,
 715         .prcm_mod       = PLL_MOD,
 716         .rate           = 54000000,
 717         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 718                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 719         .clkdm          = { .name = "prm_clkdm" },
 720         .enable_reg     = CM_CLKEN,
 721         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 722         .enable         = &omap2_clk_fixed_enable,
 723         .disable        = &omap2_clk_fixed_disable,
 724 };
 725
 726 /*
 727  * PRCM digital base sources
 728  */
 729
 730 /* func_54m_ck */
 731
 732 static const struct clksel_rate func_54m_apll54_rates[] = {
 733         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 734         { .div = 0 },
 735 };
 736
 737 static const struct clksel_rate func_54m_alt_rates[] = {
 738         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 739         { .div = 0 },
 740 };
 741
 742 static const struct clksel func_54m_clksel[] = {
 743         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 744         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 745         { .parent = NULL },
 746 };
 747
 748 static struct clk func_54m_ck = {
 749         .name           = "func_54m_ck",
 750         .parent         = &apll54_ck,   /* can also be alt_clk */
 751         .prcm_mod       = PLL_MOD,
 752         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 753                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 754         .clkdm          = { .name = "cm_clkdm" },
 755         .init           = &omap2_init_clksel_parent,
 756         .clksel_reg     = CM_CLKSEL1,
 757         .clksel_mask    = OMAP24XX_54M_SOURCE,
 758         .clksel         = func_54m_clksel,
 759         .recalc         = &omap2_clksel_recalc,
 760 };
 761
 762 static struct clk core_ck = {
 763         .name           = "core_ck",
 764         .parent         = &dpll_ck,             /* can also be 32k */
 765         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 766                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 767         .clkdm          = { .name = "cm_clkdm" },
 768         .recalc         = &followparent_recalc,
 769 };
 770
 771 /* func_96m_ck */
 772 static const struct clksel_rate func_96m_apll96_rates[] = {
 773         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 774         { .div = 0 },
 775 };
 776
 777 static const struct clksel_rate func_96m_alt_rates[] = {
 778         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 779         { .div = 0 },
 780 };
 781
 782 static const struct clksel func_96m_clksel[] = {
 783         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 784         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 785         { .parent = NULL }
 786 };
 787
 788 /* The parent of this clock is not selectable on 2420. */
 789 static struct clk func_96m_ck = {
 790         .name           = "func_96m_ck",
 791         .parent         = &apll96_ck,
 792         .prcm_mod       = PLL_MOD,
 793         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 794                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 795         .clkdm          = { .name = "cm_clkdm" },
 796         .init           = &omap2_init_clksel_parent,
 797         .clksel_reg     = CM_CLKSEL1,
 798         .clksel_mask    = OMAP2430_96M_SOURCE,
 799         .clksel         = func_96m_clksel,
 800         .recalc         = &omap2_clksel_recalc,
 801         .round_rate     = &omap2_clksel_round_rate,
 802         .set_rate       = &omap2_clksel_set_rate
 803 };
 804
 805 /* func_48m_ck */
 806
 807 static const struct clksel_rate func_48m_apll96_rates[] = {
 808         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 809         { .div = 0 },
 810 };
 811
 812 static const struct clksel_rate func_48m_alt_rates[] = {
 813         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 814         { .div = 0 },
 815 };
 816
 817 static const struct clksel func_48m_clksel[] = {
 818         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 819         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 820         { .parent = NULL }
 821 };
 822
 823 static struct clk func_48m_ck = {
 824         .name           = "func_48m_ck",
 825         .parent         = &apll96_ck,    /* 96M or Alt */
 826         .prcm_mod       = PLL_MOD,
 827         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 828                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 829         .clkdm          = { .name = "cm_clkdm" },
 830         .init           = &omap2_init_clksel_parent,
 831         .clksel_reg     = CM_CLKSEL1,
 832         .clksel_mask    = OMAP24XX_48M_SOURCE,
 833         .clksel         = func_48m_clksel,
 834         .recalc         = &omap2_clksel_recalc,
 835         .round_rate     = &omap2_clksel_round_rate,
 836         .set_rate       = &omap2_clksel_set_rate
 837 };
 838
 839 static struct clk func_12m_ck = {
 840         .name           = "func_12m_ck",
 841         .parent         = &func_48m_ck,
 842         .fixed_div      = 4,
 843         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 844                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 845         .clkdm          = { .name = "cm_clkdm" },
 846         .recalc         = &omap2_fixed_divisor_recalc,
 847 };
 848
 849 /* Secure timer, only available in secure mode */
 850 static struct clk wdt1_osc_ck = {
 851         .name           = "wdt1_osc_ck",
 852         .parent         = &osc_ck,
 853         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 854         .clkdm          = { .name = "prm_clkdm" },
 855         .recalc         = &followparent_recalc,
 856 };
 857
 858 /*
 859  * The common_clkout* clksel_rate structs are common to
 860  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 861  * sys_clkout2_* are 2420-only, so the
 862  * clksel_rate flags fields are inaccurate for those clocks. This is
 863  * harmless since access to those clocks are gated by the struct clk
 864  * flags fields, which mark them as 2420-only.
 865  */
 866 static const struct clksel_rate common_clkout_src_core_rates[] = {
 867         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 868         { .div = 0 }
 869 };
 870
 871 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 872         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 873         { .div = 0 }
 874 };
 875
 876 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 877         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 878         { .div = 0 }
 879 };
 880
 881 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 882         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 883         { .div = 0 }
 884 };
 885
 886 static const struct clksel common_clkout_src_clksel[] = {
 887         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 888         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 889         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 890         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 891         { .parent = NULL }
 892 };
 893
 894 static struct clk sys_clkout_src = {
 895         .name           = "sys_clkout_src",
 896         .parent         = &func_54m_ck,
 897         .prcm_mod       = OMAP24XX_GR_MOD,
 898         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 899                                 RATE_PROPAGATES,
 900         .clkdm          = { .name = "prm_clkdm" },
 901         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 902         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 903         .init           = &omap2_init_clksel_parent,
 904         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 905         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 906         .clksel         = common_clkout_src_clksel,
 907         .recalc         = &omap2_clksel_recalc,
 908         .round_rate     = &omap2_clksel_round_rate,
 909         .set_rate       = &omap2_clksel_set_rate
 910 };
 911
 912 static const struct clksel_rate common_clkout_rates[] = {
 913         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 914         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 915         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 916         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 917         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 918         { .div = 0 },
 919 };
 920
 921 static const struct clksel sys_clkout_clksel[] = {
 922         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 923         { .parent = NULL }
 924 };
 925
 926 static struct clk sys_clkout = {
 927         .name           = "sys_clkout",
 928         .parent         = &sys_clkout_src,
 929         .prcm_mod       = OMAP24XX_GR_MOD,
 930         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 931                                 PARENT_CONTROLS_CLOCK,
 932         .clkdm          = { .name = "prm_clkdm" },
 933         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 934         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 935         .clksel         = sys_clkout_clksel,
 936         .recalc         = &omap2_clksel_recalc,
 937         .round_rate     = &omap2_clksel_round_rate,
 938         .set_rate       = &omap2_clksel_set_rate
 939 };
 940
 941 /* In 2430, new in 2420 ES2 */
 942 static struct clk sys_clkout2_src = {
 943         .name           = "sys_clkout2_src",
 944         .parent         = &func_54m_ck,
 945         .prcm_mod       = OMAP24XX_GR_MOD,
 946         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 947         .clkdm          = { .name = "cm_clkdm" },
 948         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 949         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 950         .init           = &omap2_init_clksel_parent,
 951         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 952         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 953         .clksel         = common_clkout_src_clksel,
 954         .recalc         = &omap2_clksel_recalc,
 955         .round_rate     = &omap2_clksel_round_rate,
 956         .set_rate       = &omap2_clksel_set_rate
 957 };
 958
 959 static const struct clksel sys_clkout2_clksel[] = {
 960         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 961         { .parent = NULL }
 962 };
 963
 964 /* In 2430, new in 2420 ES2 */
 965 static struct clk sys_clkout2 = {
 966         .name           = "sys_clkout2",
 967         .parent         = &sys_clkout2_src,
 968         .prcm_mod       = OMAP24XX_GR_MOD,
 969         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 970         .clkdm          = { .name = "cm_clkdm" },
 971         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 972         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 973         .clksel         = sys_clkout2_clksel,
 974         .recalc         = &omap2_clksel_recalc,
 975         .round_rate     = &omap2_clksel_round_rate,
 976         .set_rate       = &omap2_clksel_set_rate
 977 };
 978
 979 static struct clk emul_ck = {
 980         .name           = "emul_ck",
 981         .parent         = &func_54m_ck,
 982         .prcm_mod       = OMAP24XX_GR_MOD,
 983         .flags          = CLOCK_IN_OMAP242X,
 984         .clkdm          = { .name = "cm_clkdm" },
 985         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET,
 986         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 987         .recalc         = &followparent_recalc,
 988
 989 };
 990
 991 /*
 992  * MPU clock domain
 993  *      Clocks:
 994  *              MPU_FCLK, MPU_ICLK
 995  *              INT_M_FCLK, INT_M_I_CLK
 996  *
 997  * - Individual clocks are hardware managed.
 998  * - Base divider comes from: CM_CLKSEL_MPU
 999  *
1000  */
1001 static const struct clksel_rate mpu_core_rates[] = {
1002         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1003         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1004         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1005         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1006         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1007         { .div = 0 },
1008 };
1009
1010 static const struct clksel mpu_clksel[] = {
1011         { .parent = &core_ck, .rates = mpu_core_rates },
1012         { .parent = NULL }
1013 };
1014
1015 static struct clk mpu_ck = {    /* Control cpu */
1016         .name           = "mpu_ck",
1017         .parent         = &core_ck,
1018         .prcm_mod       = MPU_MOD,
1019         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1020                                 ALWAYS_ENABLED | DELAYED_APP |
1021                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1022         .clkdm          = { .name = "mpu_clkdm" },
1023         .init           = &omap2_init_clksel_parent,
1024         .clksel_reg     = CM_CLKSEL,
1025         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1026         .clksel         = mpu_clksel,
1027         .recalc         = &omap2_clksel_recalc,
1028         .round_rate     = &omap2_clksel_round_rate,
1029         .set_rate       = &omap2_clksel_set_rate
1030 };
1031
1032 /*
1033  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1034  * Clocks:
1035  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1036  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1037  *
1038  * Won't be too specific here. The core clock comes into this block
1039  * it is divided then tee'ed. One branch goes directly to xyz enable
1040  * controls. The other branch gets further divided by 2 then possibly
1041  * routed into a synchronizer and out of clocks abc.
1042  */
1043 static const struct clksel_rate dsp_fck_core_rates[] = {
1044         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1045         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1046         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1047         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1048         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1049         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1050         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1051         { .div = 0 },
1052 };
1053
1054 static const struct clksel dsp_fck_clksel[] = {
1055         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1056         { .parent = NULL }
1057 };
1058
1059 static struct clk dsp_fck = {
1060         .name           = "dsp_fck",
1061         .parent         = &core_ck,
1062         .prcm_mod       = OMAP24XX_DSP_MOD,
1063         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1064                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1065         .clkdm          = { .name = "dsp_clkdm" },
1066         .enable_reg     = CM_FCLKEN,
1067         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1068         .clksel_reg     = CM_CLKSEL,
1069         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1070         .clksel         = dsp_fck_clksel,
1071         .recalc         = &omap2_clksel_recalc,
1072         .round_rate     = &omap2_clksel_round_rate,
1073         .set_rate       = &omap2_clksel_set_rate
1074 };
1075
1076 /* DSP interface clock */
1077 static const struct clksel_rate dsp_irate_ick_rates[] = {
1078         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1079         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1080         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1081         { .div = 0 },
1082 };
1083
1084 static const struct clksel dsp_irate_ick_clksel[] = {
1085         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1086         { .parent = NULL }
1087 };
1088
1089 /* This clock does not exist as such in the TRM. */
1090 static struct clk dsp_irate_ick = {
1091         .name           = "dsp_irate_ick",
1092         .parent         = &dsp_fck,
1093         .prcm_mod       = OMAP24XX_DSP_MOD,
1094         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1095                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1096         .clkdm          = { .name = "dsp_clkdm" },
1097         .clksel_reg     = CM_CLKSEL,
1098         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1099         .clksel         = dsp_irate_ick_clksel,
1100         .recalc         = &omap2_clksel_recalc,
1101         .round_rate     = &omap2_clksel_round_rate,
1102         .set_rate       = &omap2_clksel_set_rate
1103 };
1104
1105 /* 2420 only */
1106 static struct clk dsp_ick = {
1107         .name           = "dsp_ick",     /* apparently ipi and isp */
1108         .parent         = &dsp_irate_ick,
1109         .prcm_mod       = OMAP24XX_DSP_MOD,
1110         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1111         .clkdm          = { .name = "dsp_clkdm" },
1112         .enable_reg     = CM_ICLKEN,
1113         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1114 };
1115
1116 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1117 static struct clk iva2_1_ick = {
1118         .name           = "iva2_1_ick",
1119         .parent         = &dsp_irate_ick,
1120         .prcm_mod       = OMAP24XX_DSP_MOD,
1121         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1122         .clkdm          = { .name = "dsp_clkdm" },
1123         .enable_reg     = CM_FCLKEN,
1124         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1125 };
1126
1127 /*
1128  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1129  * the C54x, but which is contained in the DSP powerdomain.  Does not
1130  * exist on later OMAPs.
1131  */
1132 static struct clk iva1_ifck = {
1133         .name           = "iva1_ifck",
1134         .parent         = &core_ck,
1135         .prcm_mod       = OMAP24XX_DSP_MOD,
1136         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1137                                 RATE_PROPAGATES | DELAYED_APP,
1138         .clkdm          = { .name = "iva1_clkdm" },
1139         .enable_reg     = CM_FCLKEN,
1140         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1141         .clksel_reg     = CM_CLKSEL,
1142         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1143         .clksel         = dsp_fck_clksel,
1144         .recalc         = &omap2_clksel_recalc,
1145         .round_rate     = &omap2_clksel_round_rate,
1146         .set_rate       = &omap2_clksel_set_rate
1147 };
1148
1149 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1150 static struct clk iva1_mpu_int_ifck = {
1151         .name           = "iva1_mpu_int_ifck",
1152         .parent         = &iva1_ifck,
1153         .prcm_mod       = OMAP24XX_DSP_MOD,
1154         .flags          = CLOCK_IN_OMAP242X,
1155         .clkdm          = { .name = "iva1_clkdm" },
1156         .enable_reg     = CM_FCLKEN,
1157         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1158         .fixed_div      = 2,
1159         .recalc         = &omap2_fixed_divisor_recalc,
1160 };
1161
1162 /*
1163  * L3 clock domain
1164  * L3 clocks are used for both interface and functional clocks to
1165  * multiple entities. Some of these clocks are completely managed
1166  * by hardware, and some others allow software control. Hardware
1167  * managed ones general are based on directly CLK_REQ signals and
1168  * various auto idle settings. The functional spec sets many of these
1169  * as 'tie-high' for their enables.
1170  *
1171  * I-CLOCKS:
1172  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1173  *      CAM, HS-USB.
1174  * F-CLOCK
1175  *      SSI.
1176  *
1177  * GPMC memories and SDRC have timing and clock sensitive registers which
1178  * may very well need notification when the clock changes. Currently for low
1179  * operating points, these are taken care of in sleep.S.
1180  */
1181 static const struct clksel_rate core_l3_core_rates[] = {
1182         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1183         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1184         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1185         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1186         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1187         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1188         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1189         { .div = 0 }
1190 };
1191
1192 static const struct clksel core_l3_clksel[] = {
1193         { .parent = &core_ck, .rates = core_l3_core_rates },
1194         { .parent = NULL }
1195 };
1196
1197 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1198         .name           = "core_l3_ck",
1199         .parent         = &core_ck,
1200         .prcm_mod       = CORE_MOD,
1201         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1202                                 ALWAYS_ENABLED | DELAYED_APP |
1203                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1204         .clkdm          = { .name = "core_l3_clkdm" },
1205         .clksel_reg     = CM_CLKSEL1,
1206         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1207         .clksel         = core_l3_clksel,
1208         .recalc         = &omap2_clksel_recalc,
1209         .round_rate     = &omap2_clksel_round_rate,
1210         .set_rate       = &omap2_clksel_set_rate
1211 };
1212
1213 /* usb_l4_ick */
1214 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1215         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1216         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1217         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1218         { .div = 0 }
1219 };
1220
1221 static const struct clksel usb_l4_ick_clksel[] = {
1222         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1223         { .parent = NULL },
1224 };
1225
1226 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1227 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1228         .name           = "usb_l4_ick",
1229         .parent         = &core_l3_ck,
1230         .prcm_mod       = CORE_MOD,
1231         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1232                                 DELAYED_APP | CONFIG_PARTICIPANT | WAIT_READY,
1233         .clkdm          = { .name = "core_l4_clkdm" },
1234         .enable_reg     = CM_ICLKEN2,
1235         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1236         .idlest_bit     = OMAP24XX_ST_USB_SHIFT,
1237         .clksel_reg     = CM_CLKSEL1,
1238         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1239         .clksel         = usb_l4_ick_clksel,
1240         .recalc         = &omap2_clksel_recalc,
1241         .round_rate     = &omap2_clksel_round_rate,
1242         .set_rate       = &omap2_clksel_set_rate
1243 };
1244
1245 /*
1246  * L4 clock management domain
1247  *
1248  * This domain contains lots of interface clocks from the L4 interface, some
1249  * functional clocks.   Fixed APLL functional source clocks are managed in
1250  * this domain.
1251  */
1252 static const struct clksel_rate l4_core_l3_rates[] = {
1253         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1254         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1255         { .div = 0 }
1256 };
1257
1258 static const struct clksel l4_clksel[] = {
1259         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1260         { .parent = NULL }
1261 };
1262
1263 static struct clk l4_ck = {             /* used both as an ick and fck */
1264         .name           = "l4_ck",
1265         .parent         = &core_l3_ck,
1266         .prcm_mod       = CORE_MOD,
1267         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1268                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1269         .clkdm          = { .name = "core_l4_clkdm" },
1270         .clksel_reg     = CM_CLKSEL1,
1271         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1272         .clksel         = l4_clksel,
1273         .recalc         = &omap2_clksel_recalc,
1274         .round_rate     = &omap2_clksel_round_rate,
1275         .set_rate       = &omap2_clksel_set_rate
1276 };
1277
1278 /*
1279  * SSI is in L3 management domain, its direct parent is core not l3,
1280  * many core power domain entities are grouped into the L3 clock
1281  * domain.
1282  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1283  *
1284  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1285  */
1286 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1287         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1288         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1289         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1290         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1291         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1292         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1293         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1294         { .div = 0 }
1295 };
1296
1297 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1298         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1299         { .parent = NULL }
1300 };
1301
1302 static struct clk ssi_ssr_sst_fck = {
1303         .name           = "ssi_fck",
1304         .parent         = &core_ck,
1305         .prcm_mod       = CORE_MOD,
1306         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY |
1307                                 DELAYED_APP,
1308         .clkdm          = { .name = "core_l3_clkdm" },
1309         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1310         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1311         .idlest_bit     = OMAP24XX_ST_SSI_SHIFT,
1312         .clksel_reg     = CM_CLKSEL1,
1313         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1314         .clksel         = ssi_ssr_sst_fck_clksel,
1315         .recalc         = &omap2_clksel_recalc,
1316         .round_rate     = &omap2_clksel_round_rate,
1317         .set_rate       = &omap2_clksel_set_rate
1318 };
1319
1320 /*
1321  * Presumably this is the same as SSI_ICLK.
1322  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1323  */
1324 static struct clk ssi_l4_ick = {
1325         .name           = "ssi_l4_ick",
1326         .parent         = &l4_ck,
1327         .prcm_mod       = CORE_MOD,
1328         .clkdm          = { .name = "core_l4_clkdm" },
1329         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1330         .enable_reg     = CM_ICLKEN2,
1331         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1332         .idlest_bit     = OMAP24XX_ST_SSI_SHIFT,
1333         .recalc         = &followparent_recalc,
1334 };
1335
1336
1337 /*
1338  * GFX clock domain
1339  *      Clocks:
1340  * GFX_FCLK, GFX_ICLK
1341  * GFX_CG1(2d), GFX_CG2(3d)
1342  *
1343  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1344  * The 2d and 3d clocks run at a hardware determined
1345  * divided value of fclk.
1346  *
1347  */
1348 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1349
1350 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1351 static const struct clksel gfx_fck_clksel[] = {
1352         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1353         { .parent = NULL },
1354 };
1355
1356 static struct clk gfx_3d_fck = {
1357         .name           = "gfx_3d_fck",
1358         .parent         = &core_l3_ck,
1359         .prcm_mod       = GFX_MOD,
1360         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1361         .clkdm          = { .name = "gfx_clkdm" },
1362         .enable_reg     = CM_FCLKEN,
1363         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1364         .clksel_reg     = CM_CLKSEL,
1365         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1366         .clksel         = gfx_fck_clksel,
1367         .recalc         = &omap2_clksel_recalc,
1368         .round_rate     = &omap2_clksel_round_rate,
1369         .set_rate       = &omap2_clksel_set_rate
1370 };
1371
1372 static struct clk gfx_2d_fck = {
1373         .name           = "gfx_2d_fck",
1374         .parent         = &core_l3_ck,
1375         .prcm_mod       = GFX_MOD,
1376         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1377         .clkdm          = { .name = "gfx_clkdm" },
1378         .enable_reg     = CM_FCLKEN,
1379         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1380         .clksel_reg     = CM_CLKSEL,
1381         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1382         .clksel         = gfx_fck_clksel,
1383         .recalc         = &omap2_clksel_recalc,
1384         .round_rate     = &omap2_clksel_round_rate,
1385         .set_rate       = &omap2_clksel_set_rate
1386 };
1387
1388 static struct clk gfx_ick = {
1389         .name           = "gfx_ick",            /* From l3 */
1390         .parent         = &core_l3_ck,
1391         .prcm_mod       = GFX_MOD,
1392         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1393         .clkdm          = { .name = "gfx_clkdm" },
1394         .enable_reg     = CM_ICLKEN,
1395         .enable_bit     = OMAP_EN_GFX_SHIFT,
1396         .recalc         = &followparent_recalc,
1397 };
1398
1399 /*
1400  * Modem clock domain (2430)
1401  *      CLOCKS:
1402  *              MDM_OSC_CLK
1403  *              MDM_ICLK
1404  * These clocks are usable in chassis mode only.
1405  */
1406 static const struct clksel_rate mdm_ick_core_rates[] = {
1407         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1408         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1409         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1410         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1411         { .div = 0 }
1412 };
1413
1414 static const struct clksel mdm_ick_clksel[] = {
1415         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1416         { .parent = NULL }
1417 };
1418
1419 static struct clk mdm_ick = {           /* used both as a ick and fck */
1420         .name           = "mdm_ick",
1421         .parent         = &core_ck,
1422         .prcm_mod       = OMAP2430_MDM_MOD,
1423         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1424         .clkdm          = { .name = "mdm_clkdm" },
1425         .enable_reg     = CM_ICLKEN,
1426         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1427         .clksel_reg     = CM_CLKSEL,
1428         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1429         .clksel         = mdm_ick_clksel,
1430         .recalc         = &omap2_clksel_recalc,
1431         .round_rate     = &omap2_clksel_round_rate,
1432         .set_rate       = &omap2_clksel_set_rate
1433 };
1434
1435 static struct clk mdm_osc_ck = {
1436         .name           = "mdm_osc_ck",
1437         .parent         = &osc_ck,
1438         .prcm_mod       = OMAP2430_MDM_MOD,
1439         .flags          = CLOCK_IN_OMAP243X,
1440         .clkdm          = { .name = "mdm_clkdm" },
1441         .enable_reg     = CM_FCLKEN,
1442         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1443         .recalc         = &followparent_recalc,
1444 };
1445
1446 /*
1447  * DSS clock domain
1448  * CLOCKs:
1449  * DSS_L4_ICLK, DSS_L3_ICLK,
1450  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1451  *
1452  * DSS is both initiator and target.
1453  */
1454 /* XXX Add RATE_NOT_VALIDATED */
1455
1456 static const struct clksel_rate dss1_fck_sys_rates[] = {
1457         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1458         { .div = 0 }
1459 };
1460
1461 static const struct clksel_rate dss1_fck_core_rates[] = {
1462         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1463         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1464         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1465         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1466         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1467         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1468         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1469         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1470         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1471         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1472         { .div = 0 }
1473 };
1474
1475 static const struct clksel dss1_fck_clksel[] = {
1476         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1477         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1478         { .parent = NULL },
1479 };
1480
1481 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1482         .name           = "dss_ick",
1483         .parent         = &l4_ck,       /* really both l3 and l4 */
1484         .prcm_mod       = CORE_MOD,
1485         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1486         .clkdm          = { .name = "dss_clkdm" },
1487         .enable_reg     = CM_ICLKEN1,
1488         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1489         .recalc         = &followparent_recalc,
1490 };
1491
1492 static struct clk dss1_fck = {
1493         .name           = "dss1_fck",
1494         .parent         = &core_ck,             /* Core or sys */
1495         .prcm_mod       = CORE_MOD,
1496         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1497                                 DELAYED_APP,
1498         .clkdm          = { .name = "dss_clkdm" },
1499         .enable_reg     = CM_FCLKEN1,
1500         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1501         .init           = &omap2_init_clksel_parent,
1502         .clksel_reg     = CM_CLKSEL1,
1503         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1504         .clksel         = dss1_fck_clksel,
1505         .recalc         = &omap2_clksel_recalc,
1506         .round_rate     = &omap2_clksel_round_rate,
1507         .set_rate       = &omap2_clksel_set_rate
1508 };
1509
1510 static const struct clksel_rate dss2_fck_sys_rates[] = {
1511         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1512         { .div = 0 }
1513 };
1514
1515 static const struct clksel_rate dss2_fck_48m_rates[] = {
1516         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1517         { .div = 0 }
1518 };
1519
1520 static const struct clksel dss2_fck_clksel[] = {
1521         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1522         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1523         { .parent = NULL }
1524 };
1525
1526 static struct clk dss2_fck = {          /* Alt clk used in power management */
1527         .name           = "dss2_fck",
1528         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1529         .prcm_mod       = CORE_MOD,
1530         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1531                                 DELAYED_APP,
1532         .clkdm          = { .name = "dss_clkdm" },
1533         .enable_reg     = CM_FCLKEN1,
1534         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1535         .init           = &omap2_init_clksel_parent,
1536         .clksel_reg     = CM_CLKSEL1,
1537         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1538         .clksel         = dss2_fck_clksel,
1539         .recalc         = &followparent_recalc,
1540 };
1541
1542 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1543         .name           = "dss_54m_fck",        /* 54m tv clk */
1544         .parent         = &func_54m_ck,
1545         .prcm_mod       = CORE_MOD,
1546         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1547         .clkdm          = { .name = "dss_clkdm" },
1548         .enable_reg     = CM_FCLKEN1,
1549         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1550         .recalc         = &followparent_recalc,
1551 };
1552
1553 /*
1554  * CORE power domain ICLK & FCLK defines.
1555  * Many of the these can have more than one possible parent. Entries
1556  * here will likely have an L4 interface parent, and may have multiple
1557  * functional clock parents.
1558  */
1559 static const struct clksel_rate gpt_alt_rates[] = {
1560         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1561         { .div = 0 }
1562 };
1563
1564 static const struct clksel omap24xx_gpt_clksel[] = {
1565         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1566         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1567         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1568         { .parent = NULL },
1569 };
1570
1571 static struct clk gpt1_ick = {
1572         .name           = "gpt1_ick",
1573         .parent         = &l4_ck,
1574         .prcm_mod       = WKUP_MOD,
1575         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1576         .clkdm          = { .name = "core_l4_clkdm" },
1577         .enable_reg     = CM_ICLKEN,
1578         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1579         .idlest_bit     = OMAP24XX_ST_GPT1_SHIFT,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk gpt1_fck = {
1584         .name           = "gpt1_fck",
1585         .parent         = &func_32k_ck,
1586         .prcm_mod       = WKUP_MOD,
1587         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1588         .clkdm          = { .name = "core_l4_clkdm" },
1589         .enable_reg     = CM_FCLKEN,
1590         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1591         .init           = &omap2_init_clksel_parent,
1592         .clksel_reg     = CM_CLKSEL1,
1593         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1594         .clksel         = omap24xx_gpt_clksel,
1595         .recalc         = &omap2_clksel_recalc,
1596         .round_rate     = &omap2_clksel_round_rate,
1597         .set_rate       = &omap2_clksel_set_rate
1598 };
1599
1600 static struct clk gpt2_ick = {
1601         .name           = "gpt2_ick",
1602         .parent         = &l4_ck,
1603         .prcm_mod       = CORE_MOD,
1604         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1605         .clkdm          = { .name = "core_l4_clkdm" },
1606         .enable_reg     = CM_ICLKEN1,
1607         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1608         .idlest_bit     = OMAP24XX_ST_GPT2_SHIFT,
1609         .recalc         = &followparent_recalc,
1610 };
1611
1612 static struct clk gpt2_fck = {
1613         .name           = "gpt2_fck",
1614         .parent         = &func_32k_ck,
1615         .prcm_mod       = CORE_MOD,
1616         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1617         .clkdm          = { .name = "core_l4_clkdm" },
1618         .enable_reg     = CM_FCLKEN1,
1619         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1620         .init           = &omap2_init_clksel_parent,
1621         .clksel_reg     = CM_CLKSEL2,
1622         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1623         .clksel         = omap24xx_gpt_clksel,
1624         .recalc         = &omap2_clksel_recalc,
1625 };
1626
1627 static struct clk gpt3_ick = {
1628         .name           = "gpt3_ick",
1629         .parent         = &l4_ck,
1630         .prcm_mod       = CORE_MOD,
1631         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1632         .clkdm          = { .name = "core_l4_clkdm" },
1633         .enable_reg     = CM_ICLKEN1,
1634         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1635         .idlest_bit     = OMAP24XX_ST_GPT3_SHIFT,
1636         .recalc         = &followparent_recalc,
1637 };
1638
1639 static struct clk gpt3_fck = {
1640         .name           = "gpt3_fck",
1641         .parent         = &func_32k_ck,
1642         .prcm_mod       = CORE_MOD,
1643         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1644         .clkdm          = { .name = "core_l4_clkdm" },
1645         .enable_reg     = CM_FCLKEN1,
1646         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1647         .init           = &omap2_init_clksel_parent,
1648         .clksel_reg     = CM_CLKSEL2,
1649         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1650         .clksel         = omap24xx_gpt_clksel,
1651         .recalc         = &omap2_clksel_recalc,
1652 };
1653
1654 static struct clk gpt4_ick = {
1655         .name           = "gpt4_ick",
1656         .parent         = &l4_ck,
1657         .prcm_mod       = CORE_MOD,
1658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1659         .clkdm          = { .name = "core_l4_clkdm" },
1660         .enable_reg     = CM_ICLKEN1,
1661         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1662         .idlest_bit     = OMAP24XX_ST_GPT4_SHIFT,
1663         .recalc         = &followparent_recalc,
1664 };
1665
1666 static struct clk gpt4_fck = {
1667         .name           = "gpt4_fck",
1668         .parent         = &func_32k_ck,
1669         .prcm_mod       = CORE_MOD,
1670         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1671         .clkdm          = { .name = "core_l4_clkdm" },
1672         .enable_reg     = CM_FCLKEN1,
1673         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1674         .init           = &omap2_init_clksel_parent,
1675         .clksel_reg     = CM_CLKSEL2,
1676         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1677         .clksel         = omap24xx_gpt_clksel,
1678         .recalc         = &omap2_clksel_recalc,
1679 };
1680
1681 static struct clk gpt5_ick = {
1682         .name           = "gpt5_ick",
1683         .parent         = &l4_ck,
1684         .prcm_mod       = CORE_MOD,
1685         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1686         .clkdm          = { .name = "core_l4_clkdm" },
1687         .enable_reg     = CM_ICLKEN1,
1688         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1689         .idlest_bit     = OMAP24XX_ST_GPT5_SHIFT,
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 static struct clk gpt5_fck = {
1694         .name           = "gpt5_fck",
1695         .parent         = &func_32k_ck,
1696         .prcm_mod       = CORE_MOD,
1697         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1698         .clkdm          = { .name = "core_l4_clkdm" },
1699         .enable_reg     = CM_FCLKEN1,
1700         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1701         .init           = &omap2_init_clksel_parent,
1702         .clksel_reg     = CM_CLKSEL2,
1703         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1704         .clksel         = omap24xx_gpt_clksel,
1705         .recalc         = &omap2_clksel_recalc,
1706 };
1707
1708 static struct clk gpt6_ick = {
1709         .name           = "gpt6_ick",
1710         .parent         = &l4_ck,
1711         .prcm_mod       = CORE_MOD,
1712         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1713         .clkdm          = { .name = "core_l4_clkdm" },
1714         .enable_reg     = CM_ICLKEN1,
1715         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1716         .idlest_bit     = OMAP24XX_ST_GPT6_SHIFT,
1717         .recalc         = &followparent_recalc,
1718 };
1719
1720 static struct clk gpt6_fck = {
1721         .name           = "gpt6_fck",
1722         .parent         = &func_32k_ck,
1723         .prcm_mod       = CORE_MOD,
1724         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1725         .clkdm          = { .name = "core_l4_clkdm" },
1726         .enable_reg     = CM_FCLKEN1,
1727         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1728         .init           = &omap2_init_clksel_parent,
1729         .clksel_reg     = CM_CLKSEL2,
1730         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1731         .clksel         = omap24xx_gpt_clksel,
1732         .recalc         = &omap2_clksel_recalc,
1733 };
1734
1735 static struct clk gpt7_ick = {
1736         .name           = "gpt7_ick",
1737         .parent         = &l4_ck,
1738         .prcm_mod       = CORE_MOD,
1739         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1740         .clkdm          = { .name = "core_l4_clkdm" },
1741         .enable_reg     = CM_ICLKEN1,
1742         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1743         .idlest_bit     = OMAP24XX_ST_GPT7_SHIFT,
1744         .recalc         = &followparent_recalc,
1745 };
1746
1747 static struct clk gpt7_fck = {
1748         .name           = "gpt7_fck",
1749         .parent         = &func_32k_ck,
1750         .prcm_mod       = CORE_MOD,
1751         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1752         .clkdm          = { .name = "core_l4_clkdm" },
1753         .enable_reg     = CM_FCLKEN1,
1754         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1755         .init           = &omap2_init_clksel_parent,
1756         .clksel_reg     = CM_CLKSEL2,
1757         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1758         .clksel         = omap24xx_gpt_clksel,
1759         .recalc         = &omap2_clksel_recalc,
1760 };
1761
1762 static struct clk gpt8_ick = {
1763         .name           = "gpt8_ick",
1764         .parent         = &l4_ck,
1765         .prcm_mod       = CORE_MOD,
1766         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1767         .clkdm          = { .name = "core_l4_clkdm" },
1768         .enable_reg     = CM_ICLKEN1,
1769         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1770         .idlest_bit     = OMAP24XX_ST_GPT8_SHIFT,
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk gpt8_fck = {
1775         .name           = "gpt8_fck",
1776         .parent         = &func_32k_ck,
1777         .prcm_mod       = CORE_MOD,
1778         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1779         .clkdm          = { .name = "core_l4_clkdm" },
1780         .enable_reg     = CM_FCLKEN1,
1781         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1782         .init           = &omap2_init_clksel_parent,
1783         .clksel_reg     = CM_CLKSEL2,
1784         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1785         .clksel         = omap24xx_gpt_clksel,
1786         .recalc         = &omap2_clksel_recalc,
1787 };
1788
1789 static struct clk gpt9_ick = {
1790         .name           = "gpt9_ick",
1791         .parent         = &l4_ck,
1792         .prcm_mod       = CORE_MOD,
1793         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1794         .clkdm          = { .name = "core_l4_clkdm" },
1795         .enable_reg     = CM_ICLKEN1,
1796         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1797         .idlest_bit     = OMAP24XX_ST_GPT9_SHIFT,
1798         .recalc         = &followparent_recalc,
1799 };
1800
1801 static struct clk gpt9_fck = {
1802         .name           = "gpt9_fck",
1803         .parent         = &func_32k_ck,
1804         .prcm_mod       = CORE_MOD,
1805         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1806         .clkdm          = { .name = "core_l4_clkdm" },
1807         .enable_reg     = CM_FCLKEN1,
1808         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1809         .init           = &omap2_init_clksel_parent,
1810         .clksel_reg     = CM_CLKSEL2,
1811         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1812         .clksel         = omap24xx_gpt_clksel,
1813         .recalc         = &omap2_clksel_recalc,
1814 };
1815
1816 static struct clk gpt10_ick = {
1817         .name           = "gpt10_ick",
1818         .parent         = &l4_ck,
1819         .prcm_mod       = CORE_MOD,
1820         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1821         .clkdm          = { .name = "core_l4_clkdm" },
1822         .enable_reg     = CM_ICLKEN1,
1823         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1824         .idlest_bit     = OMAP24XX_ST_GPT10_SHIFT,
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk gpt10_fck = {
1829         .name           = "gpt10_fck",
1830         .parent         = &func_32k_ck,
1831         .prcm_mod       = CORE_MOD,
1832         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1833         .clkdm          = { .name = "core_l4_clkdm" },
1834         .enable_reg     = CM_FCLKEN1,
1835         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1836         .init           = &omap2_init_clksel_parent,
1837         .clksel_reg     = CM_CLKSEL2,
1838         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1839         .clksel         = omap24xx_gpt_clksel,
1840         .recalc         = &omap2_clksel_recalc,
1841 };
1842
1843 static struct clk gpt11_ick = {
1844         .name           = "gpt11_ick",
1845         .parent         = &l4_ck,
1846         .prcm_mod       = CORE_MOD,
1847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1848         .clkdm          = { .name = "core_l4_clkdm" },
1849         .enable_reg     = CM_ICLKEN1,
1850         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1851         .idlest_bit     = OMAP24XX_ST_GPT11_SHIFT,
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk gpt11_fck = {
1856         .name           = "gpt11_fck",
1857         .parent         = &func_32k_ck,
1858         .prcm_mod       = CORE_MOD,
1859         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1860         .clkdm          = { .name = "core_l4_clkdm" },
1861         .enable_reg     = CM_FCLKEN1,
1862         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1863         .init           = &omap2_init_clksel_parent,
1864         .clksel_reg     = CM_CLKSEL2,
1865         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1866         .clksel         = omap24xx_gpt_clksel,
1867         .recalc         = &omap2_clksel_recalc,
1868 };
1869
1870 static struct clk gpt12_ick = {
1871         .name           = "gpt12_ick",
1872         .parent         = &l4_ck,
1873         .prcm_mod       = CORE_MOD,
1874         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1875         .clkdm          = { .name = "core_l4_clkdm" },
1876         .enable_reg     = CM_ICLKEN1,
1877         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1878         .idlest_bit     = OMAP24XX_ST_GPT12_SHIFT,
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk gpt12_fck = {
1883         .name           = "gpt12_fck",
1884         .parent         = &func_32k_ck,
1885         .prcm_mod       = CORE_MOD,
1886         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1887         .clkdm          = { .name = "core_l4_clkdm" },
1888         .enable_reg     = CM_FCLKEN1,
1889         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1890         .init           = &omap2_init_clksel_parent,
1891         .clksel_reg     = CM_CLKSEL2,
1892         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1893         .clksel         = omap24xx_gpt_clksel,
1894         .recalc         = &omap2_clksel_recalc,
1895 };
1896
1897 static struct clk mcbsp1_ick = {
1898         .name           = "mcbsp_ick",
1899         .id             = 1,
1900         .parent         = &l4_ck,
1901         .prcm_mod       = CORE_MOD,
1902         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1903         .clkdm          = { .name = "core_l4_clkdm" },
1904         .enable_reg     = CM_ICLKEN1,
1905         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1906         .idlest_bit     = OMAP24XX_ST_MCBSP1_SHIFT,
1907         .recalc         = &followparent_recalc,
1908 };
1909
1910 static struct clk mcbsp1_fck = {
1911         .name           = "mcbsp_fck",
1912         .id             = 1,
1913         .parent         = &func_96m_ck,
1914         .prcm_mod       = CORE_MOD,
1915         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1916         .clkdm          = { .name = "core_l4_clkdm" },
1917         .enable_reg     = CM_FCLKEN1,
1918         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk mcbsp2_ick = {
1923         .name           = "mcbsp_ick",
1924         .id             = 2,
1925         .parent         = &l4_ck,
1926         .prcm_mod       = CORE_MOD,
1927         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1928         .clkdm          = { .name = "core_l4_clkdm" },
1929         .enable_reg     = CM_ICLKEN1,
1930         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1931         .idlest_bit     = OMAP24XX_ST_MCBSP2_SHIFT,
1932         .recalc         = &followparent_recalc,
1933 };
1934
1935 static struct clk mcbsp2_fck = {
1936         .name           = "mcbsp_fck",
1937         .id             = 2,
1938         .parent         = &func_96m_ck,
1939         .prcm_mod       = CORE_MOD,
1940         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1941         .clkdm          = { .name = "core_l4_clkdm" },
1942         .enable_reg     = CM_FCLKEN1,
1943         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1944         .recalc         = &followparent_recalc,
1945 };
1946
1947 static struct clk mcbsp3_ick = {
1948         .name           = "mcbsp_ick",
1949         .id             = 3,
1950         .parent         = &l4_ck,
1951         .prcm_mod       = CORE_MOD,
1952         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1953         .clkdm          = { .name = "core_l4_clkdm" },
1954         .enable_reg     = CM_ICLKEN2,
1955         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1956         .idlest_bit     = OMAP2430_ST_MCBSP3_SHIFT,
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 static struct clk mcbsp3_fck = {
1961         .name           = "mcbsp_fck",
1962         .id             = 3,
1963         .parent         = &func_96m_ck,
1964         .prcm_mod       = CORE_MOD,
1965         .flags          = CLOCK_IN_OMAP243X,
1966         .clkdm          = { .name = "core_l4_clkdm" },
1967         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1968         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1969         .recalc         = &followparent_recalc,
1970 };
1971
1972 static struct clk mcbsp4_ick = {
1973         .name           = "mcbsp_ick",
1974         .id             = 4,
1975         .parent         = &l4_ck,
1976         .prcm_mod       = CORE_MOD,
1977         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1978         .clkdm          = { .name = "core_l4_clkdm" },
1979         .enable_reg     = CM_ICLKEN2,
1980         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1981         .idlest_bit     = OMAP2430_ST_MCBSP4_SHIFT,
1982         .recalc         = &followparent_recalc,
1983 };
1984
1985 static struct clk mcbsp4_fck = {
1986         .name           = "mcbsp_fck",
1987         .id             = 4,
1988         .parent         = &func_96m_ck,
1989         .prcm_mod       = CORE_MOD,
1990         .flags          = CLOCK_IN_OMAP243X,
1991         .clkdm          = { .name = "core_l4_clkdm" },
1992         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1993         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk mcbsp5_ick = {
1998         .name           = "mcbsp_ick",
1999         .id             = 5,
2000         .parent         = &l4_ck,
2001         .prcm_mod       = CORE_MOD,
2002         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2003         .clkdm          = { .name = "core_l4_clkdm" },
2004         .enable_reg     = CM_ICLKEN2,
2005         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2006         .idlest_bit     = OMAP2430_ST_MCBSP5_SHIFT,
2007         .recalc         = &followparent_recalc,
2008 };
2009
2010 static struct clk mcbsp5_fck = {
2011         .name           = "mcbsp_fck",
2012         .id             = 5,
2013         .parent         = &func_96m_ck,
2014         .prcm_mod       = CORE_MOD,
2015         .flags          = CLOCK_IN_OMAP243X,
2016         .clkdm          = { .name = "core_l4_clkdm" },
2017         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2018         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2019         .recalc         = &followparent_recalc,
2020 };
2021
2022 static struct clk mcspi1_ick = {
2023         .name           = "mcspi_ick",
2024         .id             = 1,
2025         .parent         = &l4_ck,
2026         .prcm_mod       = CORE_MOD,
2027         .clkdm          = { .name = "core_l4_clkdm" },
2028         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2029         .enable_reg     = CM_ICLKEN1,
2030         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2031         .idlest_bit     = OMAP24XX_ST_MCSPI1_SHIFT,
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 static struct clk mcspi1_fck = {
2036         .name           = "mcspi_fck",
2037         .id             = 1,
2038         .parent         = &func_48m_ck,
2039         .prcm_mod       = CORE_MOD,
2040         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2041         .clkdm          = { .name = "core_l4_clkdm" },
2042         .enable_reg     = CM_FCLKEN1,
2043         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2044         .recalc         = &followparent_recalc,
2045 };
2046
2047 static struct clk mcspi2_ick = {
2048         .name           = "mcspi_ick",
2049         .id             = 2,
2050         .parent         = &l4_ck,
2051         .prcm_mod       = CORE_MOD,
2052         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2053         .clkdm          = { .name = "core_l4_clkdm" },
2054         .enable_reg     = CM_ICLKEN1,
2055         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2056         .idlest_bit     = OMAP24XX_ST_MCSPI2_SHIFT,
2057         .recalc         = &followparent_recalc,
2058 };
2059
2060 static struct clk mcspi2_fck = {
2061         .name           = "mcspi_fck",
2062         .id             = 2,
2063         .parent         = &func_48m_ck,
2064         .prcm_mod       = CORE_MOD,
2065         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2066         .clkdm          = { .name = "core_l4_clkdm" },
2067         .enable_reg     = CM_FCLKEN1,
2068         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2069         .recalc         = &followparent_recalc,
2070 };
2071
2072 static struct clk mcspi3_ick = {
2073         .name           = "mcspi_ick",
2074         .id             = 3,
2075         .parent         = &l4_ck,
2076         .prcm_mod       = CORE_MOD,
2077         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2078         .clkdm          = { .name = "core_l4_clkdm" },
2079         .enable_reg     = CM_ICLKEN2,
2080         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2081         .idlest_bit     = OMAP2430_ST_MCSPI3_SHIFT,
2082         .recalc         = &followparent_recalc,
2083 };
2084
2085 static struct clk mcspi3_fck = {
2086         .name           = "mcspi_fck",
2087         .id             = 3,
2088         .parent         = &func_48m_ck,
2089         .prcm_mod       = CORE_MOD,
2090         .flags          = CLOCK_IN_OMAP243X,
2091         .clkdm          = { .name = "core_l4_clkdm" },
2092         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2093         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2094         .recalc         = &followparent_recalc,
2095 };
2096
2097 static struct clk uart1_ick = {
2098         .name           = "uart1_ick",
2099         .parent         = &l4_ck,
2100         .prcm_mod       = CORE_MOD,
2101         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2102         .clkdm          = { .name = "core_l4_clkdm" },
2103         .enable_reg     = CM_ICLKEN1,
2104         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2105         .idlest_bit     = OMAP24XX_ST_UART1_SHIFT,
2106         .recalc         = &followparent_recalc,
2107 };
2108
2109 static struct clk uart1_fck = {
2110         .name           = "uart1_fck",
2111         .parent         = &func_48m_ck,
2112         .prcm_mod       = CORE_MOD,
2113         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2114         .clkdm          = { .name = "core_l4_clkdm" },
2115         .enable_reg     = CM_FCLKEN1,
2116         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk uart2_ick = {
2121         .name           = "uart2_ick",
2122         .parent         = &l4_ck,
2123         .prcm_mod       = CORE_MOD,
2124         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2125         .clkdm          = { .name = "core_l4_clkdm" },
2126         .enable_reg     = CM_ICLKEN1,
2127         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2128         .idlest_bit     = OMAP24XX_ST_UART2_SHIFT,
2129         .recalc         = &followparent_recalc,
2130 };
2131
2132 static struct clk uart2_fck = {
2133         .name           = "uart2_fck",
2134         .parent         = &func_48m_ck,
2135         .prcm_mod       = CORE_MOD,
2136         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2137         .clkdm          = { .name = "core_l4_clkdm" },
2138         .enable_reg     = CM_FCLKEN1,
2139         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2140         .recalc         = &followparent_recalc,
2141 };
2142
2143 static struct clk uart3_ick = {
2144         .name           = "uart3_ick",
2145         .parent         = &l4_ck,
2146         .prcm_mod       = CORE_MOD,
2147         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2148         .clkdm          = { .name = "core_l4_clkdm" },
2149         .enable_reg     = CM_ICLKEN2,
2150         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2151         .idlest_bit     = OMAP24XX_ST_UART3_SHIFT,
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 static struct clk uart3_fck = {
2156         .name           = "uart3_fck",
2157         .parent         = &func_48m_ck,
2158         .prcm_mod       = CORE_MOD,
2159         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2160         .clkdm          = { .name = "core_l4_clkdm" },
2161         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2162         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2163         .recalc         = &followparent_recalc,
2164 };
2165
2166 static struct clk gpios_ick = {
2167         .name           = "gpios_ick",
2168         .parent         = &l4_ck,
2169         .prcm_mod       = WKUP_MOD,
2170         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2171         .clkdm          = { .name = "core_l4_clkdm" },
2172         .enable_reg     = CM_ICLKEN,
2173         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2174         .idlest_bit     = OMAP24XX_ST_GPIOS_SHIFT,
2175         .recalc         = &followparent_recalc,
2176 };
2177
2178 static struct clk gpios_fck = {
2179         .name           = "gpios_fck",
2180         .parent         = &func_32k_ck,
2181         .prcm_mod       = WKUP_MOD,
2182         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2183         .clkdm          = { .name = "prm_clkdm" },
2184         .enable_reg     = CM_FCLKEN,
2185         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2186         .idlest_bit     = OMAP24XX_ST_GPIOS_SHIFT,
2187         .recalc         = &followparent_recalc,
2188 };
2189
2190 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2191 static struct clk mpu_wdt_ick = {
2192         .name           = "mpu_wdt_ick",
2193         .parent         = &l4_ck,
2194         .prcm_mod       = WKUP_MOD,
2195         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2196         .clkdm          = { .name = "prm_clkdm" },
2197         .enable_reg     = CM_ICLKEN,
2198         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2199         .idlest_bit     = OMAP24XX_ST_MPU_WDT_SHIFT,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 /* aka WDT2 */
2204 static struct clk mpu_wdt_fck = {
2205         .name           = "mpu_wdt_fck",
2206         .parent         = &func_32k_ck,
2207         .prcm_mod       = WKUP_MOD,
2208         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2209         .clkdm          = { .name = "prm_clkdm" },
2210         .enable_reg     = CM_FCLKEN,
2211         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2212         .idlest_bit     = OMAP24XX_ST_MPU_WDT_SHIFT,
2213         .recalc         = &followparent_recalc,
2214 };
2215
2216 static struct clk sync_32k_ick = {
2217         .name           = "sync_32k_ick",
2218         .parent         = &l4_ck,
2219         .prcm_mod       = WKUP_MOD,
2220         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2221                                 ENABLE_ON_INIT | WAIT_READY,
2222         .clkdm          = { .name = "core_l4_clkdm" },
2223         .enable_reg     = CM_ICLKEN,
2224         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2225         .idlest_bit     = OMAP24XX_ST_32KSYNC_SHIFT,
2226         .recalc         = &followparent_recalc,
2227 };
2228
2229 /* REVISIT: parent is really wu_l4_iclk */
2230 static struct clk wdt1_ick = {
2231         .name           = "wdt1_ick",
2232         .parent         = &l4_ck,
2233         .prcm_mod       = WKUP_MOD,
2234         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2235         .clkdm          = { .name = "prm_clkdm" },
2236         .enable_reg     = CM_ICLKEN,
2237         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2238         .idlest_bit     = OMAP24XX_ST_WDT1_SHIFT,
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 static struct clk omapctrl_ick = {
2243         .name           = "omapctrl_ick",
2244         .parent         = &l4_ck,
2245         .prcm_mod       = WKUP_MOD,
2246         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2247                                 ENABLE_ON_INIT,
2248         .clkdm          = { .name = "core_l4_clkdm" },
2249         .enable_reg     = CM_ICLKEN,
2250         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2251         .idlest_bit     = OMAP24XX_ST_OMAPCTRL_SHIFT,
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 static struct clk icr_ick = {
2256         .name           = "icr_ick",
2257         .parent         = &l4_ck,
2258         .prcm_mod       = WKUP_MOD,
2259         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2260         .clkdm          = { .name = "core_l4_clkdm" },
2261         .enable_reg     = CM_ICLKEN,
2262         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2263         .idlest_bit     = OMAP2430_ST_ICR_SHIFT,
2264         .recalc         = &followparent_recalc,
2265 };
2266
2267 static struct clk cam_ick = {
2268         .name           = "cam_ick",
2269         .parent         = &l4_ck,
2270         .prcm_mod       = CORE_MOD,
2271         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2272         .clkdm          = { .name = "core_l4_clkdm" },
2273         .enable_reg     = CM_ICLKEN1,
2274         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2275         .recalc         = &followparent_recalc,
2276 };
2277
2278 /*
2279  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2280  * split into two separate clocks, since the parent clocks are different
2281  * and the clockdomains are also different.
2282  */
2283 static struct clk cam_fck = {
2284         .name           = "cam_fck",
2285         .parent         = &func_96m_ck,
2286         .prcm_mod       = CORE_MOD,
2287         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2288         .clkdm          = { .name = "core_l3_clkdm" },
2289         .enable_reg     = CM_FCLKEN1,
2290         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2291         .recalc         = &followparent_recalc,
2292 };
2293
2294 static struct clk mailboxes_ick = {
2295         .name           = "mailboxes_ick",
2296         .parent         = &l4_ck,
2297         .prcm_mod       = CORE_MOD,
2298         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2299         .clkdm          = { .name = "core_l4_clkdm" },
2300         .enable_reg     = CM_ICLKEN1,
2301         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2302         .idlest_bit     = OMAP24XX_ST_MAILBOXES_SHIFT,
2303         .recalc         = &followparent_recalc,
2304 };
2305
2306 static struct clk wdt4_ick = {
2307         .name           = "wdt4_ick",
2308         .parent         = &l4_ck,
2309         .prcm_mod       = CORE_MOD,
2310         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2311         .clkdm          = { .name = "core_l4_clkdm" },
2312         .enable_reg     = CM_ICLKEN1,
2313         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2314         .idlest_bit     = OMAP24XX_ST_WDT4_SHIFT,
2315         .recalc         = &followparent_recalc,
2316 };
2317
2318 static struct clk wdt4_fck = {
2319         .name           = "wdt4_fck",
2320         .parent         = &func_32k_ck,
2321         .prcm_mod       = CORE_MOD,
2322         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2323         .clkdm          = { .name = "core_l4_clkdm" },
2324         .enable_reg     = CM_FCLKEN1,
2325         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2326         .recalc         = &followparent_recalc,
2327 };
2328
2329 static struct clk wdt3_ick = {
2330         .name           = "wdt3_ick",
2331         .parent         = &l4_ck,
2332         .prcm_mod       = CORE_MOD,
2333         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2334         .clkdm          = { .name = "core_l4_clkdm" },
2335         .enable_reg     = CM_ICLKEN1,
2336         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2337         .idlest_bit     = OMAP2420_ST_WDT3_SHIFT,
2338         .recalc         = &followparent_recalc,
2339 };
2340
2341 static struct clk wdt3_fck = {
2342         .name           = "wdt3_fck",
2343         .parent         = &func_32k_ck,
2344         .prcm_mod       = CORE_MOD,
2345         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2346         .clkdm          = { .name = "core_l4_clkdm" },
2347         .enable_reg     = CM_FCLKEN1,
2348         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2349         .enable_bit     = OMAP2420_ST_WDT3_SHIFT,
2350         .recalc         = &followparent_recalc,
2351 };
2352
2353 static struct clk mspro_ick = {
2354         .name           = "mspro_ick",
2355         .parent         = &l4_ck,
2356         .prcm_mod       = CORE_MOD,
2357         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2358         .clkdm          = { .name = "core_l4_clkdm" },
2359         .enable_reg     = CM_ICLKEN1,
2360         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2361         .idlest_bit     = OMAP24XX_ST_MSPRO_SHIFT,
2362         .recalc         = &followparent_recalc,
2363 };
2364
2365 static struct clk mspro_fck = {
2366         .name           = "mspro_fck",
2367         .parent         = &func_96m_ck,
2368         .prcm_mod       = CORE_MOD,
2369         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2370         .clkdm          = { .name = "core_l4_clkdm" },
2371         .enable_reg     = CM_FCLKEN1,
2372         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2373         .idlest_bit     = OMAP24XX_ST_MSPRO_SHIFT,
2374         .recalc         = &followparent_recalc,
2375 };
2376
2377 static struct clk mmc_ick = {
2378         .name           = "mmc_ick",
2379         .parent         = &l4_ck,
2380         .prcm_mod       = CORE_MOD,
2381         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2382         .clkdm          = { .name = "core_l4_clkdm" },
2383         .enable_reg     = CM_ICLKEN1,
2384         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2385         .idlest_bit     = OMAP2420_ST_MMC_SHIFT,
2386         .recalc         = &followparent_recalc,
2387 };
2388
2389 static struct clk mmc_fck = {
2390         .name           = "mmc_fck",
2391         .parent         = &func_96m_ck,
2392         .prcm_mod       = CORE_MOD,
2393         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2394         .clkdm          = { .name = "core_l4_clkdm" },
2395         .enable_reg     = CM_FCLKEN1,
2396         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2397         .idlest_bit     = OMAP2420_ST_MMC_SHIFT,
2398         .recalc         = &followparent_recalc,
2399 };
2400
2401 static struct clk fac_ick = {
2402         .name           = "fac_ick",
2403         .parent         = &l4_ck,
2404         .prcm_mod       = CORE_MOD,
2405         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2406         .clkdm          = { .name = "core_l4_clkdm" },
2407         .enable_reg     = CM_ICLKEN1,
2408         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2409         .idlest_bit     = OMAP24XX_ST_FAC_SHIFT,
2410         .recalc         = &followparent_recalc,
2411 };
2412
2413 static struct clk fac_fck = {
2414         .name           = "fac_fck",
2415         .parent         = &func_12m_ck,
2416         .prcm_mod       = CORE_MOD,
2417         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2418         .clkdm          = { .name = "core_l4_clkdm" },
2419         .enable_reg     = CM_FCLKEN1,
2420         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2421         .idlest_bit     = OMAP24XX_ST_FAC_SHIFT,
2422         .recalc         = &followparent_recalc,
2423 };
2424
2425 static struct clk eac_ick = {
2426         .name           = "eac_ick",
2427         .parent         = &l4_ck,
2428         .prcm_mod       = CORE_MOD,
2429         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2430         .clkdm          = { .name = "core_l4_clkdm" },
2431         .enable_reg     = CM_ICLKEN1,
2432         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2433         .idlest_bit     = OMAP2420_ST_EAC_SHIFT,
2434         .recalc         = &followparent_recalc,
2435 };
2436
2437 static struct clk eac_fck = {
2438         .name           = "eac_fck",
2439         .parent         = &func_96m_ck,
2440         .prcm_mod       = CORE_MOD,
2441         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2442         .clkdm          = { .name = "core_l4_clkdm" },
2443         .enable_reg     = CM_FCLKEN1,
2444         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2445         .idlest_bit     = OMAP2420_ST_EAC_SHIFT,
2446         .recalc         = &followparent_recalc,
2447 };
2448
2449 static struct clk hdq_ick = {
2450         .name           = "hdq_ick",
2451         .parent         = &l4_ck,
2452         .prcm_mod       = CORE_MOD,
2453         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2454         .clkdm          = { .name = "core_l4_clkdm" },
2455         .enable_reg     = CM_ICLKEN1,
2456         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2457         .idlest_bit     = OMAP24XX_ST_HDQ_SHIFT,
2458         .recalc         = &followparent_recalc,
2459 };
2460
2461 static struct clk hdq_fck = {
2462         .name           = "hdq_fck",
2463         .parent         = &func_12m_ck,
2464         .prcm_mod       = CORE_MOD,
2465         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2466         .clkdm          = { .name = "core_l4_clkdm" },
2467         .enable_reg     = CM_FCLKEN1,
2468         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2469         .idlest_bit     = OMAP24XX_ST_HDQ_SHIFT,
2470         .recalc         = &followparent_recalc,
2471 };
2472
2473 static struct clk i2c2_ick = {
2474         .name           = "i2c_ick",
2475         .id             = 2,
2476         .parent         = &l4_ck,
2477         .prcm_mod       = CORE_MOD,
2478         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2479         .clkdm          = { .name = "core_l4_clkdm" },
2480         .enable_reg     = CM_ICLKEN1,
2481         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2482         .idlest_bit     = OMAP2420_ST_I2C2_SHIFT,
2483         .recalc         = &followparent_recalc,
2484 };
2485
2486 static struct clk i2c2_fck = {
2487         .name           = "i2c_fck",
2488         .id             = 2,
2489         .parent         = &func_12m_ck,
2490         .prcm_mod       = CORE_MOD,
2491         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2492         .clkdm          = { .name = "core_l4_clkdm" },
2493         .enable_reg     = CM_FCLKEN1,
2494         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2495         .idlest_bit     = OMAP2420_ST_I2C2_SHIFT,
2496         .recalc         = &followparent_recalc,
2497 };
2498
2499 static struct clk i2chs2_fck = {
2500         .name           = "i2c_fck",
2501         .id             = 2,
2502         .parent         = &func_96m_ck,
2503         .prcm_mod       = CORE_MOD,
2504         .flags          = CLOCK_IN_OMAP243X,
2505         .clkdm          = { .name = "core_l4_clkdm" },
2506         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2507         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2508         .recalc         = &followparent_recalc,
2509 };
2510
2511 static struct clk i2c1_ick = {
2512         .name           = "i2c_ick",
2513         .id             = 1,
2514         .parent         = &l4_ck,
2515         .prcm_mod       = CORE_MOD,
2516         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2517         .clkdm          = { .name = "core_l4_clkdm" },
2518         .enable_reg     = CM_ICLKEN1,
2519         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2520         .idlest_bit     = OMAP2420_ST_I2C1_SHIFT,
2521         .recalc         = &followparent_recalc,
2522 };
2523
2524 static struct clk i2c1_fck = {
2525         .name           = "i2c_fck",
2526         .id             = 1,
2527         .parent         = &func_12m_ck,
2528         .prcm_mod       = CORE_MOD,
2529         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2530         .clkdm          = { .name = "core_l4_clkdm" },
2531         .enable_reg     = CM_FCLKEN1,
2532         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2533         .idlest_bit     = OMAP2420_ST_I2C1_SHIFT,
2534         .recalc         = &followparent_recalc,
2535 };
2536
2537 static struct clk i2chs1_fck = {
2538         .name           = "i2c_fck",
2539         .id             = 1,
2540         .parent         = &func_96m_ck,
2541         .prcm_mod       = CORE_MOD,
2542         .flags          = CLOCK_IN_OMAP243X,
2543         .clkdm          = { .name = "core_l4_clkdm" },
2544         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2545         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2546         .recalc         = &followparent_recalc,
2547 };
2548
2549 static struct clk gpmc_fck = {
2550         .name           = "gpmc_fck",
2551         .parent         = &core_l3_ck,
2552         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2553                                 ENABLE_ON_INIT,
2554         .clkdm          = { .name = "core_l3_clkdm" },
2555         .recalc         = &followparent_recalc,
2556 };
2557
2558 static struct clk sdma_fck = {
2559         .name           = "sdma_fck",
2560         .parent         = &core_l3_ck,
2561         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2562         .clkdm          = { .name = "core_l3_clkdm" },
2563         .recalc         = &followparent_recalc,
2564 };
2565
2566 static struct clk sdma_ick = {
2567         .name           = "sdma_ick",
2568         .parent         = &l4_ck,
2569         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2570         .clkdm          = { .name = "core_l3_clkdm" },
2571         .recalc         = &followparent_recalc,
2572 };
2573
2574 static struct clk vlynq_ick = {
2575         .name           = "vlynq_ick",
2576         .parent         = &core_l3_ck,
2577         .prcm_mod       = CORE_MOD,
2578         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2579         .clkdm          = { .name = "core_l3_clkdm" },
2580         .enable_reg     = CM_ICLKEN1,
2581         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2582         .idlest_bit     = OMAP2420_ST_VLYNQ_SHIFT,
2583         .recalc         = &followparent_recalc,
2584 };
2585
2586 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2587         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2588         { .div = 0 }
2589 };
2590
2591 static const struct clksel_rate vlynq_fck_core_rates[] = {
2592         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2593         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2594         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2595         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2596         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2597         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2598         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2599         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2600         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2601         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2602         { .div = 0 }
2603 };
2604
2605 static const struct clksel vlynq_fck_clksel[] = {
2606         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2607         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2608         { .parent = NULL }
2609 };
2610
2611 static struct clk vlynq_fck = {
2612         .name           = "vlynq_fck",
2613         .parent         = &func_96m_ck,
2614         .prcm_mod       = CORE_MOD,
2615         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | WAIT_READY,
2616         .clkdm          = { .name = "core_l3_clkdm" },
2617         .enable_reg     = CM_FCLKEN1,
2618         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2619         .idlest_bit     = OMAP2420_ST_VLYNQ_SHIFT,
2620         .init           = &omap2_init_clksel_parent,
2621         .clksel_reg     = CM_CLKSEL1,
2622         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2623         .clksel         = vlynq_fck_clksel,
2624         .recalc         = &omap2_clksel_recalc,
2625         .round_rate     = &omap2_clksel_round_rate,
2626         .set_rate       = &omap2_clksel_set_rate
2627 };
2628
2629 static struct clk sdrc_ick = {
2630         .name           = "sdrc_ick",
2631         .parent         = &l4_ck,
2632         .prcm_mod       = CORE_MOD,
2633         .flags          = CLOCK_IN_OMAP243X | WAIT_READY | ENABLE_ON_INIT,
2634         .clkdm          = { .name = "core_l4_clkdm" },
2635         .enable_reg     = CM_ICLKEN3,
2636         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2637         .idlest_bit     = OMAP2430_ST_SDRC_SHIFT,
2638         .recalc         = &followparent_recalc,
2639 };
2640
2641 static struct clk des_ick = {
2642         .name           = "des_ick",
2643         .parent         = &l4_ck,
2644         .prcm_mod       = CORE_MOD,
2645         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2646         .clkdm          = { .name = "core_l4_clkdm" },
2647         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2648         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2649         .idlest_bit     = OMAP24XX_ST_DES_SHIFT,
2650         .recalc         = &followparent_recalc,
2651 };
2652
2653 static struct clk sha_ick = {
2654         .name           = "sha_ick",
2655         .parent         = &l4_ck,
2656         .prcm_mod       = CORE_MOD,
2657         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2658         .clkdm          = { .name = "core_l4_clkdm" },
2659         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2660         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2661         .idlest_bit     = OMAP24XX_ST_SHA_SHIFT,
2662         .recalc         = &followparent_recalc,
2663 };
2664
2665 static struct clk rng_ick = {
2666         .name           = "rng_ick",
2667         .parent         = &l4_ck,
2668         .prcm_mod       = CORE_MOD,
2669         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2670         .clkdm          = { .name = "core_l4_clkdm" },
2671         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2672         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2673         .idlest_bit     = OMAP24XX_ST_RNG_SHIFT,
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static struct clk aes_ick = {
2678         .name           = "aes_ick",
2679         .parent         = &l4_ck,
2680         .prcm_mod       = CORE_MOD,
2681         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2682         .clkdm          = { .name = "core_l4_clkdm" },
2683         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2684         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2685         .idlest_bit     = OMAP24XX_ST_AES_SHIFT,
2686         .recalc         = &followparent_recalc,
2687 };
2688
2689 static struct clk pka_ick = {
2690         .name           = "pka_ick",
2691         .parent         = &l4_ck,
2692         .prcm_mod       = CORE_MOD,
2693         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2694         .clkdm          = { .name = "core_l4_clkdm" },
2695         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2696         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2697         .idlest_bit     = OMAP24XX_ST_PKA_SHIFT,
2698         .recalc         = &followparent_recalc,
2699 };
2700
2701 static struct clk usb_fck = {
2702         .name           = "usb_fck",
2703         .parent         = &func_48m_ck,
2704         .prcm_mod       = CORE_MOD,
2705         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2706         .clkdm          = { .name = "core_l3_clkdm" },
2707         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2708         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2709         .idlest_bit     = OMAP24XX_ST_USB_SHIFT,
2710         .recalc         = &followparent_recalc,
2711 };
2712
2713 static struct clk usbhs_ick = {
2714         .name           = "usbhs_ick",
2715         .parent         = &core_l3_ck,
2716         .prcm_mod       = CORE_MOD,
2717         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2718         .clkdm          = { .name = "core_l3_clkdm" },
2719         .enable_reg     = CM_ICLKEN2,
2720         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2721         .idlest_bit     = OMAP2430_ST_USBHS_SHIFT,
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk mmchs1_ick = {
2726         .name           = "mmchs_ick",
2727         .parent         = &l4_ck,
2728         .prcm_mod       = CORE_MOD,
2729         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2730         .clkdm          = { .name = "core_l4_clkdm" },
2731         .enable_reg     = CM_ICLKEN2,
2732         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2733         .idlest_bit     = OMAP2430_ST_MMCHS1_SHIFT,
2734         .recalc         = &followparent_recalc,
2735 };
2736
2737 static struct clk mmchs1_fck = {
2738         .name           = "mmchs_fck",
2739         .parent         = &func_96m_ck,
2740         .prcm_mod       = CORE_MOD,
2741         .flags          = CLOCK_IN_OMAP243X,
2742         .clkdm          = { .name = "core_l3_clkdm" },
2743         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2744         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2745         .recalc         = &followparent_recalc,
2746 };
2747
2748 static struct clk mmchs2_ick = {
2749         .name           = "mmchs_ick",
2750         .id             = 1,
2751         .parent         = &l4_ck,
2752         .prcm_mod       = CORE_MOD,
2753         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2754         .clkdm          = { .name = "core_l4_clkdm" },
2755         .enable_reg     = CM_ICLKEN2,
2756         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2757         .idlest_bit     = OMAP2430_ST_MMCHS2_SHIFT,
2758         .recalc         = &followparent_recalc,
2759 };
2760
2761 static struct clk mmchs2_fck = {
2762         .name           = "mmchs_fck",
2763         .id             = 1,
2764         .parent         = &func_96m_ck,
2765         .prcm_mod       = CORE_MOD,
2766         .flags          = CLOCK_IN_OMAP243X,
2767         .clkdm          = { .name = "core_l4_clkdm" },
2768         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2769         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2770         .recalc         = &followparent_recalc,
2771 };
2772
2773 static struct clk gpio5_ick = {
2774         .name           = "gpio5_ick",
2775         .parent         = &l4_ck,
2776         .prcm_mod       = CORE_MOD,
2777         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2778         .clkdm          = { .name = "core_l4_clkdm" },
2779         .enable_reg     = CM_ICLKEN2,
2780         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2781         .idlest_bit     = OMAP2430_ST_GPIO5_SHIFT,
2782         .recalc         = &followparent_recalc,
2783 };
2784
2785 static struct clk gpio5_fck = {
2786         .name           = "gpio5_fck",
2787         .parent         = &func_32k_ck,
2788         .prcm_mod       = CORE_MOD,
2789         .flags          = CLOCK_IN_OMAP243X,
2790         .clkdm          = { .name = "core_l4_clkdm" },
2791         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2792         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2793         .recalc         = &followparent_recalc,
2794 };
2795
2796 static struct clk mdm_intc_ick = {
2797         .name           = "mdm_intc_ick",
2798         .parent         = &l4_ck,
2799         .prcm_mod       = CORE_MOD,
2800         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2801         .clkdm          = { .name = "core_l4_clkdm" },
2802         .enable_reg     = CM_ICLKEN2,
2803         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2804         .idlest_bit     = OMAP2430_ST_MDM_INTC_SHIFT,
2805         .recalc         = &followparent_recalc,
2806 };
2807
2808 static struct clk mmchsdb1_fck = {
2809         .name           = "mmchsdb_fck",
2810         .parent         = &func_32k_ck,
2811         .prcm_mod       = CORE_MOD,
2812         .flags          = CLOCK_IN_OMAP243X,
2813         .clkdm          = { .name = "core_l4_clkdm" },
2814         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2815         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2816         .recalc         = &followparent_recalc,
2817 };
2818
2819 static struct clk mmchsdb2_fck = {
2820         .name           = "mmchsdb_fck",
2821         .id             = 1,
2822         .parent         = &func_32k_ck,
2823         .prcm_mod       = CORE_MOD,
2824         .flags          = CLOCK_IN_OMAP243X,
2825         .clkdm          = { .name = "core_l4_clkdm" },
2826         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2827         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2828         .recalc         = &followparent_recalc,
2829 };
2830
2831 /*
2832  * This clock is a composite clock which does entire set changes then
2833  * forces a rebalance. It keys on the MPU speed, but it really could
2834  * be any key speed part of a set in the rate table.
2835  *
2836  * to really change a set, you need memory table sets which get changed
2837  * in sram, pre-notifiers & post notifiers, changing the top set, without
2838  * having low level display recalc's won't work... this is why dpm notifiers
2839  * work, isr's off, walk a list of clocks already _off_ and not messing with
2840  * the bus.
2841  *
2842  * This clock should have no parent. It embodies the entire upper level
2843  * active set. A parent will mess up some of the init also.
2844  */
2845 static struct clk virt_prcm_set = {
2846         .name           = "virt_prcm_set",
2847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2848                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2849         .clkdm          = { .name = "virt_opp_clkdm" },
2850         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2851         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2852         .set_rate       = &omap2_select_table_rate,
2853         .round_rate     = &omap2_round_to_table_rate,
2854 };
2855
2856 static struct clk *onchip_24xx_clks[] __initdata = {
2857         /* external root sources */
2858         &func_32k_ck,
2859         &osc_ck,
2860         &sys_ck,
2861         &alt_ck,
2862         /* internal analog sources */
2863         &dpll_ck,
2864         &apll96_ck,
2865         &apll54_ck,
2866         /* internal prcm root sources */
2867         &func_54m_ck,
2868         &core_ck,
2869         &func_96m_ck,
2870         &func_48m_ck,
2871         &func_12m_ck,
2872         &wdt1_osc_ck,
2873         &sys_clkout_src,
2874         &sys_clkout,
2875         &sys_clkout2_src,
2876         &sys_clkout2,
2877         &emul_ck,
2878         /* mpu domain clocks */
2879         &mpu_ck,
2880         /* dsp domain clocks */
2881         &dsp_fck,
2882         &dsp_irate_ick,
2883         &dsp_ick,               /* 242x */
2884         &iva2_1_ick,            /* 243x */
2885         &iva1_ifck,             /* 242x */
2886         &iva1_mpu_int_ifck,     /* 242x */
2887         /* GFX domain clocks */
2888         &gfx_3d_fck,
2889         &gfx_2d_fck,
2890         &gfx_ick,
2891         /* Modem domain clocks */
2892         &mdm_ick,
2893         &mdm_osc_ck,
2894         /* DSS domain clocks */
2895         &dss_ick,
2896         &dss1_fck,
2897         &dss2_fck,
2898         &dss_54m_fck,
2899         /* L3 domain clocks */
2900         &core_l3_ck,
2901         &ssi_ssr_sst_fck,
2902         &usb_l4_ick,
2903         /* L4 domain clocks */
2904         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2905         &ssi_l4_ick,
2906         /* virtual meta-group clock */
2907         &virt_prcm_set,
2908         /* general l4 interface ck, multi-parent functional clk */
2909         &gpt1_ick,
2910         &gpt1_fck,
2911         &gpt2_ick,
2912         &gpt2_fck,
2913         &gpt3_ick,
2914         &gpt3_fck,
2915         &gpt4_ick,
2916         &gpt4_fck,
2917         &gpt5_ick,
2918         &gpt5_fck,
2919         &gpt6_ick,
2920         &gpt6_fck,
2921         &gpt7_ick,
2922         &gpt7_fck,
2923         &gpt8_ick,
2924         &gpt8_fck,
2925         &gpt9_ick,
2926         &gpt9_fck,
2927         &gpt10_ick,
2928         &gpt10_fck,
2929         &gpt11_ick,
2930         &gpt11_fck,
2931         &gpt12_ick,
2932         &gpt12_fck,
2933         &mcbsp1_ick,
2934         &mcbsp1_fck,
2935         &mcbsp2_ick,
2936         &mcbsp2_fck,
2937         &mcbsp3_ick,
2938         &mcbsp3_fck,
2939         &mcbsp4_ick,
2940         &mcbsp4_fck,
2941         &mcbsp5_ick,
2942         &mcbsp5_fck,
2943         &mcspi1_ick,
2944         &mcspi1_fck,
2945         &mcspi2_ick,
2946         &mcspi2_fck,
2947         &mcspi3_ick,
2948         &mcspi3_fck,
2949         &uart1_ick,
2950         &uart1_fck,
2951         &uart2_ick,
2952         &uart2_fck,
2953         &uart3_ick,
2954         &uart3_fck,
2955         &gpios_ick,
2956         &gpios_fck,
2957         &mpu_wdt_ick,
2958         &mpu_wdt_fck,
2959         &sync_32k_ick,
2960         &wdt1_ick,
2961         &omapctrl_ick,
2962         &icr_ick,
2963         &cam_fck,
2964         &cam_ick,
2965         &mailboxes_ick,
2966         &wdt4_ick,
2967         &wdt4_fck,
2968         &wdt3_ick,
2969         &wdt3_fck,
2970         &mspro_ick,
2971         &mspro_fck,
2972         &mmc_ick,
2973         &mmc_fck,
2974         &fac_ick,
2975         &fac_fck,
2976         &eac_ick,
2977         &eac_fck,
2978         &hdq_ick,
2979         &hdq_fck,
2980         &i2c1_ick,
2981         &i2c1_fck,
2982         &i2chs1_fck,
2983         &i2c2_ick,
2984         &i2c2_fck,
2985         &i2chs2_fck,
2986         &gpmc_fck,
2987         &sdma_fck,
2988         &sdma_ick,
2989         &vlynq_ick,
2990         &vlynq_fck,
2991         &sdrc_ick,
2992         &des_ick,
2993         &sha_ick,
2994         &rng_ick,
2995         &aes_ick,
2996         &pka_ick,
2997         &usb_fck,
2998         &usbhs_ick,
2999         &mmchs1_ick,
3000         &mmchs1_fck,
3001         &mmchs2_ick,
3002         &mmchs2_fck,
3003         &gpio5_ick,
3004         &gpio5_fck,
3005         &mdm_intc_ick,
3006         &mmchsdb1_fck,
3007         &mmchsdb2_fck,
3008 };
3009
3010 #endif
3011