arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk, unsigned long parent_rate,
  28                                    u8 rate_storage);
  29 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  30 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  31 static void omap2_sys_clk_recalc(struct clk *clk, unsigned long parent_rate,
  32                                  u8 rate_storage);
  33 static void omap2_osc_clk_recalc(struct clk *clk, unsigned long parent_rate,
  34                                  u8 rate_storage);
  35 static void omap2_dpllcore_recalc(struct clk *clk, unsigned long parent_rate,
  36                                  u8 rate_storage);
  37 static int omap2_clk_fixed_enable(struct clk *clk);
  38 static void omap2_clk_fixed_disable(struct clk *clk);
  39 static int omap2_enable_osc_ck(struct clk *clk);
  40 static void omap2_disable_osc_ck(struct clk *clk);
  41 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  42
  43 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  44  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  45  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  46  */
  47 struct prcm_config {
  48         unsigned long xtal_speed;       /* crystal rate */
  49         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  50         unsigned long mpu_speed;        /* speed of MPU */
  51         unsigned long cm_clksel_mpu;    /* mpu divider */
  52         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  53         unsigned long cm_clksel_gfx;    /* gfx dividers */
  54         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  55         unsigned long cm_clksel1_pll;   /* m,n */
  56         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  57         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  58         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  59         unsigned char flags;
  60 };
  61
  62 /*
  63  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  64  * These configurations are characterized by voltage and speed for clocks.
  65  * The device is only validated for certain combinations. One way to express
  66  * these combinations is via the 'ratio's' which the clocks operate with
  67  * respect to each other. These ratio sets are for a given voltage/DPLL
  68  * setting. All configurations can be described by a DPLL setting and a ratio
  69  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  70  *
  71  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  72  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  73  * 2430 (iva2.1, NOdsp, mdm)
  74  */
  75
  76 /* Core fields for cm_clksel, not ratio governed */
  77 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  78 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  79 #define RX_CLKSEL_SSI                   (0x5 << 20)
  80
  81 /*-------------------------------------------------------------------------
  82  * Voltage/DPLL ratios
  83  *-------------------------------------------------------------------------*/
  84
  85 /* 2430 Ratio's, 2430-Ratio Config 1 */
  86 #define R1_CLKSEL_L3                    (4 << 0)
  87 #define R1_CLKSEL_L4                    (2 << 5)
  88 #define R1_CLKSEL_USB                   (4 << 25)
  89 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  90                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  91                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  92 #define R1_CLKSEL_MPU                   (2 << 0)
  93 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  94 #define R1_CLKSEL_DSP                   (2 << 0)
  95 #define R1_CLKSEL_DSP_IF                (2 << 5)
  96 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  97 #define R1_CLKSEL_GFX                   (2 << 0)
  98 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  99 #define R1_CLKSEL_MDM                   (4 << 0)
 100 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 101
 102 /* 2430-Ratio Config 2 */
 103 #define R2_CLKSEL_L3                    (6 << 0)
 104 #define R2_CLKSEL_L4                    (2 << 5)
 105 #define R2_CLKSEL_USB                   (2 << 25)
 106 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 107                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 108                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 109 #define R2_CLKSEL_MPU                   (2 << 0)
 110 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 111 #define R2_CLKSEL_DSP                   (2 << 0)
 112 #define R2_CLKSEL_DSP_IF                (3 << 5)
 113 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 114 #define R2_CLKSEL_GFX                   (2 << 0)
 115 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 116 #define R2_CLKSEL_MDM                   (6 << 0)
 117 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 118
 119 /* 2430-Ratio Bootm (BYPASS) */
 120 #define RB_CLKSEL_L3                    (1 << 0)
 121 #define RB_CLKSEL_L4                    (1 << 5)
 122 #define RB_CLKSEL_USB                   (1 << 25)
 123 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 124                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 125                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 126 #define RB_CLKSEL_MPU                   (1 << 0)
 127 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 128 #define RB_CLKSEL_DSP                   (1 << 0)
 129 #define RB_CLKSEL_DSP_IF                (1 << 5)
 130 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 131 #define RB_CLKSEL_GFX                   (1 << 0)
 132 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 133 #define RB_CLKSEL_MDM                   (1 << 0)
 134 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 135
 136 /* 2420 Ratio Equivalents */
 137 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 138 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 139
 140 /* 2420-PRCM III 532MHz core */
 141 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 142 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 143 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 144 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 145                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 146                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 147                                         RIII_CLKSEL_L3
 148 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 149 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 150 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 151 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 152 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 153 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 154 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 155 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 156                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 157                                         RIII_CLKSEL_DSP
 158 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 159 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 160
 161 /* 2420-PRCM II 600MHz core */
 162 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 163 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 164 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 165 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 166                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 167                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 168                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 169 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 170 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 171 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 172 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 173 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 174 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 175 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 176 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 177                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 178                                         RII_CLKSEL_DSP
 179 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 180 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 181
 182 /* 2420-PRCM I 660MHz core */
 183 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 184 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 185 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 186 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 187                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 188                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 189                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 190 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 191 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 192 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 193 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 194 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 195 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 196 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 197 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 198                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 199                                         RI_CLKSEL_DSP
 200 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 201 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 202
 203 /* 2420-PRCM VII (boot) */
 204 #define RVII_CLKSEL_L3                  (1 << 0)
 205 #define RVII_CLKSEL_L4                  (1 << 5)
 206 #define RVII_CLKSEL_DSS1                (1 << 8)
 207 #define RVII_CLKSEL_DSS2                (0 << 13)
 208 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 209 #define RVII_CLKSEL_SSI                 (1 << 20)
 210 #define RVII_CLKSEL_USB                 (1 << 25)
 211
 212 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 213                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 214                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 215
 216 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 217 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 218
 219 #define RVII_CLKSEL_DSP                 (1 << 0)
 220 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 221 #define RVII_SYNC_DSP                   (0 << 7)
 222 #define RVII_CLKSEL_IVA                 (1 << 8)
 223 #define RVII_SYNC_IVA                   (0 << 13)
 224 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 225                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 226
 227 #define RVII_CLKSEL_GFX                 (1 << 0)
 228 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 229
 230 /*-------------------------------------------------------------------------
 231  * 2430 Target modes: Along with each configuration the CPU has several
 232  * modes which goes along with them. Modes mainly are the addition of
 233  * describe DPLL combinations to go along with a ratio.
 234  *-------------------------------------------------------------------------*/
 235
 236 /* Hardware governed */
 237 #define MX_48M_SRC                      (0 << 3)
 238 #define MX_54M_SRC                      (0 << 5)
 239 #define MX_APLLS_CLIKIN_12              (3 << 23)
 240 #define MX_APLLS_CLIKIN_13              (2 << 23)
 241 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 242
 243 /*
 244  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 245  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 246  */
 247 #define M5A_DPLL_MULT_12                (133 << 12)
 248 #define M5A_DPLL_DIV_12                 (5 << 8)
 249 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 250                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 251                                         MX_APLLS_CLIKIN_12
 252 #define M5A_DPLL_MULT_13                (61 << 12)
 253 #define M5A_DPLL_DIV_13                 (2 << 8)
 254 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 255                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 256                                         MX_APLLS_CLIKIN_13
 257 #define M5A_DPLL_MULT_19                (55 << 12)
 258 #define M5A_DPLL_DIV_19                 (3 << 8)
 259 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 260                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 261                                         MX_APLLS_CLIKIN_19_2
 262 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 263 #define M5B_DPLL_MULT_12                (50 << 12)
 264 #define M5B_DPLL_DIV_12                 (2 << 8)
 265 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 266                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 267                                         MX_APLLS_CLIKIN_12
 268 #define M5B_DPLL_MULT_13                (200 << 12)
 269 #define M5B_DPLL_DIV_13                 (12 << 8)
 270
 271 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 272                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 273                                         MX_APLLS_CLIKIN_13
 274 #define M5B_DPLL_MULT_19                (125 << 12)
 275 #define M5B_DPLL_DIV_19                 (31 << 8)
 276 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 277                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 278                                         MX_APLLS_CLIKIN_19_2
 279 /*
 280  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 281  */
 282 #define M4_DPLL_MULT_12                 (133 << 12)
 283 #define M4_DPLL_DIV_12                  (3 << 8)
 284 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 285                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 286                                         MX_APLLS_CLIKIN_12
 287
 288 #define M4_DPLL_MULT_13                 (399 << 12)
 289 #define M4_DPLL_DIV_13                  (12 << 8)
 290 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 291                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 292                                         MX_APLLS_CLIKIN_13
 293
 294 #define M4_DPLL_MULT_19                 (145 << 12)
 295 #define M4_DPLL_DIV_19                  (6 << 8)
 296 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 297                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 298                                         MX_APLLS_CLIKIN_19_2
 299
 300 /*
 301  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 302  */
 303 #define M3_DPLL_MULT_12                 (55 << 12)
 304 #define M3_DPLL_DIV_12                  (1 << 8)
 305 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 306                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 307                                         MX_APLLS_CLIKIN_12
 308 #define M3_DPLL_MULT_13                 (76 << 12)
 309 #define M3_DPLL_DIV_13                  (2 << 8)
 310 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 311                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 312                                         MX_APLLS_CLIKIN_13
 313 #define M3_DPLL_MULT_19                 (17 << 12)
 314 #define M3_DPLL_DIV_19                  (0 << 8)
 315 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 316                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 317                                         MX_APLLS_CLIKIN_19_2
 318
 319 /*
 320  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 321  */
 322 #define M2_DPLL_MULT_12                 (55 << 12)
 323 #define M2_DPLL_DIV_12                  (1 << 8)
 324 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 325                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 326                                         MX_APLLS_CLIKIN_12
 327
 328 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 329  * relock time issue */
 330 /* Core frequency changed from 330/165 to 329/164 MHz*/
 331 #define M2_DPLL_MULT_13                 (76 << 12)
 332 #define M2_DPLL_DIV_13                  (2 << 8)
 333 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 334                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 335                                         MX_APLLS_CLIKIN_13
 336
 337 #define M2_DPLL_MULT_19                 (17 << 12)
 338 #define M2_DPLL_DIV_19                  (0 << 8)
 339 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 340                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 341                                         MX_APLLS_CLIKIN_19_2
 342
 343 /* boot (boot) */
 344 #define MB_DPLL_MULT                    (1 << 12)
 345 #define MB_DPLL_DIV                     (0 << 8)
 346 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 348
 349 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 351
 352 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 353                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 354
 355 /*
 356  * 2430 - chassis (sedna)
 357  * 165 (ratio1) same as above #2
 358  * 150 (ratio1)
 359  * 133 (ratio2) same as above #4
 360  * 110 (ratio2) same as above #3
 361  * 104 (ratio2)
 362  * boot (boot)
 363  */
 364
 365 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 366 #define MI_DPLL_MULT_12                 (55 << 12)
 367 #define MI_DPLL_DIV_12                  (1 << 8)
 368 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 369                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 370                                         MX_APLLS_CLIKIN_12
 371
 372 /*
 373  * 2420 Equivalent - mode registers
 374  * PRCM II , target DPLL = 2*300MHz = 600MHz
 375  */
 376 #define MII_DPLL_MULT_12                (50 << 12)
 377 #define MII_DPLL_DIV_12                 (1 << 8)
 378 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 379                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 380                                         MX_APLLS_CLIKIN_12
 381 #define MII_DPLL_MULT_13                (300 << 12)
 382 #define MII_DPLL_DIV_13                 (12 << 8)
 383 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 384                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 385                                         MX_APLLS_CLIKIN_13
 386
 387 /* PRCM III target DPLL = 2*266 = 532MHz*/
 388 #define MIII_DPLL_MULT_12               (133 << 12)
 389 #define MIII_DPLL_DIV_12                (5 << 8)
 390 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 391                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 392                                         MX_APLLS_CLIKIN_12
 393 #define MIII_DPLL_MULT_13               (266 << 12)
 394 #define MIII_DPLL_DIV_13                (12 << 8)
 395 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 396                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 397                                         MX_APLLS_CLIKIN_13
 398
 399 /* PRCM VII (boot bypass) */
 400 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 401 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 402
 403 /* High and low operation value */
 404 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 405 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 406
 407 /* MPU speed defines */
 408 #define S12M    12000000
 409 #define S13M    13000000
 410 #define S19M    19200000
 411 #define S26M    26000000
 412 #define S100M   100000000
 413 #define S133M   133000000
 414 #define S150M   150000000
 415 #define S164M   164000000
 416 #define S165M   165000000
 417 #define S199M   199000000
 418 #define S200M   200000000
 419 #define S266M   266000000
 420 #define S300M   300000000
 421 #define S329M   329000000
 422 #define S330M   330000000
 423 #define S399M   399000000
 424 #define S400M   400000000
 425 #define S532M   532000000
 426 #define S600M   600000000
 427 #define S658M   658000000
 428 #define S660M   660000000
 429 #define S798M   798000000
 430
 431 /*-------------------------------------------------------------------------
 432  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 433  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 434  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 435  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 436  *
 437  * Filling in table based on H4 boards and 2430-SDPs variants available.
 438  * There are quite a few more rates combinations which could be defined.
 439  *
 440  * When multiple values are defined the start up will try and choose the
 441  * fastest one. If a 'fast' value is defined, then automatically, the /2
 442  * one should be included as it can be used.    Generally having more that
 443  * one fast set does not make sense, as static timings need to be changed
 444  * to change the set.    The exception is the bypass setting which is
 445  * availble for low power bypass.
 446  *
 447  * Note: This table needs to be sorted, fastest to slowest.
 448  *-------------------------------------------------------------------------*/
 449 static struct prcm_config rate_table[] = {
 450         /* PRCM I - FAST */
 451         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 452                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 453                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 454                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 455                 RATE_IN_242X},
 456
 457         /* PRCM II - FAST */
 458         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 459                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 460                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 461                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 462                 RATE_IN_242X},
 463
 464         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 465                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 466                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 467                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 468                 RATE_IN_242X},
 469
 470         /* PRCM III - FAST */
 471         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 472                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 473                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 474                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 475                 RATE_IN_242X},
 476
 477         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 478                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 479                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 480                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 481                 RATE_IN_242X},
 482
 483         /* PRCM II - SLOW */
 484         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 485                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 486                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 487                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 488                 RATE_IN_242X},
 489
 490         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 491                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 492                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 493                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 494                 RATE_IN_242X},
 495
 496         /* PRCM III - SLOW */
 497         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 498                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 499                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 500                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 501                 RATE_IN_242X},
 502
 503         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 504                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 505                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 506                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 507                 RATE_IN_242X},
 508
 509         /* PRCM-VII (boot-bypass) */
 510         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 511                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 512                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 513                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 514                 RATE_IN_242X},
 515
 516         /* PRCM-VII (boot-bypass) */
 517         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 518                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 519                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 520                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 521                 RATE_IN_242X},
 522
 523         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 524         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 525                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 526                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 527                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 528                 SDRC_RFR_CTRL_133MHz,
 529                 RATE_IN_243X},
 530
 531         /* PRCM #2 - ratio1 (ES2) - FAST */
 532         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 533                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 534                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 535                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 536                 SDRC_RFR_CTRL_165MHz,
 537                 RATE_IN_243X},
 538
 539         /* PRCM #5a - ratio1 - FAST */
 540         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 541                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 542                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 543                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 544                 SDRC_RFR_CTRL_133MHz,
 545                 RATE_IN_243X},
 546
 547         /* PRCM #5b - ratio1 - FAST */
 548         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 549                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 550                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 551                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 552                 SDRC_RFR_CTRL_100MHz,
 553                 RATE_IN_243X},
 554
 555         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 556         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 557                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 558                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 559                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 560                 SDRC_RFR_CTRL_133MHz,
 561                 RATE_IN_243X},
 562
 563         /* PRCM #2 - ratio1 (ES2) - SLOW */
 564         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 565                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 566                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 567                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 568                 SDRC_RFR_CTRL_165MHz,
 569                 RATE_IN_243X},
 570
 571         /* PRCM #5a - ratio1 - SLOW */
 572         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 573                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 574                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 575                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 576                 SDRC_RFR_CTRL_133MHz,
 577                 RATE_IN_243X},
 578
 579         /* PRCM #5b - ratio1 - SLOW*/
 580         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 581                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 582                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 583                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 584                 SDRC_RFR_CTRL_100MHz,
 585                 RATE_IN_243X},
 586
 587         /* PRCM-boot/bypass */
 588         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 589                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 590                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 591                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 592                 SDRC_RFR_CTRL_BYPASS,
 593                 RATE_IN_243X},
 594
 595         /* PRCM-boot/bypass */
 596         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 597                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 598                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 599                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 600                 SDRC_RFR_CTRL_BYPASS,
 601                 RATE_IN_243X},
 602
 603         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 604 };
 605
 606 /*-------------------------------------------------------------------------
 607  * 24xx clock tree.
 608  *
 609  * NOTE:In many cases here we are assigning a 'default' parent. In many
 610  *      cases the parent is selectable. The get/set parent calls will also
 611  *      switch sources.
 612  *
 613  *      Many some clocks say always_enabled, but they can be auto idled for
 614  *      power savings. They will always be available upon clock request.
 615  *
 616  *      Several sources are given initial rates which may be wrong, this will
 617  *      be fixed up in the init func.
 618  *
 619  *      Things are broadly separated below by clock domains. It is
 620  *      noteworthy that most periferals have dependencies on multiple clock
 621  *      domains. Many get their interface clocks from the L4 domain, but get
 622  *      functional clocks from fixed sources or other core domain derived
 623  *      clocks.
 624  *-------------------------------------------------------------------------*/
 625
 626 /* Base external input clocks */
 627 static struct clk func_32k_ck = {
 628         .name           = "func_32k_ck",
 629         .rate           = 32000,
 630         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 631                                 ALWAYS_ENABLED,
 632         .clkdm          = { .name = "prm_clkdm" },
 633 };
 634
 635 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 636 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 637         .name           = "osc_ck",
 638         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 639         .clkdm          = { .name = "prm_clkdm" },
 640         .enable         = &omap2_enable_osc_ck,
 641         .disable        = &omap2_disable_osc_ck,
 642         .recalc         = &omap2_osc_clk_recalc,
 643 };
 644
 645 /* Without modem likely 12MHz, with modem likely 13MHz */
 646 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 647         .name           = "sys_ck",             /* ~ ref_clk also */
 648         .parent         = &osc_ck,
 649         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 650                                 ALWAYS_ENABLED,
 651         .clkdm          = { .name = "prm_clkdm" },
 652         .recalc         = &omap2_sys_clk_recalc,
 653 };
 654
 655 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 656         .name           = "alt_ck",
 657         .rate           = 54000000,
 658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 659                                 ALWAYS_ENABLED,
 660         .clkdm          = { .name = "prm_clkdm" },
 661 };
 662
 663 /*
 664  * Analog domain root source clocks
 665  */
 666
 667 /* dpll_ck, is broken out in to special cases through clksel */
 668 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 669  * deal with this
 670  */
 671
 672 static struct dpll_data dpll_dd = {
 673         .mult_div1_reg          = CM_CLKSEL1,
 674         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 675         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 676         .control_reg            = CM_CLKEN,
 677         .enable_mask            = OMAP24XX_EN_DPLL_MASK,
 678         .max_multiplier         = 1024,
 679         .min_divider            = 1,
 680         .max_divider            = 16,
 681         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 682 };
 683
 684 /*
 685  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 686  * not just a DPLL
 687  */
 688 static struct clk dpll_ck = {
 689         .name           = "dpll_ck",
 690         .parent         = &sys_ck,              /* Can be func_32k also */
 691         .prcm_mod       = PLL_MOD,
 692         .dpll_data      = &dpll_dd,
 693         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 694                                 ALWAYS_ENABLED,
 695         .clkdm          = { .name = "prm_clkdm" },
 696         .recalc         = &omap2_dpllcore_recalc,
 697         .set_rate       = &omap2_reprogram_dpllcore,
 698 };
 699
 700 static struct clk apll96_ck = {
 701         .name           = "apll96_ck",
 702         .parent         = &sys_ck,
 703         .prcm_mod       = PLL_MOD,
 704         .rate           = 96000000,
 705         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 706                                 ENABLE_ON_INIT,
 707         .clkdm          = { .name = "prm_clkdm" },
 708         .enable_reg     = CM_CLKEN,
 709         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 710         .enable         = &omap2_clk_fixed_enable,
 711         .disable        = &omap2_clk_fixed_disable,
 712 };
 713
 714 static struct clk apll54_ck = {
 715         .name           = "apll54_ck",
 716         .parent         = &sys_ck,
 717         .prcm_mod       = PLL_MOD,
 718         .rate           = 54000000,
 719         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 720                                 ENABLE_ON_INIT,
 721         .clkdm          = { .name = "prm_clkdm" },
 722         .enable_reg     = CM_CLKEN,
 723         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 724         .enable         = &omap2_clk_fixed_enable,
 725         .disable        = &omap2_clk_fixed_disable,
 726 };
 727
 728 /*
 729  * PRCM digital base sources
 730  */
 731
 732 /* func_54m_ck */
 733
 734 static const struct clksel_rate func_54m_apll54_rates[] = {
 735         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 736         { .div = 0 },
 737 };
 738
 739 static const struct clksel_rate func_54m_alt_rates[] = {
 740         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 741         { .div = 0 },
 742 };
 743
 744 static const struct clksel func_54m_clksel[] = {
 745         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 746         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 747         { .parent = NULL },
 748 };
 749
 750 static struct clk func_54m_ck = {
 751         .name           = "func_54m_ck",
 752         .parent         = &apll54_ck,   /* can also be alt_clk */
 753         .prcm_mod       = PLL_MOD,
 754         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 755                                 PARENT_CONTROLS_CLOCK,
 756         .clkdm          = { .name = "cm_clkdm" },
 757         .init           = &omap2_init_clksel_parent,
 758         .clksel_reg     = CM_CLKSEL1,
 759         .clksel_mask    = OMAP24XX_54M_SOURCE,
 760         .clksel         = func_54m_clksel,
 761         .recalc         = &omap2_clksel_recalc,
 762 };
 763
 764 static struct clk core_ck = {
 765         .name           = "core_ck",
 766         .parent         = &dpll_ck,             /* can also be 32k */
 767         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 768                                 ALWAYS_ENABLED,
 769         .clkdm          = { .name = "cm_clkdm" },
 770         .recalc         = &followparent_recalc,
 771 };
 772
 773 /* func_96m_ck */
 774 static const struct clksel_rate func_96m_apll96_rates[] = {
 775         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 776         { .div = 0 },
 777 };
 778
 779 static const struct clksel_rate func_96m_alt_rates[] = {
 780         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 781         { .div = 0 },
 782 };
 783
 784 static const struct clksel func_96m_clksel[] = {
 785         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 786         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 787         { .parent = NULL }
 788 };
 789
 790 /* The parent of this clock is not selectable on 2420. */
 791 static struct clk func_96m_ck = {
 792         .name           = "func_96m_ck",
 793         .parent         = &apll96_ck,
 794         .prcm_mod       = PLL_MOD,
 795         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 796                                 PARENT_CONTROLS_CLOCK,
 797         .clkdm          = { .name = "cm_clkdm" },
 798         .init           = &omap2_init_clksel_parent,
 799         .clksel_reg     = CM_CLKSEL1,
 800         .clksel_mask    = OMAP2430_96M_SOURCE,
 801         .clksel         = func_96m_clksel,
 802         .recalc         = &omap2_clksel_recalc,
 803         .round_rate     = &omap2_clksel_round_rate,
 804         .set_rate       = &omap2_clksel_set_rate
 805 };
 806
 807 /* func_48m_ck */
 808
 809 static const struct clksel_rate func_48m_apll96_rates[] = {
 810         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 811         { .div = 0 },
 812 };
 813
 814 static const struct clksel_rate func_48m_alt_rates[] = {
 815         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 816         { .div = 0 },
 817 };
 818
 819 static const struct clksel func_48m_clksel[] = {
 820         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 821         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 822         { .parent = NULL }
 823 };
 824
 825 static struct clk func_48m_ck = {
 826         .name           = "func_48m_ck",
 827         .parent         = &apll96_ck,    /* 96M or Alt */
 828         .prcm_mod       = PLL_MOD,
 829         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 830                                 PARENT_CONTROLS_CLOCK,
 831         .clkdm          = { .name = "cm_clkdm" },
 832         .init           = &omap2_init_clksel_parent,
 833         .clksel_reg     = CM_CLKSEL1,
 834         .clksel_mask    = OMAP24XX_48M_SOURCE,
 835         .clksel         = func_48m_clksel,
 836         .recalc         = &omap2_clksel_recalc,
 837         .round_rate     = &omap2_clksel_round_rate,
 838         .set_rate       = &omap2_clksel_set_rate
 839 };
 840
 841 static struct clk func_12m_ck = {
 842         .name           = "func_12m_ck",
 843         .parent         = &func_48m_ck,
 844         .fixed_div      = 4,
 845         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 846                                 PARENT_CONTROLS_CLOCK,
 847         .clkdm          = { .name = "cm_clkdm" },
 848         .recalc         = &omap2_fixed_divisor_recalc,
 849 };
 850
 851 /* Secure timer, only available in secure mode */
 852 static struct clk wdt1_osc_ck = {
 853         .name           = "wdt1_osc_ck",
 854         .parent         = &osc_ck,
 855         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 856         .clkdm          = { .name = "prm_clkdm" },
 857         .recalc         = &followparent_recalc,
 858 };
 859
 860 /*
 861  * The common_clkout* clksel_rate structs are common to
 862  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 863  * sys_clkout2_* are 2420-only, so the
 864  * clksel_rate flags fields are inaccurate for those clocks. This is
 865  * harmless since access to those clocks are gated by the struct clk
 866  * flags fields, which mark them as 2420-only.
 867  */
 868 static const struct clksel_rate common_clkout_src_core_rates[] = {
 869         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 870         { .div = 0 }
 871 };
 872
 873 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 874         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 875         { .div = 0 }
 876 };
 877
 878 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 879         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 880         { .div = 0 }
 881 };
 882
 883 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 884         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 885         { .div = 0 }
 886 };
 887
 888 static const struct clksel common_clkout_src_clksel[] = {
 889         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 890         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 891         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 892         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 893         { .parent = NULL }
 894 };
 895
 896 static struct clk sys_clkout_src = {
 897         .name           = "sys_clkout_src",
 898         .parent         = &func_54m_ck,
 899         .prcm_mod       = OMAP24XX_GR_MOD,
 900         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 901         .clkdm          = { .name = "prm_clkdm" },
 902         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 903         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 904         .init           = &omap2_init_clksel_parent,
 905         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 906         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 907         .clksel         = common_clkout_src_clksel,
 908         .recalc         = &omap2_clksel_recalc,
 909         .round_rate     = &omap2_clksel_round_rate,
 910         .set_rate       = &omap2_clksel_set_rate
 911 };
 912
 913 static const struct clksel_rate common_clkout_rates[] = {
 914         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 915         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 916         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 917         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 918         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 919         { .div = 0 },
 920 };
 921
 922 static const struct clksel sys_clkout_clksel[] = {
 923         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 924         { .parent = NULL }
 925 };
 926
 927 static struct clk sys_clkout = {
 928         .name           = "sys_clkout",
 929         .parent         = &sys_clkout_src,
 930         .prcm_mod       = OMAP24XX_GR_MOD,
 931         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 932                                 PARENT_CONTROLS_CLOCK,
 933         .clkdm          = { .name = "prm_clkdm" },
 934         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 935         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 936         .clksel         = sys_clkout_clksel,
 937         .recalc         = &omap2_clksel_recalc,
 938         .round_rate     = &omap2_clksel_round_rate,
 939         .set_rate       = &omap2_clksel_set_rate
 940 };
 941
 942 /* In 2430, new in 2420 ES2 */
 943 static struct clk sys_clkout2_src = {
 944         .name           = "sys_clkout2_src",
 945         .parent         = &func_54m_ck,
 946         .prcm_mod       = OMAP24XX_GR_MOD,
 947         .flags          = CLOCK_IN_OMAP242X,
 948         .clkdm          = { .name = "cm_clkdm" },
 949         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 950         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 951         .init           = &omap2_init_clksel_parent,
 952         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 953         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 954         .clksel         = common_clkout_src_clksel,
 955         .recalc         = &omap2_clksel_recalc,
 956         .round_rate     = &omap2_clksel_round_rate,
 957         .set_rate       = &omap2_clksel_set_rate
 958 };
 959
 960 static const struct clksel sys_clkout2_clksel[] = {
 961         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 962         { .parent = NULL }
 963 };
 964
 965 /* In 2430, new in 2420 ES2 */
 966 static struct clk sys_clkout2 = {
 967         .name           = "sys_clkout2",
 968         .parent         = &sys_clkout2_src,
 969         .prcm_mod       = OMAP24XX_GR_MOD,
 970         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 971         .clkdm          = { .name = "cm_clkdm" },
 972         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET,
 973         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 974         .clksel         = sys_clkout2_clksel,
 975         .recalc         = &omap2_clksel_recalc,
 976         .round_rate     = &omap2_clksel_round_rate,
 977         .set_rate       = &omap2_clksel_set_rate
 978 };
 979
 980 static struct clk emul_ck = {
 981         .name           = "emul_ck",
 982         .parent         = &func_54m_ck,
 983         .prcm_mod       = OMAP24XX_GR_MOD,
 984         .flags          = CLOCK_IN_OMAP242X,
 985         .clkdm          = { .name = "cm_clkdm" },
 986         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET,
 987         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 988         .recalc         = &followparent_recalc,
 989
 990 };
 991
 992 /*
 993  * MPU clock domain
 994  *      Clocks:
 995  *              MPU_FCLK, MPU_ICLK
 996  *              INT_M_FCLK, INT_M_I_CLK
 997  *
 998  * - Individual clocks are hardware managed.
 999  * - Base divider comes from: CM_CLKSEL_MPU
1000  *
1001  */
1002 static const struct clksel_rate mpu_core_rates[] = {
1003         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1004         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1005         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1006         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1007         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1008         { .div = 0 },
1009 };
1010
1011 static const struct clksel mpu_clksel[] = {
1012         { .parent = &core_ck, .rates = mpu_core_rates },
1013         { .parent = NULL }
1014 };
1015
1016 static struct clk mpu_ck = {    /* Control cpu */
1017         .name           = "mpu_ck",
1018         .parent         = &core_ck,
1019         .prcm_mod       = MPU_MOD,
1020         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1021                                 ALWAYS_ENABLED | DELAYED_APP,
1022         .clkdm          = { .name = "mpu_clkdm" },
1023         .init           = &omap2_init_clksel_parent,
1024         .clksel_reg     = CM_CLKSEL,
1025         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
1026         .clksel         = mpu_clksel,
1027         .recalc         = &omap2_clksel_recalc,
1028 };
1029
1030 /*
1031  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1032  * Clocks:
1033  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1034  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1035  *
1036  * Won't be too specific here. The core clock comes into this block
1037  * it is divided then tee'ed. One branch goes directly to xyz enable
1038  * controls. The other branch gets further divided by 2 then possibly
1039  * routed into a synchronizer and out of clocks abc.
1040  */
1041 static const struct clksel_rate dsp_fck_core_rates[] = {
1042         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1043         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1044         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1045         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1046         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1047         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1048         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1049         { .div = 0 },
1050 };
1051
1052 static const struct clksel dsp_fck_clksel[] = {
1053         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1054         { .parent = NULL }
1055 };
1056
1057 static struct clk dsp_fck = {
1058         .name           = "dsp_fck",
1059         .parent         = &core_ck,
1060         .prcm_mod       = OMAP24XX_DSP_MOD,
1061         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP,
1062         .clkdm          = { .name = "dsp_clkdm" },
1063         .enable_reg     = CM_FCLKEN,
1064         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1065         .clksel_reg     = CM_CLKSEL,
1066         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1067         .clksel         = dsp_fck_clksel,
1068         .recalc         = &omap2_clksel_recalc,
1069 };
1070
1071 /* DSP interface clock */
1072 static const struct clksel_rate dsp_irate_ick_rates[] = {
1073         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1074         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1075         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1076         { .div = 0 },
1077 };
1078
1079 static const struct clksel dsp_irate_ick_clksel[] = {
1080         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1081         { .parent = NULL }
1082 };
1083
1084 /* This clock does not exist as such in the TRM. */
1085 static struct clk dsp_irate_ick = {
1086         .name           = "dsp_irate_ick",
1087         .parent         = &dsp_fck,
1088         .prcm_mod       = OMAP24XX_DSP_MOD,
1089         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1090                                 PARENT_CONTROLS_CLOCK,
1091         .clkdm          = { .name = "dsp_clkdm" },
1092         .clksel_reg     = CM_CLKSEL,
1093         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1094         .clksel         = dsp_irate_ick_clksel,
1095         .recalc         = &omap2_clksel_recalc,
1096 };
1097
1098 /* 2420 only */
1099 static struct clk dsp_ick = {
1100         .name           = "dsp_ick",     /* apparently ipi and isp */
1101         .parent         = &dsp_irate_ick,
1102         .prcm_mod       = OMAP24XX_DSP_MOD,
1103         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
1104         .clkdm          = { .name = "dsp_clkdm" },
1105         .enable_reg     = CM_ICLKEN,
1106         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1107 };
1108
1109 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1110 static struct clk iva2_1_ick = {
1111         .name           = "iva2_1_ick",
1112         .parent         = &dsp_irate_ick,
1113         .prcm_mod       = OMAP24XX_DSP_MOD,
1114         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP,
1115         .clkdm          = { .name = "dsp_clkdm" },
1116         .enable_reg     = CM_FCLKEN,
1117         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1118 };
1119
1120 /*
1121  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1122  * the C54x, but which is contained in the DSP powerdomain.  Does not
1123  * exist on later OMAPs.
1124  */
1125 static struct clk iva1_ifck = {
1126         .name           = "iva1_ifck",
1127         .parent         = &core_ck,
1128         .prcm_mod       = OMAP24XX_DSP_MOD,
1129         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
1130         .clkdm          = { .name = "iva1_clkdm" },
1131         .enable_reg     = CM_FCLKEN,
1132         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1133         .clksel_reg     = CM_CLKSEL,
1134         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1135         .clksel         = dsp_fck_clksel,
1136         .recalc         = &omap2_clksel_recalc,
1137         .round_rate     = &omap2_clksel_round_rate,
1138         .set_rate       = &omap2_clksel_set_rate
1139 };
1140
1141 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1142 static struct clk iva1_mpu_int_ifck = {
1143         .name           = "iva1_mpu_int_ifck",
1144         .parent         = &iva1_ifck,
1145         .prcm_mod       = OMAP24XX_DSP_MOD,
1146         .flags          = CLOCK_IN_OMAP242X,
1147         .clkdm          = { .name = "iva1_clkdm" },
1148         .enable_reg     = CM_FCLKEN,
1149         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1150         .fixed_div      = 2,
1151         .recalc         = &omap2_fixed_divisor_recalc,
1152 };
1153
1154 /*
1155  * L3 clock domain
1156  * L3 clocks are used for both interface and functional clocks to
1157  * multiple entities. Some of these clocks are completely managed
1158  * by hardware, and some others allow software control. Hardware
1159  * managed ones general are based on directly CLK_REQ signals and
1160  * various auto idle settings. The functional spec sets many of these
1161  * as 'tie-high' for their enables.
1162  *
1163  * I-CLOCKS:
1164  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1165  *      CAM, HS-USB.
1166  * F-CLOCK
1167  *      SSI.
1168  *
1169  * GPMC memories and SDRC have timing and clock sensitive registers which
1170  * may very well need notification when the clock changes. Currently for low
1171  * operating points, these are taken care of in sleep.S.
1172  */
1173 static const struct clksel_rate core_l3_core_rates[] = {
1174         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1175         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1176         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1177         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1178         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1179         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1180         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1181         { .div = 0 }
1182 };
1183
1184 static const struct clksel core_l3_clksel[] = {
1185         { .parent = &core_ck, .rates = core_l3_core_rates },
1186         { .parent = NULL }
1187 };
1188
1189 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1190         .name           = "core_l3_ck",
1191         .parent         = &core_ck,
1192         .prcm_mod       = CORE_MOD,
1193         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1194                                 ALWAYS_ENABLED | DELAYED_APP,
1195         .clkdm          = { .name = "core_l3_clkdm" },
1196         .clksel_reg     = CM_CLKSEL1,
1197         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1198         .clksel         = core_l3_clksel,
1199         .recalc         = &omap2_clksel_recalc,
1200 };
1201
1202 /* usb_l4_ick */
1203 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1204         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1205         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1206         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1207         { .div = 0 }
1208 };
1209
1210 static const struct clksel usb_l4_ick_clksel[] = {
1211         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1212         { .parent = NULL },
1213 };
1214
1215 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1216 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1217         .name           = "usb_l4_ick",
1218         .parent         = &core_l3_ck,
1219         .prcm_mod       = CORE_MOD,
1220         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY |
1221                                 DELAYED_APP,
1222         .clkdm          = { .name = "core_l4_clkdm" },
1223         .enable_reg     = CM_ICLKEN2,
1224         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1225         .idlest_bit     = OMAP24XX_ST_USB_SHIFT,
1226         .clksel_reg     = CM_CLKSEL1,
1227         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1228         .clksel         = usb_l4_ick_clksel,
1229         .recalc         = &omap2_clksel_recalc,
1230 };
1231
1232 /*
1233  * L4 clock management domain
1234  *
1235  * This domain contains lots of interface clocks from the L4 interface, some
1236  * functional clocks.   Fixed APLL functional source clocks are managed in
1237  * this domain.
1238  */
1239 static const struct clksel_rate l4_core_l3_rates[] = {
1240         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1241         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1242         { .div = 0 }
1243 };
1244
1245 static const struct clksel l4_clksel[] = {
1246         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1247         { .parent = NULL }
1248 };
1249
1250 static struct clk l4_ck = {             /* used both as an ick and fck */
1251         .name           = "l4_ck",
1252         .parent         = &core_l3_ck,
1253         .prcm_mod       = CORE_MOD,
1254         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1255                                 ALWAYS_ENABLED | DELAYED_APP,
1256         .clkdm          = { .name = "core_l4_clkdm" },
1257         .clksel_reg     = CM_CLKSEL1,
1258         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1259         .clksel         = l4_clksel,
1260         .recalc         = &omap2_clksel_recalc,
1261         .round_rate     = &omap2_clksel_round_rate,
1262         .set_rate       = &omap2_clksel_set_rate
1263 };
1264
1265 /*
1266  * SSI is in L3 management domain, its direct parent is core not l3,
1267  * many core power domain entities are grouped into the L3 clock
1268  * domain.
1269  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1270  *
1271  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1272  */
1273 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1274         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1275         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1276         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1277         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1278         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1279         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1280         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1281         { .div = 0 }
1282 };
1283
1284 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1285         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1286         { .parent = NULL }
1287 };
1288
1289 static struct clk ssi_ssr_sst_fck = {
1290         .name           = "ssi_fck",
1291         .parent         = &core_ck,
1292         .prcm_mod       = CORE_MOD,
1293         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY |
1294                                 DELAYED_APP,
1295         .clkdm          = { .name = "core_l3_clkdm" },
1296         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1297         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1298         .idlest_bit     = OMAP24XX_ST_SSI_SHIFT,
1299         .clksel_reg     = CM_CLKSEL1,
1300         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1301         .clksel         = ssi_ssr_sst_fck_clksel,
1302         .recalc         = &omap2_clksel_recalc,
1303         .round_rate     = &omap2_clksel_round_rate,
1304         .set_rate       = &omap2_clksel_set_rate
1305 };
1306
1307 /*
1308  * Presumably this is the same as SSI_ICLK.
1309  * TRM contradicts itself on what clockdomain SSI_ICLK is in
1310  */
1311 static struct clk ssi_l4_ick = {
1312         .name           = "ssi_l4_ick",
1313         .parent         = &l4_ck,
1314         .prcm_mod       = CORE_MOD,
1315         .clkdm          = { .name = "core_l4_clkdm" },
1316         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1317         .enable_reg     = CM_ICLKEN2,
1318         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1319         .idlest_bit     = OMAP24XX_ST_SSI_SHIFT,
1320         .recalc         = &followparent_recalc,
1321 };
1322
1323
1324 /*
1325  * GFX clock domain
1326  *      Clocks:
1327  * GFX_FCLK, GFX_ICLK
1328  * GFX_CG1(2d), GFX_CG2(3d)
1329  *
1330  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1331  * The 2d and 3d clocks run at a hardware determined
1332  * divided value of fclk.
1333  *
1334  */
1335 /* XXX REVISIT: GFX clock is part of the table rate set also? doublecheck. */
1336
1337 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1338 static const struct clksel gfx_fck_clksel[] = {
1339         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1340         { .parent = NULL },
1341 };
1342
1343 static struct clk gfx_3d_fck = {
1344         .name           = "gfx_3d_fck",
1345         .parent         = &core_l3_ck,
1346         .prcm_mod       = GFX_MOD,
1347         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1348         .clkdm          = { .name = "gfx_clkdm" },
1349         .enable_reg     = CM_FCLKEN,
1350         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1351         .clksel_reg     = CM_CLKSEL,
1352         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1353         .clksel         = gfx_fck_clksel,
1354         .recalc         = &omap2_clksel_recalc,
1355         .round_rate     = &omap2_clksel_round_rate,
1356         .set_rate       = &omap2_clksel_set_rate
1357 };
1358
1359 static struct clk gfx_2d_fck = {
1360         .name           = "gfx_2d_fck",
1361         .parent         = &core_l3_ck,
1362         .prcm_mod       = GFX_MOD,
1363         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1364         .clkdm          = { .name = "gfx_clkdm" },
1365         .enable_reg     = CM_FCLKEN,
1366         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1367         .clksel_reg     = CM_CLKSEL,
1368         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1369         .clksel         = gfx_fck_clksel,
1370         .recalc         = &omap2_clksel_recalc,
1371         .round_rate     = &omap2_clksel_round_rate,
1372         .set_rate       = &omap2_clksel_set_rate
1373 };
1374
1375 static struct clk gfx_ick = {
1376         .name           = "gfx_ick",            /* From l3 */
1377         .parent         = &core_l3_ck,
1378         .prcm_mod       = GFX_MOD,
1379         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1380         .clkdm          = { .name = "gfx_clkdm" },
1381         .enable_reg     = CM_ICLKEN,
1382         .enable_bit     = OMAP_EN_GFX_SHIFT,
1383         .recalc         = &followparent_recalc,
1384 };
1385
1386 /*
1387  * Modem clock domain (2430)
1388  *      CLOCKS:
1389  *              MDM_OSC_CLK
1390  *              MDM_ICLK
1391  * These clocks are usable in chassis mode only.
1392  */
1393 static const struct clksel_rate mdm_ick_core_rates[] = {
1394         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1395         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1396         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1397         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1398         { .div = 0 }
1399 };
1400
1401 static const struct clksel mdm_ick_clksel[] = {
1402         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1403         { .parent = NULL }
1404 };
1405
1406 static struct clk mdm_ick = {           /* used both as a ick and fck */
1407         .name           = "mdm_ick",
1408         .parent         = &core_ck,
1409         .prcm_mod       = OMAP2430_MDM_MOD,
1410         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP,
1411         .clkdm          = { .name = "mdm_clkdm" },
1412         .enable_reg     = CM_ICLKEN,
1413         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1414         .clksel_reg     = CM_CLKSEL,
1415         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1416         .clksel         = mdm_ick_clksel,
1417         .recalc         = &omap2_clksel_recalc,
1418 };
1419
1420 static struct clk mdm_osc_ck = {
1421         .name           = "mdm_osc_ck",
1422         .parent         = &osc_ck,
1423         .prcm_mod       = OMAP2430_MDM_MOD,
1424         .flags          = CLOCK_IN_OMAP243X,
1425         .clkdm          = { .name = "mdm_clkdm" },
1426         .enable_reg     = CM_FCLKEN,
1427         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1428         .recalc         = &followparent_recalc,
1429 };
1430
1431 /*
1432  * DSS clock domain
1433  * CLOCKs:
1434  * DSS_L4_ICLK, DSS_L3_ICLK,
1435  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1436  *
1437  * DSS is both initiator and target.
1438  */
1439 /* XXX Add RATE_NOT_VALIDATED */
1440
1441 static const struct clksel_rate dss1_fck_sys_rates[] = {
1442         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1443         { .div = 0 }
1444 };
1445
1446 static const struct clksel_rate dss1_fck_core_rates[] = {
1447         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1448         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1449         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1450         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1451         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1452         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1453         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1454         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1455         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1456         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1457         { .div = 0 }
1458 };
1459
1460 static const struct clksel dss1_fck_clksel[] = {
1461         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1462         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1463         { .parent = NULL },
1464 };
1465
1466 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1467         .name           = "dss_ick",
1468         .parent         = &l4_ck,       /* really both l3 and l4 */
1469         .prcm_mod       = CORE_MOD,
1470         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1471         .clkdm          = { .name = "dss_clkdm" },
1472         .enable_reg     = CM_ICLKEN1,
1473         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1474         .recalc         = &followparent_recalc,
1475 };
1476
1477 static struct clk dss1_fck = {
1478         .name           = "dss1_fck",
1479         .parent         = &core_ck,             /* Core or sys */
1480         .prcm_mod       = CORE_MOD,
1481         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1482                                 DELAYED_APP,
1483         .clkdm          = { .name = "dss_clkdm" },
1484         .enable_reg     = CM_FCLKEN1,
1485         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1486         .init           = &omap2_init_clksel_parent,
1487         .clksel_reg     = CM_CLKSEL1,
1488         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1489         .clksel         = dss1_fck_clksel,
1490         .recalc         = &omap2_clksel_recalc,
1491         .round_rate     = &omap2_clksel_round_rate,
1492         .set_rate       = &omap2_clksel_set_rate
1493 };
1494
1495 static const struct clksel_rate dss2_fck_sys_rates[] = {
1496         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1497         { .div = 0 }
1498 };
1499
1500 static const struct clksel_rate dss2_fck_48m_rates[] = {
1501         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1502         { .div = 0 }
1503 };
1504
1505 static const struct clksel dss2_fck_clksel[] = {
1506         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1507         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1508         { .parent = NULL }
1509 };
1510
1511 static struct clk dss2_fck = {          /* Alt clk used in power management */
1512         .name           = "dss2_fck",
1513         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1514         .prcm_mod       = CORE_MOD,
1515         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1516                                 DELAYED_APP,
1517         .clkdm          = { .name = "dss_clkdm" },
1518         .enable_reg     = CM_FCLKEN1,
1519         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1520         .init           = &omap2_init_clksel_parent,
1521         .clksel_reg     = CM_CLKSEL1,
1522         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1523         .clksel         = dss2_fck_clksel,
1524         .recalc         = &followparent_recalc,
1525 };
1526
1527 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1528         .name           = "dss_54m_fck",        /* 54m tv clk */
1529         .parent         = &func_54m_ck,
1530         .prcm_mod       = CORE_MOD,
1531         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1532         .clkdm          = { .name = "dss_clkdm" },
1533         .enable_reg     = CM_FCLKEN1,
1534         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1535         .recalc         = &followparent_recalc,
1536 };
1537
1538 /*
1539  * CORE power domain ICLK & FCLK defines.
1540  * Many of the these can have more than one possible parent. Entries
1541  * here will likely have an L4 interface parent, and may have multiple
1542  * functional clock parents.
1543  */
1544 static const struct clksel_rate gpt_alt_rates[] = {
1545         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1546         { .div = 0 }
1547 };
1548
1549 static const struct clksel omap24xx_gpt_clksel[] = {
1550         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1551         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1552         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1553         { .parent = NULL },
1554 };
1555
1556 static struct clk gpt1_ick = {
1557         .name           = "gpt1_ick",
1558         .parent         = &l4_ck,
1559         .prcm_mod       = WKUP_MOD,
1560         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1561         .clkdm          = { .name = "core_l4_clkdm" },
1562         .enable_reg     = CM_ICLKEN,
1563         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1564         .idlest_bit     = OMAP24XX_ST_GPT1_SHIFT,
1565         .recalc         = &followparent_recalc,
1566 };
1567
1568 static struct clk gpt1_fck = {
1569         .name           = "gpt1_fck",
1570         .parent         = &func_32k_ck,
1571         .prcm_mod       = WKUP_MOD,
1572         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573         .clkdm          = { .name = "core_l4_clkdm" },
1574         .enable_reg     = CM_FCLKEN,
1575         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1576         .init           = &omap2_init_clksel_parent,
1577         .clksel_reg     = CM_CLKSEL1,
1578         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1579         .clksel         = omap24xx_gpt_clksel,
1580         .recalc         = &omap2_clksel_recalc,
1581         .round_rate     = &omap2_clksel_round_rate,
1582         .set_rate       = &omap2_clksel_set_rate
1583 };
1584
1585 static struct clk gpt2_ick = {
1586         .name           = "gpt2_ick",
1587         .parent         = &l4_ck,
1588         .prcm_mod       = CORE_MOD,
1589         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1590         .clkdm          = { .name = "core_l4_clkdm" },
1591         .enable_reg     = CM_ICLKEN1,
1592         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1593         .idlest_bit     = OMAP24XX_ST_GPT2_SHIFT,
1594         .recalc         = &followparent_recalc,
1595 };
1596
1597 static struct clk gpt2_fck = {
1598         .name           = "gpt2_fck",
1599         .parent         = &func_32k_ck,
1600         .prcm_mod       = CORE_MOD,
1601         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1602         .clkdm          = { .name = "core_l4_clkdm" },
1603         .enable_reg     = CM_FCLKEN1,
1604         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1605         .init           = &omap2_init_clksel_parent,
1606         .clksel_reg     = CM_CLKSEL2,
1607         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1608         .clksel         = omap24xx_gpt_clksel,
1609         .recalc         = &omap2_clksel_recalc,
1610 };
1611
1612 static struct clk gpt3_ick = {
1613         .name           = "gpt3_ick",
1614         .parent         = &l4_ck,
1615         .prcm_mod       = CORE_MOD,
1616         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1617         .clkdm          = { .name = "core_l4_clkdm" },
1618         .enable_reg     = CM_ICLKEN1,
1619         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1620         .idlest_bit     = OMAP24XX_ST_GPT3_SHIFT,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 static struct clk gpt3_fck = {
1625         .name           = "gpt3_fck",
1626         .parent         = &func_32k_ck,
1627         .prcm_mod       = CORE_MOD,
1628         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1629         .clkdm          = { .name = "core_l4_clkdm" },
1630         .enable_reg     = CM_FCLKEN1,
1631         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1632         .init           = &omap2_init_clksel_parent,
1633         .clksel_reg     = CM_CLKSEL2,
1634         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1635         .clksel         = omap24xx_gpt_clksel,
1636         .recalc         = &omap2_clksel_recalc,
1637 };
1638
1639 static struct clk gpt4_ick = {
1640         .name           = "gpt4_ick",
1641         .parent         = &l4_ck,
1642         .prcm_mod       = CORE_MOD,
1643         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1644         .clkdm          = { .name = "core_l4_clkdm" },
1645         .enable_reg     = CM_ICLKEN1,
1646         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1647         .idlest_bit     = OMAP24XX_ST_GPT4_SHIFT,
1648         .recalc         = &followparent_recalc,
1649 };
1650
1651 static struct clk gpt4_fck = {
1652         .name           = "gpt4_fck",
1653         .parent         = &func_32k_ck,
1654         .prcm_mod       = CORE_MOD,
1655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1656         .clkdm          = { .name = "core_l4_clkdm" },
1657         .enable_reg     = CM_FCLKEN1,
1658         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1659         .init           = &omap2_init_clksel_parent,
1660         .clksel_reg     = CM_CLKSEL2,
1661         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1662         .clksel         = omap24xx_gpt_clksel,
1663         .recalc         = &omap2_clksel_recalc,
1664 };
1665
1666 static struct clk gpt5_ick = {
1667         .name           = "gpt5_ick",
1668         .parent         = &l4_ck,
1669         .prcm_mod       = CORE_MOD,
1670         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1671         .clkdm          = { .name = "core_l4_clkdm" },
1672         .enable_reg     = CM_ICLKEN1,
1673         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1674         .idlest_bit     = OMAP24XX_ST_GPT5_SHIFT,
1675         .recalc         = &followparent_recalc,
1676 };
1677
1678 static struct clk gpt5_fck = {
1679         .name           = "gpt5_fck",
1680         .parent         = &func_32k_ck,
1681         .prcm_mod       = CORE_MOD,
1682         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1683         .clkdm          = { .name = "core_l4_clkdm" },
1684         .enable_reg     = CM_FCLKEN1,
1685         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1686         .init           = &omap2_init_clksel_parent,
1687         .clksel_reg     = CM_CLKSEL2,
1688         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1689         .clksel         = omap24xx_gpt_clksel,
1690         .recalc         = &omap2_clksel_recalc,
1691 };
1692
1693 static struct clk gpt6_ick = {
1694         .name           = "gpt6_ick",
1695         .parent         = &l4_ck,
1696         .prcm_mod       = CORE_MOD,
1697         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1698         .clkdm          = { .name = "core_l4_clkdm" },
1699         .enable_reg     = CM_ICLKEN1,
1700         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1701         .idlest_bit     = OMAP24XX_ST_GPT6_SHIFT,
1702         .recalc         = &followparent_recalc,
1703 };
1704
1705 static struct clk gpt6_fck = {
1706         .name           = "gpt6_fck",
1707         .parent         = &func_32k_ck,
1708         .prcm_mod       = CORE_MOD,
1709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1710         .clkdm          = { .name = "core_l4_clkdm" },
1711         .enable_reg     = CM_FCLKEN1,
1712         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1713         .init           = &omap2_init_clksel_parent,
1714         .clksel_reg     = CM_CLKSEL2,
1715         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1716         .clksel         = omap24xx_gpt_clksel,
1717         .recalc         = &omap2_clksel_recalc,
1718 };
1719
1720 static struct clk gpt7_ick = {
1721         .name           = "gpt7_ick",
1722         .parent         = &l4_ck,
1723         .prcm_mod       = CORE_MOD,
1724         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1725         .clkdm          = { .name = "core_l4_clkdm" },
1726         .enable_reg     = CM_ICLKEN1,
1727         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1728         .idlest_bit     = OMAP24XX_ST_GPT7_SHIFT,
1729         .recalc         = &followparent_recalc,
1730 };
1731
1732 static struct clk gpt7_fck = {
1733         .name           = "gpt7_fck",
1734         .parent         = &func_32k_ck,
1735         .prcm_mod       = CORE_MOD,
1736         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1737         .clkdm          = { .name = "core_l4_clkdm" },
1738         .enable_reg     = CM_FCLKEN1,
1739         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1740         .init           = &omap2_init_clksel_parent,
1741         .clksel_reg     = CM_CLKSEL2,
1742         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1743         .clksel         = omap24xx_gpt_clksel,
1744         .recalc         = &omap2_clksel_recalc,
1745 };
1746
1747 static struct clk gpt8_ick = {
1748         .name           = "gpt8_ick",
1749         .parent         = &l4_ck,
1750         .prcm_mod       = CORE_MOD,
1751         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1752         .clkdm          = { .name = "core_l4_clkdm" },
1753         .enable_reg     = CM_ICLKEN1,
1754         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1755         .idlest_bit     = OMAP24XX_ST_GPT8_SHIFT,
1756         .recalc         = &followparent_recalc,
1757 };
1758
1759 static struct clk gpt8_fck = {
1760         .name           = "gpt8_fck",
1761         .parent         = &func_32k_ck,
1762         .prcm_mod       = CORE_MOD,
1763         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764         .clkdm          = { .name = "core_l4_clkdm" },
1765         .enable_reg     = CM_FCLKEN1,
1766         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1767         .init           = &omap2_init_clksel_parent,
1768         .clksel_reg     = CM_CLKSEL2,
1769         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1770         .clksel         = omap24xx_gpt_clksel,
1771         .recalc         = &omap2_clksel_recalc,
1772 };
1773
1774 static struct clk gpt9_ick = {
1775         .name           = "gpt9_ick",
1776         .parent         = &l4_ck,
1777         .prcm_mod       = CORE_MOD,
1778         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1779         .clkdm          = { .name = "core_l4_clkdm" },
1780         .enable_reg     = CM_ICLKEN1,
1781         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1782         .idlest_bit     = OMAP24XX_ST_GPT9_SHIFT,
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk gpt9_fck = {
1787         .name           = "gpt9_fck",
1788         .parent         = &func_32k_ck,
1789         .prcm_mod       = CORE_MOD,
1790         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1791         .clkdm          = { .name = "core_l4_clkdm" },
1792         .enable_reg     = CM_FCLKEN1,
1793         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1794         .init           = &omap2_init_clksel_parent,
1795         .clksel_reg     = CM_CLKSEL2,
1796         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1797         .clksel         = omap24xx_gpt_clksel,
1798         .recalc         = &omap2_clksel_recalc,
1799 };
1800
1801 static struct clk gpt10_ick = {
1802         .name           = "gpt10_ick",
1803         .parent         = &l4_ck,
1804         .prcm_mod       = CORE_MOD,
1805         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1806         .clkdm          = { .name = "core_l4_clkdm" },
1807         .enable_reg     = CM_ICLKEN1,
1808         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1809         .idlest_bit     = OMAP24XX_ST_GPT10_SHIFT,
1810         .recalc         = &followparent_recalc,
1811 };
1812
1813 static struct clk gpt10_fck = {
1814         .name           = "gpt10_fck",
1815         .parent         = &func_32k_ck,
1816         .prcm_mod       = CORE_MOD,
1817         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1818         .clkdm          = { .name = "core_l4_clkdm" },
1819         .enable_reg     = CM_FCLKEN1,
1820         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1821         .init           = &omap2_init_clksel_parent,
1822         .clksel_reg     = CM_CLKSEL2,
1823         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1824         .clksel         = omap24xx_gpt_clksel,
1825         .recalc         = &omap2_clksel_recalc,
1826 };
1827
1828 static struct clk gpt11_ick = {
1829         .name           = "gpt11_ick",
1830         .parent         = &l4_ck,
1831         .prcm_mod       = CORE_MOD,
1832         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1833         .clkdm          = { .name = "core_l4_clkdm" },
1834         .enable_reg     = CM_ICLKEN1,
1835         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1836         .idlest_bit     = OMAP24XX_ST_GPT11_SHIFT,
1837         .recalc         = &followparent_recalc,
1838 };
1839
1840 static struct clk gpt11_fck = {
1841         .name           = "gpt11_fck",
1842         .parent         = &func_32k_ck,
1843         .prcm_mod       = CORE_MOD,
1844         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1845         .clkdm          = { .name = "core_l4_clkdm" },
1846         .enable_reg     = CM_FCLKEN1,
1847         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1848         .init           = &omap2_init_clksel_parent,
1849         .clksel_reg     = CM_CLKSEL2,
1850         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1851         .clksel         = omap24xx_gpt_clksel,
1852         .recalc         = &omap2_clksel_recalc,
1853 };
1854
1855 static struct clk gpt12_ick = {
1856         .name           = "gpt12_ick",
1857         .parent         = &l4_ck,
1858         .prcm_mod       = CORE_MOD,
1859         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1860         .clkdm          = { .name = "core_l4_clkdm" },
1861         .enable_reg     = CM_ICLKEN1,
1862         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1863         .idlest_bit     = OMAP24XX_ST_GPT12_SHIFT,
1864         .recalc         = &followparent_recalc,
1865 };
1866
1867 static struct clk gpt12_fck = {
1868         .name           = "gpt12_fck",
1869         .parent         = &func_32k_ck,
1870         .prcm_mod       = CORE_MOD,
1871         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1872         .clkdm          = { .name = "core_l4_clkdm" },
1873         .enable_reg     = CM_FCLKEN1,
1874         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1875         .init           = &omap2_init_clksel_parent,
1876         .clksel_reg     = CM_CLKSEL2,
1877         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1878         .clksel         = omap24xx_gpt_clksel,
1879         .recalc         = &omap2_clksel_recalc,
1880 };
1881
1882 static struct clk mcbsp1_ick = {
1883         .name           = "mcbsp_ick",
1884         .id             = 1,
1885         .parent         = &l4_ck,
1886         .prcm_mod       = CORE_MOD,
1887         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1888         .clkdm          = { .name = "core_l4_clkdm" },
1889         .enable_reg     = CM_ICLKEN1,
1890         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1891         .idlest_bit     = OMAP24XX_ST_MCBSP1_SHIFT,
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk mcbsp1_fck = {
1896         .name           = "mcbsp_fck",
1897         .id             = 1,
1898         .parent         = &func_96m_ck,
1899         .prcm_mod       = CORE_MOD,
1900         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1901         .clkdm          = { .name = "core_l4_clkdm" },
1902         .enable_reg     = CM_FCLKEN1,
1903         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1904         .recalc         = &followparent_recalc,
1905 };
1906
1907 static struct clk mcbsp2_ick = {
1908         .name           = "mcbsp_ick",
1909         .id             = 2,
1910         .parent         = &l4_ck,
1911         .prcm_mod       = CORE_MOD,
1912         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
1913         .clkdm          = { .name = "core_l4_clkdm" },
1914         .enable_reg     = CM_ICLKEN1,
1915         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1916         .idlest_bit     = OMAP24XX_ST_MCBSP2_SHIFT,
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk mcbsp2_fck = {
1921         .name           = "mcbsp_fck",
1922         .id             = 2,
1923         .parent         = &func_96m_ck,
1924         .prcm_mod       = CORE_MOD,
1925         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1926         .clkdm          = { .name = "core_l4_clkdm" },
1927         .enable_reg     = CM_FCLKEN1,
1928         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk mcbsp3_ick = {
1933         .name           = "mcbsp_ick",
1934         .id             = 3,
1935         .parent         = &l4_ck,
1936         .prcm_mod       = CORE_MOD,
1937         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1938         .clkdm          = { .name = "core_l4_clkdm" },
1939         .enable_reg     = CM_ICLKEN2,
1940         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1941         .idlest_bit     = OMAP2430_ST_MCBSP3_SHIFT,
1942         .recalc         = &followparent_recalc,
1943 };
1944
1945 static struct clk mcbsp3_fck = {
1946         .name           = "mcbsp_fck",
1947         .id             = 3,
1948         .parent         = &func_96m_ck,
1949         .prcm_mod       = CORE_MOD,
1950         .flags          = CLOCK_IN_OMAP243X,
1951         .clkdm          = { .name = "core_l4_clkdm" },
1952         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1953         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1954         .recalc         = &followparent_recalc,
1955 };
1956
1957 static struct clk mcbsp4_ick = {
1958         .name           = "mcbsp_ick",
1959         .id             = 4,
1960         .parent         = &l4_ck,
1961         .prcm_mod       = CORE_MOD,
1962         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1963         .clkdm          = { .name = "core_l4_clkdm" },
1964         .enable_reg     = CM_ICLKEN2,
1965         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1966         .idlest_bit     = OMAP2430_ST_MCBSP4_SHIFT,
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk mcbsp4_fck = {
1971         .name           = "mcbsp_fck",
1972         .id             = 4,
1973         .parent         = &func_96m_ck,
1974         .prcm_mod       = CORE_MOD,
1975         .flags          = CLOCK_IN_OMAP243X,
1976         .clkdm          = { .name = "core_l4_clkdm" },
1977         .enable_reg     = OMAP24XX_CM_FCLKEN2,
1978         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1979         .recalc         = &followparent_recalc,
1980 };
1981
1982 static struct clk mcbsp5_ick = {
1983         .name           = "mcbsp_ick",
1984         .id             = 5,
1985         .parent         = &l4_ck,
1986         .prcm_mod       = CORE_MOD,
1987         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
1988         .clkdm          = { .name = "core_l4_clkdm" },
1989         .enable_reg     = CM_ICLKEN2,
1990         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1991         .idlest_bit     = OMAP2430_ST_MCBSP5_SHIFT,
1992         .recalc         = &followparent_recalc,
1993 };
1994
1995 static struct clk mcbsp5_fck = {
1996         .name           = "mcbsp_fck",
1997         .id             = 5,
1998         .parent         = &func_96m_ck,
1999         .prcm_mod       = CORE_MOD,
2000         .flags          = CLOCK_IN_OMAP243X,
2001         .clkdm          = { .name = "core_l4_clkdm" },
2002         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2003         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
2004         .recalc         = &followparent_recalc,
2005 };
2006
2007 static struct clk mcspi1_ick = {
2008         .name           = "mcspi_ick",
2009         .id             = 1,
2010         .parent         = &l4_ck,
2011         .prcm_mod       = CORE_MOD,
2012         .clkdm          = { .name = "core_l4_clkdm" },
2013         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2014         .enable_reg     = CM_ICLKEN1,
2015         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2016         .idlest_bit     = OMAP24XX_ST_MCSPI1_SHIFT,
2017         .recalc         = &followparent_recalc,
2018 };
2019
2020 static struct clk mcspi1_fck = {
2021         .name           = "mcspi_fck",
2022         .id             = 1,
2023         .parent         = &func_48m_ck,
2024         .prcm_mod       = CORE_MOD,
2025         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2026         .clkdm          = { .name = "core_l4_clkdm" },
2027         .enable_reg     = CM_FCLKEN1,
2028         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
2029         .recalc         = &followparent_recalc,
2030 };
2031
2032 static struct clk mcspi2_ick = {
2033         .name           = "mcspi_ick",
2034         .id             = 2,
2035         .parent         = &l4_ck,
2036         .prcm_mod       = CORE_MOD,
2037         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2038         .clkdm          = { .name = "core_l4_clkdm" },
2039         .enable_reg     = CM_ICLKEN1,
2040         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2041         .idlest_bit     = OMAP24XX_ST_MCSPI2_SHIFT,
2042         .recalc         = &followparent_recalc,
2043 };
2044
2045 static struct clk mcspi2_fck = {
2046         .name           = "mcspi_fck",
2047         .id             = 2,
2048         .parent         = &func_48m_ck,
2049         .prcm_mod       = CORE_MOD,
2050         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2051         .clkdm          = { .name = "core_l4_clkdm" },
2052         .enable_reg     = CM_FCLKEN1,
2053         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk mcspi3_ick = {
2058         .name           = "mcspi_ick",
2059         .id             = 3,
2060         .parent         = &l4_ck,
2061         .prcm_mod       = CORE_MOD,
2062         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2063         .clkdm          = { .name = "core_l4_clkdm" },
2064         .enable_reg     = CM_ICLKEN2,
2065         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2066         .idlest_bit     = OMAP2430_ST_MCSPI3_SHIFT,
2067         .recalc         = &followparent_recalc,
2068 };
2069
2070 static struct clk mcspi3_fck = {
2071         .name           = "mcspi_fck",
2072         .id             = 3,
2073         .parent         = &func_48m_ck,
2074         .prcm_mod       = CORE_MOD,
2075         .flags          = CLOCK_IN_OMAP243X,
2076         .clkdm          = { .name = "core_l4_clkdm" },
2077         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2078         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
2079         .recalc         = &followparent_recalc,
2080 };
2081
2082 static struct clk uart1_ick = {
2083         .name           = "uart1_ick",
2084         .parent         = &l4_ck,
2085         .prcm_mod       = CORE_MOD,
2086         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2087         .clkdm          = { .name = "core_l4_clkdm" },
2088         .enable_reg     = CM_ICLKEN1,
2089         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2090         .idlest_bit     = OMAP24XX_ST_UART1_SHIFT,
2091         .recalc         = &followparent_recalc,
2092 };
2093
2094 static struct clk uart1_fck = {
2095         .name           = "uart1_fck",
2096         .parent         = &func_48m_ck,
2097         .prcm_mod       = CORE_MOD,
2098         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2099         .clkdm          = { .name = "core_l4_clkdm" },
2100         .enable_reg     = CM_FCLKEN1,
2101         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2102         .recalc         = &followparent_recalc,
2103 };
2104
2105 static struct clk uart2_ick = {
2106         .name           = "uart2_ick",
2107         .parent         = &l4_ck,
2108         .prcm_mod       = CORE_MOD,
2109         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2110         .clkdm          = { .name = "core_l4_clkdm" },
2111         .enable_reg     = CM_ICLKEN1,
2112         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2113         .idlest_bit     = OMAP24XX_ST_UART2_SHIFT,
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk uart2_fck = {
2118         .name           = "uart2_fck",
2119         .parent         = &func_48m_ck,
2120         .prcm_mod       = CORE_MOD,
2121         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2122         .clkdm          = { .name = "core_l4_clkdm" },
2123         .enable_reg     = CM_FCLKEN1,
2124         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2125         .recalc         = &followparent_recalc,
2126 };
2127
2128 static struct clk uart3_ick = {
2129         .name           = "uart3_ick",
2130         .parent         = &l4_ck,
2131         .prcm_mod       = CORE_MOD,
2132         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2133         .clkdm          = { .name = "core_l4_clkdm" },
2134         .enable_reg     = CM_ICLKEN2,
2135         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2136         .idlest_bit     = OMAP24XX_ST_UART3_SHIFT,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 static struct clk uart3_fck = {
2141         .name           = "uart3_fck",
2142         .parent         = &func_48m_ck,
2143         .prcm_mod       = CORE_MOD,
2144         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2145         .clkdm          = { .name = "core_l4_clkdm" },
2146         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2147         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2148         .recalc         = &followparent_recalc,
2149 };
2150
2151 static struct clk gpios_ick = {
2152         .name           = "gpios_ick",
2153         .parent         = &l4_ck,
2154         .prcm_mod       = WKUP_MOD,
2155         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2156         .clkdm          = { .name = "core_l4_clkdm" },
2157         .enable_reg     = CM_ICLKEN,
2158         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2159         .idlest_bit     = OMAP24XX_ST_GPIOS_SHIFT,
2160         .recalc         = &followparent_recalc,
2161 };
2162
2163 static struct clk gpios_fck = {
2164         .name           = "gpios_fck",
2165         .parent         = &func_32k_ck,
2166         .prcm_mod       = WKUP_MOD,
2167         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2168         .clkdm          = { .name = "prm_clkdm" },
2169         .enable_reg     = CM_FCLKEN,
2170         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2171         .idlest_bit     = OMAP24XX_ST_GPIOS_SHIFT,
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 /* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
2176 static struct clk mpu_wdt_ick = {
2177         .name           = "mpu_wdt_ick",
2178         .parent         = &l4_ck,
2179         .prcm_mod       = WKUP_MOD,
2180         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2181         .clkdm          = { .name = "prm_clkdm" },
2182         .enable_reg     = CM_ICLKEN,
2183         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2184         .idlest_bit     = OMAP24XX_ST_MPU_WDT_SHIFT,
2185         .recalc         = &followparent_recalc,
2186 };
2187
2188 /* aka WDT2 */
2189 static struct clk mpu_wdt_fck = {
2190         .name           = "mpu_wdt_fck",
2191         .parent         = &func_32k_ck,
2192         .prcm_mod       = WKUP_MOD,
2193         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2194         .clkdm          = { .name = "prm_clkdm" },
2195         .enable_reg     = CM_FCLKEN,
2196         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2197         .idlest_bit     = OMAP24XX_ST_MPU_WDT_SHIFT,
2198         .recalc         = &followparent_recalc,
2199 };
2200
2201 static struct clk sync_32k_ick = {
2202         .name           = "sync_32k_ick",
2203         .parent         = &l4_ck,
2204         .prcm_mod       = WKUP_MOD,
2205         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2206                                 ENABLE_ON_INIT | WAIT_READY,
2207         .clkdm          = { .name = "core_l4_clkdm" },
2208         .enable_reg     = CM_ICLKEN,
2209         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2210         .idlest_bit     = OMAP24XX_ST_32KSYNC_SHIFT,
2211         .recalc         = &followparent_recalc,
2212 };
2213
2214 /* REVISIT: parent is really wu_l4_iclk */
2215 static struct clk wdt1_ick = {
2216         .name           = "wdt1_ick",
2217         .parent         = &l4_ck,
2218         .prcm_mod       = WKUP_MOD,
2219         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2220         .clkdm          = { .name = "prm_clkdm" },
2221         .enable_reg     = CM_ICLKEN,
2222         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2223         .idlest_bit     = OMAP24XX_ST_WDT1_SHIFT,
2224         .recalc         = &followparent_recalc,
2225 };
2226
2227 static struct clk omapctrl_ick = {
2228         .name           = "omapctrl_ick",
2229         .parent         = &l4_ck,
2230         .prcm_mod       = WKUP_MOD,
2231         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2232                                 ENABLE_ON_INIT,
2233         .clkdm          = { .name = "core_l4_clkdm" },
2234         .enable_reg     = CM_ICLKEN,
2235         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2236         .idlest_bit     = OMAP24XX_ST_OMAPCTRL_SHIFT,
2237         .recalc         = &followparent_recalc,
2238 };
2239
2240 static struct clk icr_ick = {
2241         .name           = "icr_ick",
2242         .parent         = &l4_ck,
2243         .prcm_mod       = WKUP_MOD,
2244         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2245         .clkdm          = { .name = "core_l4_clkdm" },
2246         .enable_reg     = CM_ICLKEN,
2247         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2248         .idlest_bit     = OMAP2430_ST_ICR_SHIFT,
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk cam_ick = {
2253         .name           = "cam_ick",
2254         .parent         = &l4_ck,
2255         .prcm_mod       = CORE_MOD,
2256         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2257         .clkdm          = { .name = "core_l4_clkdm" },
2258         .enable_reg     = CM_ICLKEN1,
2259         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 /*
2264  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
2265  * split into two separate clocks, since the parent clocks are different
2266  * and the clockdomains are also different.
2267  */
2268 static struct clk cam_fck = {
2269         .name           = "cam_fck",
2270         .parent         = &func_96m_ck,
2271         .prcm_mod       = CORE_MOD,
2272         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2273         .clkdm          = { .name = "core_l3_clkdm" },
2274         .enable_reg     = CM_FCLKEN1,
2275         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2276         .recalc         = &followparent_recalc,
2277 };
2278
2279 static struct clk mailboxes_ick = {
2280         .name           = "mailboxes_ick",
2281         .parent         = &l4_ck,
2282         .prcm_mod       = CORE_MOD,
2283         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2284         .clkdm          = { .name = "core_l4_clkdm" },
2285         .enable_reg     = CM_ICLKEN1,
2286         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2287         .idlest_bit     = OMAP24XX_ST_MAILBOXES_SHIFT,
2288         .recalc         = &followparent_recalc,
2289 };
2290
2291 static struct clk wdt4_ick = {
2292         .name           = "wdt4_ick",
2293         .parent         = &l4_ck,
2294         .prcm_mod       = CORE_MOD,
2295         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2296         .clkdm          = { .name = "core_l4_clkdm" },
2297         .enable_reg     = CM_ICLKEN1,
2298         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2299         .idlest_bit     = OMAP24XX_ST_WDT4_SHIFT,
2300         .recalc         = &followparent_recalc,
2301 };
2302
2303 static struct clk wdt4_fck = {
2304         .name           = "wdt4_fck",
2305         .parent         = &func_32k_ck,
2306         .prcm_mod       = CORE_MOD,
2307         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2308         .clkdm          = { .name = "core_l4_clkdm" },
2309         .enable_reg     = CM_FCLKEN1,
2310         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2311         .recalc         = &followparent_recalc,
2312 };
2313
2314 static struct clk wdt3_ick = {
2315         .name           = "wdt3_ick",
2316         .parent         = &l4_ck,
2317         .prcm_mod       = CORE_MOD,
2318         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2319         .clkdm          = { .name = "core_l4_clkdm" },
2320         .enable_reg     = CM_ICLKEN1,
2321         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2322         .idlest_bit     = OMAP2420_ST_WDT3_SHIFT,
2323         .recalc         = &followparent_recalc,
2324 };
2325
2326 static struct clk wdt3_fck = {
2327         .name           = "wdt3_fck",
2328         .parent         = &func_32k_ck,
2329         .prcm_mod       = CORE_MOD,
2330         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2331         .clkdm          = { .name = "core_l4_clkdm" },
2332         .enable_reg     = CM_FCLKEN1,
2333         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2334         .enable_bit     = OMAP2420_ST_WDT3_SHIFT,
2335         .recalc         = &followparent_recalc,
2336 };
2337
2338 static struct clk mspro_ick = {
2339         .name           = "mspro_ick",
2340         .parent         = &l4_ck,
2341         .prcm_mod       = CORE_MOD,
2342         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2343         .clkdm          = { .name = "core_l4_clkdm" },
2344         .enable_reg     = CM_ICLKEN1,
2345         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2346         .idlest_bit     = OMAP24XX_ST_MSPRO_SHIFT,
2347         .recalc         = &followparent_recalc,
2348 };
2349
2350 static struct clk mspro_fck = {
2351         .name           = "mspro_fck",
2352         .parent         = &func_96m_ck,
2353         .prcm_mod       = CORE_MOD,
2354         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2355         .clkdm          = { .name = "core_l4_clkdm" },
2356         .enable_reg     = CM_FCLKEN1,
2357         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2358         .idlest_bit     = OMAP24XX_ST_MSPRO_SHIFT,
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk mmc_ick = {
2363         .name           = "mmc_ick",
2364         .parent         = &l4_ck,
2365         .prcm_mod       = CORE_MOD,
2366         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2367         .clkdm          = { .name = "core_l4_clkdm" },
2368         .enable_reg     = CM_ICLKEN1,
2369         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2370         .idlest_bit     = OMAP2420_ST_MMC_SHIFT,
2371         .recalc         = &followparent_recalc,
2372 };
2373
2374 static struct clk mmc_fck = {
2375         .name           = "mmc_fck",
2376         .parent         = &func_96m_ck,
2377         .prcm_mod       = CORE_MOD,
2378         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2379         .clkdm          = { .name = "core_l4_clkdm" },
2380         .enable_reg     = CM_FCLKEN1,
2381         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2382         .idlest_bit     = OMAP2420_ST_MMC_SHIFT,
2383         .recalc         = &followparent_recalc,
2384 };
2385
2386 static struct clk fac_ick = {
2387         .name           = "fac_ick",
2388         .parent         = &l4_ck,
2389         .prcm_mod       = CORE_MOD,
2390         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2391         .clkdm          = { .name = "core_l4_clkdm" },
2392         .enable_reg     = CM_ICLKEN1,
2393         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2394         .idlest_bit     = OMAP24XX_ST_FAC_SHIFT,
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static struct clk fac_fck = {
2399         .name           = "fac_fck",
2400         .parent         = &func_12m_ck,
2401         .prcm_mod       = CORE_MOD,
2402         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2403         .clkdm          = { .name = "core_l4_clkdm" },
2404         .enable_reg     = CM_FCLKEN1,
2405         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2406         .idlest_bit     = OMAP24XX_ST_FAC_SHIFT,
2407         .recalc         = &followparent_recalc,
2408 };
2409
2410 static struct clk eac_ick = {
2411         .name           = "eac_ick",
2412         .parent         = &l4_ck,
2413         .prcm_mod       = CORE_MOD,
2414         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2415         .clkdm          = { .name = "core_l4_clkdm" },
2416         .enable_reg     = CM_ICLKEN1,
2417         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2418         .idlest_bit     = OMAP2420_ST_EAC_SHIFT,
2419         .recalc         = &followparent_recalc,
2420 };
2421
2422 static struct clk eac_fck = {
2423         .name           = "eac_fck",
2424         .parent         = &func_96m_ck,
2425         .prcm_mod       = CORE_MOD,
2426         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2427         .clkdm          = { .name = "core_l4_clkdm" },
2428         .enable_reg     = CM_FCLKEN1,
2429         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2430         .idlest_bit     = OMAP2420_ST_EAC_SHIFT,
2431         .recalc         = &followparent_recalc,
2432 };
2433
2434 static struct clk hdq_ick = {
2435         .name           = "hdq_ick",
2436         .parent         = &l4_ck,
2437         .prcm_mod       = CORE_MOD,
2438         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2439         .clkdm          = { .name = "core_l4_clkdm" },
2440         .enable_reg     = CM_ICLKEN1,
2441         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2442         .idlest_bit     = OMAP24XX_ST_HDQ_SHIFT,
2443         .recalc         = &followparent_recalc,
2444 };
2445
2446 static struct clk hdq_fck = {
2447         .name           = "hdq_fck",
2448         .parent         = &func_12m_ck,
2449         .prcm_mod       = CORE_MOD,
2450         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2451         .clkdm          = { .name = "core_l4_clkdm" },
2452         .enable_reg     = CM_FCLKEN1,
2453         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2454         .idlest_bit     = OMAP24XX_ST_HDQ_SHIFT,
2455         .recalc         = &followparent_recalc,
2456 };
2457
2458 static struct clk i2c2_ick = {
2459         .name           = "i2c_ick",
2460         .id             = 2,
2461         .parent         = &l4_ck,
2462         .prcm_mod       = CORE_MOD,
2463         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2464         .clkdm          = { .name = "core_l4_clkdm" },
2465         .enable_reg     = CM_ICLKEN1,
2466         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2467         .idlest_bit     = OMAP2420_ST_I2C2_SHIFT,
2468         .recalc         = &followparent_recalc,
2469 };
2470
2471 static struct clk i2c2_fck = {
2472         .name           = "i2c_fck",
2473         .id             = 2,
2474         .parent         = &func_12m_ck,
2475         .prcm_mod       = CORE_MOD,
2476         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2477         .clkdm          = { .name = "core_l4_clkdm" },
2478         .enable_reg     = CM_FCLKEN1,
2479         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2480         .idlest_bit     = OMAP2420_ST_I2C2_SHIFT,
2481         .recalc         = &followparent_recalc,
2482 };
2483
2484 static struct clk i2chs2_fck = {
2485         .name           = "i2c_fck",
2486         .id             = 2,
2487         .parent         = &func_96m_ck,
2488         .prcm_mod       = CORE_MOD,
2489         .flags          = CLOCK_IN_OMAP243X,
2490         .clkdm          = { .name = "core_l4_clkdm" },
2491         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2492         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2493         .recalc         = &followparent_recalc,
2494 };
2495
2496 static struct clk i2c1_ick = {
2497         .name           = "i2c_ick",
2498         .id             = 1,
2499         .parent         = &l4_ck,
2500         .prcm_mod       = CORE_MOD,
2501         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | WAIT_READY,
2502         .clkdm          = { .name = "core_l4_clkdm" },
2503         .enable_reg     = CM_ICLKEN1,
2504         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2505         .idlest_bit     = OMAP2420_ST_I2C1_SHIFT,
2506         .recalc         = &followparent_recalc,
2507 };
2508
2509 static struct clk i2c1_fck = {
2510         .name           = "i2c_fck",
2511         .id             = 1,
2512         .parent         = &func_12m_ck,
2513         .prcm_mod       = CORE_MOD,
2514         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2515         .clkdm          = { .name = "core_l4_clkdm" },
2516         .enable_reg     = CM_FCLKEN1,
2517         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2518         .idlest_bit     = OMAP2420_ST_I2C1_SHIFT,
2519         .recalc         = &followparent_recalc,
2520 };
2521
2522 static struct clk i2chs1_fck = {
2523         .name           = "i2c_fck",
2524         .id             = 1,
2525         .parent         = &func_96m_ck,
2526         .prcm_mod       = CORE_MOD,
2527         .flags          = CLOCK_IN_OMAP243X,
2528         .clkdm          = { .name = "core_l4_clkdm" },
2529         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2530         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2531         .recalc         = &followparent_recalc,
2532 };
2533
2534 static struct clk gpmc_fck = {
2535         .name           = "gpmc_fck",
2536         .parent         = &core_l3_ck,
2537         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2538                                 ENABLE_ON_INIT,
2539         .clkdm          = { .name = "core_l3_clkdm" },
2540         .recalc         = &followparent_recalc,
2541 };
2542
2543 static struct clk sdma_fck = {
2544         .name           = "sdma_fck",
2545         .parent         = &core_l3_ck,
2546         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2547         .clkdm          = { .name = "core_l3_clkdm" },
2548         .recalc         = &followparent_recalc,
2549 };
2550
2551 static struct clk sdma_ick = {
2552         .name           = "sdma_ick",
2553         .parent         = &l4_ck,
2554         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2555         .clkdm          = { .name = "core_l3_clkdm" },
2556         .recalc         = &followparent_recalc,
2557 };
2558
2559 static struct clk vlynq_ick = {
2560         .name           = "vlynq_ick",
2561         .parent         = &core_l3_ck,
2562         .prcm_mod       = CORE_MOD,
2563         .flags          = CLOCK_IN_OMAP242X | WAIT_READY,
2564         .clkdm          = { .name = "core_l3_clkdm" },
2565         .enable_reg     = CM_ICLKEN1,
2566         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2567         .idlest_bit     = OMAP2420_ST_VLYNQ_SHIFT,
2568         .recalc         = &followparent_recalc,
2569 };
2570
2571 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2572         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2573         { .div = 0 }
2574 };
2575
2576 static const struct clksel_rate vlynq_fck_core_rates[] = {
2577         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2578         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2579         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2580         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2581         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2582         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2583         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2584         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2585         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2586         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2587         { .div = 0 }
2588 };
2589
2590 static const struct clksel vlynq_fck_clksel[] = {
2591         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2592         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2593         { .parent = NULL }
2594 };
2595
2596 static struct clk vlynq_fck = {
2597         .name           = "vlynq_fck",
2598         .parent         = &func_96m_ck,
2599         .prcm_mod       = CORE_MOD,
2600         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | WAIT_READY,
2601         .clkdm          = { .name = "core_l3_clkdm" },
2602         .enable_reg     = CM_FCLKEN1,
2603         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2604         .idlest_bit     = OMAP2420_ST_VLYNQ_SHIFT,
2605         .init           = &omap2_init_clksel_parent,
2606         .clksel_reg     = CM_CLKSEL1,
2607         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2608         .clksel         = vlynq_fck_clksel,
2609         .recalc         = &omap2_clksel_recalc,
2610         .round_rate     = &omap2_clksel_round_rate,
2611         .set_rate       = &omap2_clksel_set_rate
2612 };
2613
2614 static struct clk sdrc_ick = {
2615         .name           = "sdrc_ick",
2616         .parent         = &l4_ck,
2617         .prcm_mod       = CORE_MOD,
2618         .flags          = CLOCK_IN_OMAP243X | WAIT_READY | ENABLE_ON_INIT,
2619         .clkdm          = { .name = "core_l4_clkdm" },
2620         .enable_reg     = CM_ICLKEN3,
2621         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2622         .idlest_bit     = OMAP2430_ST_SDRC_SHIFT,
2623         .recalc         = &followparent_recalc,
2624 };
2625
2626 static struct clk des_ick = {
2627         .name           = "des_ick",
2628         .parent         = &l4_ck,
2629         .prcm_mod       = CORE_MOD,
2630         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2631         .clkdm          = { .name = "core_l4_clkdm" },
2632         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2633         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2634         .idlest_bit     = OMAP24XX_ST_DES_SHIFT,
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static struct clk sha_ick = {
2639         .name           = "sha_ick",
2640         .parent         = &l4_ck,
2641         .prcm_mod       = CORE_MOD,
2642         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2643         .clkdm          = { .name = "core_l4_clkdm" },
2644         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2645         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2646         .idlest_bit     = OMAP24XX_ST_SHA_SHIFT,
2647         .recalc         = &followparent_recalc,
2648 };
2649
2650 static struct clk rng_ick = {
2651         .name           = "rng_ick",
2652         .parent         = &l4_ck,
2653         .prcm_mod       = CORE_MOD,
2654         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2655         .clkdm          = { .name = "core_l4_clkdm" },
2656         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2657         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2658         .idlest_bit     = OMAP24XX_ST_RNG_SHIFT,
2659         .recalc         = &followparent_recalc,
2660 };
2661
2662 static struct clk aes_ick = {
2663         .name           = "aes_ick",
2664         .parent         = &l4_ck,
2665         .prcm_mod       = CORE_MOD,
2666         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2667         .clkdm          = { .name = "core_l4_clkdm" },
2668         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2669         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2670         .idlest_bit     = OMAP24XX_ST_AES_SHIFT,
2671         .recalc         = &followparent_recalc,
2672 };
2673
2674 static struct clk pka_ick = {
2675         .name           = "pka_ick",
2676         .parent         = &l4_ck,
2677         .prcm_mod       = CORE_MOD,
2678         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2679         .clkdm          = { .name = "core_l4_clkdm" },
2680         .enable_reg     = OMAP24XX_CM_ICLKEN4,
2681         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2682         .idlest_bit     = OMAP24XX_ST_PKA_SHIFT,
2683         .recalc         = &followparent_recalc,
2684 };
2685
2686 static struct clk usb_fck = {
2687         .name           = "usb_fck",
2688         .parent         = &func_48m_ck,
2689         .prcm_mod       = CORE_MOD,
2690         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X | WAIT_READY,
2691         .clkdm          = { .name = "core_l3_clkdm" },
2692         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2693         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2694         .idlest_bit     = OMAP24XX_ST_USB_SHIFT,
2695         .recalc         = &followparent_recalc,
2696 };
2697
2698 static struct clk usbhs_ick = {
2699         .name           = "usbhs_ick",
2700         .parent         = &core_l3_ck,
2701         .prcm_mod       = CORE_MOD,
2702         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2703         .clkdm          = { .name = "core_l3_clkdm" },
2704         .enable_reg     = CM_ICLKEN2,
2705         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2706         .idlest_bit     = OMAP2430_ST_USBHS_SHIFT,
2707         .recalc         = &followparent_recalc,
2708 };
2709
2710 static struct clk mmchs1_ick = {
2711         .name           = "mmchs_ick",
2712         .parent         = &l4_ck,
2713         .prcm_mod       = CORE_MOD,
2714         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2715         .clkdm          = { .name = "core_l4_clkdm" },
2716         .enable_reg     = CM_ICLKEN2,
2717         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2718         .idlest_bit     = OMAP2430_ST_MMCHS1_SHIFT,
2719         .recalc         = &followparent_recalc,
2720 };
2721
2722 static struct clk mmchs1_fck = {
2723         .name           = "mmchs_fck",
2724         .parent         = &func_96m_ck,
2725         .prcm_mod       = CORE_MOD,
2726         .flags          = CLOCK_IN_OMAP243X,
2727         .clkdm          = { .name = "core_l3_clkdm" },
2728         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2729         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2730         .recalc         = &followparent_recalc,
2731 };
2732
2733 static struct clk mmchs2_ick = {
2734         .name           = "mmchs_ick",
2735         .id             = 1,
2736         .parent         = &l4_ck,
2737         .prcm_mod       = CORE_MOD,
2738         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2739         .clkdm          = { .name = "core_l4_clkdm" },
2740         .enable_reg     = CM_ICLKEN2,
2741         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2742         .idlest_bit     = OMAP2430_ST_MMCHS2_SHIFT,
2743         .recalc         = &followparent_recalc,
2744 };
2745
2746 static struct clk mmchs2_fck = {
2747         .name           = "mmchs_fck",
2748         .id             = 1,
2749         .parent         = &func_96m_ck,
2750         .prcm_mod       = CORE_MOD,
2751         .flags          = CLOCK_IN_OMAP243X,
2752         .clkdm          = { .name = "core_l4_clkdm" },
2753         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2754         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2755         .recalc         = &followparent_recalc,
2756 };
2757
2758 static struct clk gpio5_ick = {
2759         .name           = "gpio5_ick",
2760         .parent         = &l4_ck,
2761         .prcm_mod       = CORE_MOD,
2762         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2763         .clkdm          = { .name = "core_l4_clkdm" },
2764         .enable_reg     = CM_ICLKEN2,
2765         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2766         .idlest_bit     = OMAP2430_ST_GPIO5_SHIFT,
2767         .recalc         = &followparent_recalc,
2768 };
2769
2770 static struct clk gpio5_fck = {
2771         .name           = "gpio5_fck",
2772         .parent         = &func_32k_ck,
2773         .prcm_mod       = CORE_MOD,
2774         .flags          = CLOCK_IN_OMAP243X,
2775         .clkdm          = { .name = "core_l4_clkdm" },
2776         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2777         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2778         .recalc         = &followparent_recalc,
2779 };
2780
2781 static struct clk mdm_intc_ick = {
2782         .name           = "mdm_intc_ick",
2783         .parent         = &l4_ck,
2784         .prcm_mod       = CORE_MOD,
2785         .flags          = CLOCK_IN_OMAP243X | WAIT_READY,
2786         .clkdm          = { .name = "core_l4_clkdm" },
2787         .enable_reg     = CM_ICLKEN2,
2788         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2789         .idlest_bit     = OMAP2430_ST_MDM_INTC_SHIFT,
2790         .recalc         = &followparent_recalc,
2791 };
2792
2793 static struct clk mmchsdb1_fck = {
2794         .name           = "mmchsdb_fck",
2795         .parent         = &func_32k_ck,
2796         .prcm_mod       = CORE_MOD,
2797         .flags          = CLOCK_IN_OMAP243X,
2798         .clkdm          = { .name = "core_l4_clkdm" },
2799         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2800         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2801         .recalc         = &followparent_recalc,
2802 };
2803
2804 static struct clk mmchsdb2_fck = {
2805         .name           = "mmchsdb_fck",
2806         .id             = 1,
2807         .parent         = &func_32k_ck,
2808         .prcm_mod       = CORE_MOD,
2809         .flags          = CLOCK_IN_OMAP243X,
2810         .clkdm          = { .name = "core_l4_clkdm" },
2811         .enable_reg     = OMAP24XX_CM_FCLKEN2,
2812         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2813         .recalc         = &followparent_recalc,
2814 };
2815
2816 /*
2817  * This clock is a composite clock which does entire set changes then
2818  * forces a rebalance. It keys on the MPU speed, but it really could
2819  * be any key speed part of a set in the rate table.
2820  *
2821  * to really change a set, you need memory table sets which get changed
2822  * in sram, pre-notifiers & post notifiers, changing the top set, without
2823  * having low level display recalc's won't work... this is why dpm notifiers
2824  * work, isr's off, walk a list of clocks already _off_ and not messing with
2825  * the bus.
2826  *
2827  * This clock should have no parent. It embodies the entire upper level
2828  * active set. A parent will mess up some of the init also.
2829  */
2830 static struct clk virt_prcm_set = {
2831         .name           = "virt_prcm_set",
2832         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2833                                 ALWAYS_ENABLED | DELAYED_APP,
2834         .clkdm          = { .name = "virt_opp_clkdm" },
2835         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2836         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2837         .set_rate       = &omap2_select_table_rate,
2838         .round_rate     = &omap2_round_to_table_rate,
2839 };
2840
2841 static struct clk *onchip_24xx_clks[] __initdata = {
2842         /* external root sources */
2843         &func_32k_ck,
2844         &osc_ck,
2845         &sys_ck,
2846         &alt_ck,
2847         /* internal analog sources */
2848         &dpll_ck,
2849         &apll96_ck,
2850         &apll54_ck,
2851         /* internal prcm root sources */
2852         &func_54m_ck,
2853         &core_ck,
2854         &func_96m_ck,
2855         &func_48m_ck,
2856         &func_12m_ck,
2857         &wdt1_osc_ck,
2858         &sys_clkout_src,
2859         &sys_clkout,
2860         &sys_clkout2_src,
2861         &sys_clkout2,
2862         &emul_ck,
2863         /* mpu domain clocks */
2864         &mpu_ck,
2865         /* dsp domain clocks */
2866         &dsp_fck,
2867         &dsp_irate_ick,
2868         &dsp_ick,               /* 242x */
2869         &iva2_1_ick,            /* 243x */
2870         &iva1_ifck,             /* 242x */
2871         &iva1_mpu_int_ifck,     /* 242x */
2872         /* GFX domain clocks */
2873         &gfx_3d_fck,
2874         &gfx_2d_fck,
2875         &gfx_ick,
2876         /* Modem domain clocks */
2877         &mdm_ick,
2878         &mdm_osc_ck,
2879         /* DSS domain clocks */
2880         &dss_ick,
2881         &dss1_fck,
2882         &dss2_fck,
2883         &dss_54m_fck,
2884         /* L3 domain clocks */
2885         &core_l3_ck,
2886         &ssi_ssr_sst_fck,
2887         &usb_l4_ick,
2888         /* L4 domain clocks */
2889         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2890         &ssi_l4_ick,
2891         /* virtual meta-group clock */
2892         &virt_prcm_set,
2893         /* general l4 interface ck, multi-parent functional clk */
2894         &gpt1_ick,
2895         &gpt1_fck,
2896         &gpt2_ick,
2897         &gpt2_fck,
2898         &gpt3_ick,
2899         &gpt3_fck,
2900         &gpt4_ick,
2901         &gpt4_fck,
2902         &gpt5_ick,
2903         &gpt5_fck,
2904         &gpt6_ick,
2905         &gpt6_fck,
2906         &gpt7_ick,
2907         &gpt7_fck,
2908         &gpt8_ick,
2909         &gpt8_fck,
2910         &gpt9_ick,
2911         &gpt9_fck,
2912         &gpt10_ick,
2913         &gpt10_fck,
2914         &gpt11_ick,
2915         &gpt11_fck,
2916         &gpt12_ick,
2917         &gpt12_fck,
2918         &mcbsp1_ick,
2919         &mcbsp1_fck,
2920         &mcbsp2_ick,
2921         &mcbsp2_fck,
2922         &mcbsp3_ick,
2923         &mcbsp3_fck,
2924         &mcbsp4_ick,
2925         &mcbsp4_fck,
2926         &mcbsp5_ick,
2927         &mcbsp5_fck,
2928         &mcspi1_ick,
2929         &mcspi1_fck,
2930         &mcspi2_ick,
2931         &mcspi2_fck,
2932         &mcspi3_ick,
2933         &mcspi3_fck,
2934         &uart1_ick,
2935         &uart1_fck,
2936         &uart2_ick,
2937         &uart2_fck,
2938         &uart3_ick,
2939         &uart3_fck,
2940         &gpios_ick,
2941         &gpios_fck,
2942         &mpu_wdt_ick,
2943         &mpu_wdt_fck,
2944         &sync_32k_ick,
2945         &wdt1_ick,
2946         &omapctrl_ick,
2947         &icr_ick,
2948         &cam_fck,
2949         &cam_ick,
2950         &mailboxes_ick,
2951         &wdt4_ick,
2952         &wdt4_fck,
2953         &wdt3_ick,
2954         &wdt3_fck,
2955         &mspro_ick,
2956         &mspro_fck,
2957         &mmc_ick,
2958         &mmc_fck,
2959         &fac_ick,
2960         &fac_fck,
2961         &eac_ick,
2962         &eac_fck,
2963         &hdq_ick,
2964         &hdq_fck,
2965         &i2c1_ick,
2966         &i2c1_fck,
2967         &i2chs1_fck,
2968         &i2c2_ick,
2969         &i2c2_fck,
2970         &i2chs2_fck,
2971         &gpmc_fck,
2972         &sdma_fck,
2973         &sdma_ick,
2974         &vlynq_ick,
2975         &vlynq_fck,
2976         &sdrc_ick,
2977         &des_ick,
2978         &sha_ick,
2979         &rng_ick,
2980         &aes_ick,
2981         &pka_ick,
2982         &usb_fck,
2983         &usbhs_ick,
2984         &mmchs1_ick,
2985         &mmchs1_fck,
2986         &mmchs2_ick,
2987         &mmchs2_fck,
2988         &gpio5_ick,
2989         &gpio5_fck,
2990         &mdm_intc_ick,
2991         &mmchsdb1_fck,
2992         &mmchsdb2_fck,
2993 };
2994
2995 #endif
2996