arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  23
  24 #include "clock.h"
  25
  26 #include "prm.h"
  27 #include "cm.h"
  28 #include "prm_regbits_24xx.h"
  29 #include "cm_regbits_24xx.h"
  30 #include "sdrc.h"
  31
  32 static void omap2_table_mpu_recalc(struct clk *clk);
  33 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  34 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  35 static void omap2_sys_clk_recalc(struct clk *clk);
  36 static void omap2_osc_clk_recalc(struct clk *clk);
  37 static void omap2_sys_clk_recalc(struct clk *clk);
  38 static void omap2_dpll_recalc(struct clk *clk);
  39 static int omap2_clk_fixed_enable(struct clk *clk);
  40 static void omap2_clk_fixed_disable(struct clk *clk);
  41 static int omap2_enable_osc_ck(struct clk *clk);
  42 static void omap2_disable_osc_ck(struct clk *clk);
  43 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
  44
  45 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  46  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  47  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  48  */
  49 struct prcm_config {
  50         unsigned long xtal_speed;       /* crystal rate */
  51         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  52         unsigned long mpu_speed;        /* speed of MPU */
  53         unsigned long cm_clksel_mpu;    /* mpu divider */
  54         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  55         unsigned long cm_clksel_gfx;    /* gfx dividers */
  56         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  57         unsigned long cm_clksel1_pll;   /* m,n */
  58         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  59         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  60         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  61         unsigned char flags;
  62 };
  63
  64 /*
  65  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  66  * These configurations are characterized by voltage and speed for clocks.
  67  * The device is only validated for certain combinations. One way to express
  68  * these combinations is via the 'ratio's' which the clocks operate with
  69  * respect to each other. These ratio sets are for a given voltage/DPLL
  70  * setting. All configurations can be described by a DPLL setting and a ratio
  71  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  72  *
  73  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  74  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  75  * 2430 (iva2.1, NOdsp, mdm)
  76  */
  77
  78 /* Core fields for cm_clksel, not ratio governed */
  79 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  80 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  81 #define RX_CLKSEL_SSI                   (0x5 << 20)
  82
  83 /*-------------------------------------------------------------------------
  84  * Voltage/DPLL ratios
  85  *-------------------------------------------------------------------------*/
  86
  87 /* 2430 Ratio's, 2430-Ratio Config 1 */
  88 #define R1_CLKSEL_L3                    (4 << 0)
  89 #define R1_CLKSEL_L4                    (2 << 5)
  90 #define R1_CLKSEL_USB                   (4 << 25)
  91 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  92                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  93                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  94 #define R1_CLKSEL_MPU                   (2 << 0)
  95 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  96 #define R1_CLKSEL_DSP                   (2 << 0)
  97 #define R1_CLKSEL_DSP_IF                (2 << 5)
  98 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  99 #define R1_CLKSEL_GFX                   (2 << 0)
 100 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 101 #define R1_CLKSEL_MDM                   (4 << 0)
 102 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 103
 104 /* 2430-Ratio Config 2 */
 105 #define R2_CLKSEL_L3                    (6 << 0)
 106 #define R2_CLKSEL_L4                    (2 << 5)
 107 #define R2_CLKSEL_USB                   (2 << 25)
 108 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 109                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 110                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 111 #define R2_CLKSEL_MPU                   (2 << 0)
 112 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 113 #define R2_CLKSEL_DSP                   (2 << 0)
 114 #define R2_CLKSEL_DSP_IF                (3 << 5)
 115 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 116 #define R2_CLKSEL_GFX                   (2 << 0)
 117 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 118 #define R2_CLKSEL_MDM                   (6 << 0)
 119 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 120
 121 /* 2430-Ratio Bootm (BYPASS) */
 122 #define RB_CLKSEL_L3                    (1 << 0)
 123 #define RB_CLKSEL_L4                    (1 << 5)
 124 #define RB_CLKSEL_USB                   (1 << 25)
 125 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 126                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 127                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 128 #define RB_CLKSEL_MPU                   (1 << 0)
 129 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 130 #define RB_CLKSEL_DSP                   (1 << 0)
 131 #define RB_CLKSEL_DSP_IF                (1 << 5)
 132 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 133 #define RB_CLKSEL_GFX                   (1 << 0)
 134 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 135 #define RB_CLKSEL_MDM                   (1 << 0)
 136 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 137
 138 /* 2420 Ratio Equivalents */
 139 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 140 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 141
 142 /* 2420-PRCM III 532MHz core */
 143 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 144 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 145 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 146 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 147                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 148                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 149                                         RIII_CLKSEL_L3
 150 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 151 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 152 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 153 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 154 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 155 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 156 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 157 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 158                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 159                                         RIII_CLKSEL_DSP
 160 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 161 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 162
 163 /* 2420-PRCM II 600MHz core */
 164 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 165 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 166 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 167 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 168                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 169                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 170                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 171 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 172 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 173 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 174 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 175 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 176 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 177 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 178 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 179                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 180                                         RII_CLKSEL_DSP
 181 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 182 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 183
 184 /* 2420-PRCM I 660MHz core */
 185 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 186 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 187 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 188 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 189                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 190                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 191                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 192 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 193 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 194 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 195 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 196 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 197 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 198 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 199 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 200                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 201                                         RI_CLKSEL_DSP
 202 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 203 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 204
 205 /* 2420-PRCM VII (boot) */
 206 #define RVII_CLKSEL_L3                  (1 << 0)
 207 #define RVII_CLKSEL_L4                  (1 << 5)
 208 #define RVII_CLKSEL_DSS1                (1 << 8)
 209 #define RVII_CLKSEL_DSS2                (0 << 13)
 210 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 211 #define RVII_CLKSEL_SSI                 (1 << 20)
 212 #define RVII_CLKSEL_USB                 (1 << 25)
 213
 214 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 215                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 216                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 217
 218 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 219 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 220
 221 #define RVII_CLKSEL_DSP                 (1 << 0)
 222 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 223 #define RVII_SYNC_DSP                   (0 << 7)
 224 #define RVII_CLKSEL_IVA                 (1 << 8)
 225 #define RVII_SYNC_IVA                   (0 << 13)
 226 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 227                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 228
 229 #define RVII_CLKSEL_GFX                 (1 << 0)
 230 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 231
 232 /*-------------------------------------------------------------------------
 233  * 2430 Target modes: Along with each configuration the CPU has several
 234  * modes which goes along with them. Modes mainly are the addition of
 235  * describe DPLL combinations to go along with a ratio.
 236  *-------------------------------------------------------------------------*/
 237
 238 /* Hardware governed */
 239 #define MX_48M_SRC                      (0 << 3)
 240 #define MX_54M_SRC                      (0 << 5)
 241 #define MX_APLLS_CLIKIN_12              (3 << 23)
 242 #define MX_APLLS_CLIKIN_13              (2 << 23)
 243 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 244
 245 /*
 246  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 247  * #2   (ratio1) baseport-target
 248  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 249  */
 250 #define M5A_DPLL_MULT_12                (133 << 12)
 251 #define M5A_DPLL_DIV_12                 (5 << 8)
 252 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 253                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 254                                         MX_APLLS_CLIKIN_12
 255 #define M5A_DPLL_MULT_13                (266 << 12)
 256 #define M5A_DPLL_DIV_13                 (12 << 8)
 257 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 258                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 259                                         MX_APLLS_CLIKIN_13
 260 #define M5A_DPLL_MULT_19                (180 << 12)
 261 #define M5A_DPLL_DIV_19                 (12 << 8)
 262 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 264                                         MX_APLLS_CLIKIN_19_2
 265 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 266 #define M5B_DPLL_MULT_12                (50 << 12)
 267 #define M5B_DPLL_DIV_12                 (2 << 8)
 268 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 270                                         MX_APLLS_CLIKIN_12
 271 #define M5B_DPLL_MULT_13                (200 << 12)
 272 #define M5B_DPLL_DIV_13                 (12 << 8)
 273
 274 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 275                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 276                                         MX_APLLS_CLIKIN_13
 277 #define M5B_DPLL_MULT_19                (125 << 12)
 278 #define M5B_DPLL_DIV_19                 (31 << 8)
 279 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 280                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 281                                         MX_APLLS_CLIKIN_19_2
 282 /*
 283  * #4   (ratio2)
 284  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 285  */
 286 #define M3_DPLL_MULT_12                 (55 << 12)
 287 #define M3_DPLL_DIV_12                  (1 << 8)
 288 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 289                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 290                                         MX_APLLS_CLIKIN_12
 291 #define M3_DPLL_MULT_13                 (330 << 12)
 292 #define M3_DPLL_DIV_13                  (12 << 8)
 293 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 295                                         MX_APLLS_CLIKIN_13
 296 #define M3_DPLL_MULT_19                 (275 << 12)
 297 #define M3_DPLL_DIV_19                  (15 << 8)
 298 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 299                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 300                                         MX_APLLS_CLIKIN_19_2
 301 /* boot (boot) */
 302 #define MB_DPLL_MULT                    (1 << 12)
 303 #define MB_DPLL_DIV                     (0 << 8)
 304 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 305                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 306
 307 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 308                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 309
 310 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 311                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 312
 313 /*
 314  * 2430 - chassis (sedna)
 315  * 165 (ratio1) same as above #2
 316  * 150 (ratio1)
 317  * 133 (ratio2) same as above #4
 318  * 110 (ratio2) same as above #3
 319  * 104 (ratio2)
 320  * boot (boot)
 321  */
 322
 323 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 324 #define MI_DPLL_MULT_12                 (55 << 12)
 325 #define MI_DPLL_DIV_12                  (1 << 8)
 326 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 327                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 328                                         MX_APLLS_CLIKIN_12
 329
 330 /*
 331  * 2420 Equivalent - mode registers
 332  * PRCM II , target DPLL = 2*300MHz = 600MHz
 333  */
 334 #define MII_DPLL_MULT_12                (50 << 12)
 335 #define MII_DPLL_DIV_12                 (1 << 8)
 336 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 337                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 338                                         MX_APLLS_CLIKIN_12
 339 #define MII_DPLL_MULT_13                (300 << 12)
 340 #define MII_DPLL_DIV_13                 (12 << 8)
 341 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 342                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 343                                         MX_APLLS_CLIKIN_13
 344
 345 /* PRCM III target DPLL = 2*266 = 532MHz*/
 346 #define MIII_DPLL_MULT_12               (133 << 12)
 347 #define MIII_DPLL_DIV_12                (5 << 8)
 348 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 349                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 350                                         MX_APLLS_CLIKIN_12
 351 #define MIII_DPLL_MULT_13               (266 << 12)
 352 #define MIII_DPLL_DIV_13                (12 << 8)
 353 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 354                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 355                                         MX_APLLS_CLIKIN_13
 356
 357 /* PRCM VII (boot bypass) */
 358 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 359 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 360
 361 /* High and low operation value */
 362 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 363 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 364
 365 /* MPU speed defines */
 366 #define S12M    12000000
 367 #define S13M    13000000
 368 #define S19M    19200000
 369 #define S26M    26000000
 370 #define S100M   100000000
 371 #define S133M   133000000
 372 #define S150M   150000000
 373 #define S165M   165000000
 374 #define S200M   200000000
 375 #define S266M   266000000
 376 #define S300M   300000000
 377 #define S330M   330000000
 378 #define S400M   400000000
 379 #define S532M   532000000
 380 #define S600M   600000000
 381 #define S660M   660000000
 382
 383 /*-------------------------------------------------------------------------
 384  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 385  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 386  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 387  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 388  *
 389  * Filling in table based on H4 boards and 2430-SDPs variants available.
 390  * There are quite a few more rates combinations which could be defined.
 391  *
 392  * When multiple values are defined the start up will try and choose the
 393  * fastest one. If a 'fast' value is defined, then automatically, the /2
 394  * one should be included as it can be used.    Generally having more that
 395  * one fast set does not make sense, as static timings need to be changed
 396  * to change the set.    The exception is the bypass setting which is
 397  * availble for low power bypass.
 398  *
 399  * Note: This table needs to be sorted, fastest to slowest.
 400  *-------------------------------------------------------------------------*/
 401 static struct prcm_config rate_table[] = {
 402         /* PRCM I - FAST */
 403         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 404                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 405                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 406                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 407                 RATE_IN_242X},
 408
 409         /* PRCM II - FAST */
 410         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 411                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 412                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 413                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 414                 RATE_IN_242X},
 415
 416         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 417                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 418                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 419                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 420                 RATE_IN_242X},
 421
 422         /* PRCM III - FAST */
 423         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 424                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 425                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 426                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 427                 RATE_IN_242X},
 428
 429         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 430                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 431                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 432                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 433                 RATE_IN_242X},
 434
 435         /* PRCM II - SLOW */
 436         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 437                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 438                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 439                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 440                 RATE_IN_242X},
 441
 442         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 443                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 444                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 445                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 446                 RATE_IN_242X},
 447
 448         /* PRCM III - SLOW */
 449         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 450                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 451                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 452                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 453                 RATE_IN_242X},
 454
 455         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 456                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 457                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 459                 RATE_IN_242X},
 460
 461         /* PRCM-VII (boot-bypass) */
 462         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 463                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 464                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 465                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 466                 RATE_IN_242X},
 467
 468         /* PRCM-VII (boot-bypass) */
 469         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 470                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 471                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 472                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 473                 RATE_IN_242X},
 474
 475         /* PRCM #3 - ratio2 (ES2) - FAST */
 476         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 477                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 478                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 479                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 480                 SDRC_RFR_CTRL_110MHz,
 481                 RATE_IN_243X},
 482
 483         /* PRCM #5a - ratio1 - FAST */
 484         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 485                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 486                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 487                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 488                 SDRC_RFR_CTRL_133MHz,
 489                 RATE_IN_243X},
 490
 491         /* PRCM #5b - ratio1 - FAST */
 492         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 493                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 494                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 495                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 496                 SDRC_RFR_CTRL_100MHz,
 497                 RATE_IN_243X},
 498
 499         /* PRCM #3 - ratio2 (ES2) - SLOW */
 500         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 501                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 502                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 504                 SDRC_RFR_CTRL_110MHz,
 505                 RATE_IN_243X},
 506
 507         /* PRCM #5a - ratio1 - SLOW */
 508         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 509                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 510                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 511                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 512                 SDRC_RFR_CTRL_133MHz,
 513                 RATE_IN_243X},
 514
 515         /* PRCM #5b - ratio1 - SLOW*/
 516         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 517                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 518                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 519                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 520                 SDRC_RFR_CTRL_100MHz,
 521                 RATE_IN_243X},
 522
 523         /* PRCM-boot/bypass */
 524         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 525                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 526                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 527                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 528                 SDRC_RFR_CTRL_BYPASS,
 529                 RATE_IN_243X},
 530
 531         /* PRCM-boot/bypass */
 532         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 533                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 534                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 535                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 536                 SDRC_RFR_CTRL_BYPASS,
 537                 RATE_IN_243X},
 538
 539         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 540 };
 541
 542 /*-------------------------------------------------------------------------
 543  * 24xx clock tree.
 544  *
 545  * NOTE:In many cases here we are assigning a 'default' parent. In many
 546  *      cases the parent is selectable. The get/set parent calls will also
 547  *      switch sources.
 548  *
 549  *      Many some clocks say always_enabled, but they can be auto idled for
 550  *      power savings. They will always be available upon clock request.
 551  *
 552  *      Several sources are given initial rates which may be wrong, this will
 553  *      be fixed up in the init func.
 554  *
 555  *      Things are broadly separated below by clock domains. It is
 556  *      noteworthy that most periferals have dependencies on multiple clock
 557  *      domains. Many get their interface clocks from the L4 domain, but get
 558  *      functional clocks from fixed sources or other core domain derived
 559  *      clocks.
 560  *-------------------------------------------------------------------------*/
 561
 562 /* Base external input clocks */
 563 static struct clk func_32k_ck = {
 564         .name           = "func_32k_ck",
 565         .rate           = 32000,
 566         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 567                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 568         .recalc         = &propagate_rate,
 569 };
 570
 571 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 572 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 573         .name           = "osc_ck",
 574         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 575                                 RATE_PROPAGATES,
 576         .enable         = &omap2_enable_osc_ck,
 577         .disable        = &omap2_disable_osc_ck,
 578         .recalc         = &omap2_osc_clk_recalc,
 579 };
 580
 581 /* With out modem likely 12MHz, with modem likely 13MHz */
 582 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 583         .name           = "sys_ck",             /* ~ ref_clk also */
 584         .rate           = 13000000,
 585         .parent         = &osc_ck,
 586         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 587                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 588         .recalc         = &omap2_sys_clk_recalc,
 589 };
 590
 591 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 592         .name           = "alt_ck",
 593         .rate           = 54000000,
 594         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 595                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 596         .recalc         = &propagate_rate,
 597 };
 598
 599 /*
 600  * Analog domain root source clocks
 601  */
 602
 603 /* dpll_ck, is broken out in to special cases through clksel */
 604 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 605  * deal with this
 606  */
 607
 608 static const struct dpll_data dpll_dd = {
 609         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 610         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 611         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 612 };
 613
 614 static struct clk dpll_ck = {
 615         .name           = "dpll_ck",
 616         .parent         = &sys_ck,              /* Can be func_32k also */
 617         .dpll_data      = &dpll_dd,
 618         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 619                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 620         .recalc         = &omap2_dpll_recalc,
 621         .set_rate       = &omap2_reprogram_dpll,
 622 };
 623
 624 static struct clk apll96_ck = {
 625         .name           = "apll96_ck",
 626         .parent         = &sys_ck,
 627         .rate           = 96000000,
 628         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 629                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 630         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 631         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 632         .enable         = &omap2_clk_fixed_enable,
 633         .disable        = &omap2_clk_fixed_disable,
 634         .recalc         = &propagate_rate,
 635 };
 636
 637 static struct clk apll54_ck = {
 638         .name           = "apll54_ck",
 639         .parent         = &sys_ck,
 640         .rate           = 54000000,
 641         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 642                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 643         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 644         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 645         .enable         = &omap2_clk_fixed_enable,
 646         .disable        = &omap2_clk_fixed_disable,
 647         .recalc         = &propagate_rate,
 648 };
 649
 650 /*
 651  * PRCM digital base sources
 652  */
 653
 654 /* func_54m_ck */
 655
 656 static const struct clksel_rate func_54m_apll54_rates[] = {
 657         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 658         { .div = 0 },
 659 };
 660
 661 static const struct clksel_rate func_54m_alt_rates[] = {
 662         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 663         { .div = 0 },
 664 };
 665
 666 static const struct clksel func_54m_clksel[] = {
 667         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 668         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 669         { .parent = NULL },
 670 };
 671
 672 static struct clk func_54m_ck = {
 673         .name           = "func_54m_ck",
 674         .parent         = &apll54_ck,   /* can also be alt_clk */
 675         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 676                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 677         .init           = &omap2_init_clksel_parent,
 678         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 679         .clksel_mask    = OMAP24XX_54M_SOURCE,
 680         .clksel         = func_54m_clksel,
 681         .recalc         = &omap2_clksel_recalc,
 682 };
 683
 684 static struct clk core_ck = {
 685         .name           = "core_ck",
 686         .parent         = &dpll_ck,             /* can also be 32k */
 687         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 688                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 689         .recalc         = &followparent_recalc,
 690 };
 691
 692 /* func_96m_ck */
 693 static const struct clksel_rate func_96m_apll96_rates[] = {
 694         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 695         { .div = 0 },
 696 };
 697
 698 static const struct clksel_rate func_96m_alt_rates[] = {
 699         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 700         { .div = 0 },
 701 };
 702
 703 static const struct clksel func_96m_clksel[] = {
 704         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 705         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 706         { .parent = NULL }
 707 };
 708
 709 /* The parent of this clock is not selectable on 2420. */
 710 static struct clk func_96m_ck = {
 711         .name           = "func_96m_ck",
 712         .parent         = &apll96_ck,
 713         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 714                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 715         .init           = &omap2_init_clksel_parent,
 716         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 717         .clksel_mask    = OMAP2430_96M_SOURCE,
 718         .clksel         = func_96m_clksel,
 719         .recalc         = &omap2_clksel_recalc,
 720         .round_rate     = &omap2_clksel_round_rate,
 721         .set_rate       = &omap2_clksel_set_rate
 722 };
 723
 724 /* func_48m_ck */
 725
 726 static const struct clksel_rate func_48m_apll96_rates[] = {
 727         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 728         { .div = 0 },
 729 };
 730
 731 static const struct clksel_rate func_48m_alt_rates[] = {
 732         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 733         { .div = 0 },
 734 };
 735
 736 static const struct clksel func_48m_clksel[] = {
 737         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 738         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 739         { .parent = NULL }
 740 };
 741
 742 static struct clk func_48m_ck = {
 743         .name           = "func_48m_ck",
 744         .parent         = &apll96_ck,    /* 96M or Alt */
 745         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 746                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 747         .init           = &omap2_init_clksel_parent,
 748         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 749         .clksel_mask    = OMAP24XX_48M_SOURCE,
 750         .clksel         = func_48m_clksel,
 751         .recalc         = &omap2_clksel_recalc,
 752         .round_rate     = &omap2_clksel_round_rate,
 753         .set_rate       = &omap2_clksel_set_rate
 754 };
 755
 756 static struct clk func_12m_ck = {
 757         .name           = "func_12m_ck",
 758         .parent         = &func_48m_ck,
 759         .fixed_div      = 4,
 760         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 761                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 762         .recalc         = &omap2_fixed_divisor_recalc,
 763 };
 764
 765 /* Secure timer, only available in secure mode */
 766 static struct clk wdt1_osc_ck = {
 767         .name           = "ck_wdt1_osc",
 768         .parent         = &osc_ck,
 769         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 770         .recalc         = &followparent_recalc,
 771 };
 772
 773 /*
 774  * The common_clkout* clksel_rate structs are common to
 775  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 776  * sys_clkout2_* are 2420-only, so the
 777  * clksel_rate flags fields are inaccurate for those clocks. This is
 778  * harmless since access to those clocks are gated by the struct clk
 779  * flags fields, which mark them as 2420-only.
 780  */
 781 static const struct clksel_rate common_clkout_src_core_rates[] = {
 782         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 783         { .div = 0 }
 784 };
 785
 786 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 787         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 788         { .div = 0 }
 789 };
 790
 791 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 792         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 793         { .div = 0 }
 794 };
 795
 796 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 797         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 798         { .div = 0 }
 799 };
 800
 801 static const struct clksel common_clkout_src_clksel[] = {
 802         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 803         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 804         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 805         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 806         { .parent = NULL }
 807 };
 808
 809 static struct clk sys_clkout_src = {
 810         .name           = "sys_clkout_src",
 811         .parent         = &func_54m_ck,
 812         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 813                                 RATE_PROPAGATES,
 814         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 815         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 816         .init           = &omap2_init_clksel_parent,
 817         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 818         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 819         .clksel         = common_clkout_src_clksel,
 820         .recalc         = &omap2_clksel_recalc,
 821         .round_rate     = &omap2_clksel_round_rate,
 822         .set_rate       = &omap2_clksel_set_rate
 823 };
 824
 825 static const struct clksel_rate common_clkout_rates[] = {
 826         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 827         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 828         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 829         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 830         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 831         { .div = 0 },
 832 };
 833
 834 static const struct clksel sys_clkout_clksel[] = {
 835         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 836         { .parent = NULL }
 837 };
 838
 839 static struct clk sys_clkout = {
 840         .name           = "sys_clkout",
 841         .parent         = &sys_clkout_src,
 842         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 843                                 PARENT_CONTROLS_CLOCK,
 844         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 845         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 846         .clksel         = sys_clkout_clksel,
 847         .recalc         = &omap2_clksel_recalc,
 848         .round_rate     = &omap2_clksel_round_rate,
 849         .set_rate       = &omap2_clksel_set_rate
 850 };
 851
 852 /* In 2430, new in 2420 ES2 */
 853 static struct clk sys_clkout2_src = {
 854         .name           = "sys_clkout2_src",
 855         .parent         = &func_54m_ck,
 856         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 857         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 858         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 859         .init           = &omap2_init_clksel_parent,
 860         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 861         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 862         .clksel         = common_clkout_src_clksel,
 863         .recalc         = &omap2_clksel_recalc,
 864         .round_rate     = &omap2_clksel_round_rate,
 865         .set_rate       = &omap2_clksel_set_rate
 866 };
 867
 868 static const struct clksel sys_clkout2_clksel[] = {
 869         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 870         { .parent = NULL }
 871 };
 872
 873 /* In 2430, new in 2420 ES2 */
 874 static struct clk sys_clkout2 = {
 875         .name           = "sys_clkout2",
 876         .parent         = &sys_clkout2_src,
 877         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 878         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 879         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 880         .clksel         = sys_clkout2_clksel,
 881         .recalc         = &omap2_clksel_recalc,
 882         .round_rate     = &omap2_clksel_round_rate,
 883         .set_rate       = &omap2_clksel_set_rate
 884 };
 885
 886 static struct clk emul_ck = {
 887         .name           = "emul_ck",
 888         .parent         = &func_54m_ck,
 889         .flags          = CLOCK_IN_OMAP242X,
 890         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 891         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 892         .recalc         = &followparent_recalc,
 893
 894 };
 895
 896 /*
 897  * MPU clock domain
 898  *      Clocks:
 899  *              MPU_FCLK, MPU_ICLK
 900  *              INT_M_FCLK, INT_M_I_CLK
 901  *
 902  * - Individual clocks are hardware managed.
 903  * - Base divider comes from: CM_CLKSEL_MPU
 904  *
 905  */
 906 static const struct clksel_rate mpu_core_rates[] = {
 907         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 908         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 909         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 910         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 911         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 912         { .div = 0 },
 913 };
 914
 915 static const struct clksel mpu_clksel[] = {
 916         { .parent = &core_ck, .rates = mpu_core_rates },
 917         { .parent = NULL }
 918 };
 919
 920 static struct clk mpu_ck = {    /* Control cpu */
 921         .name           = "mpu_ck",
 922         .parent         = &core_ck,
 923         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 924                                 ALWAYS_ENABLED | DELAYED_APP |
 925                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 926         .init           = &omap2_init_clksel_parent,
 927         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 928         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 929         .clksel         = mpu_clksel,
 930         .recalc         = &omap2_clksel_recalc,
 931         .round_rate     = &omap2_clksel_round_rate,
 932         .set_rate       = &omap2_clksel_set_rate
 933 };
 934
 935 /*
 936  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 937  * Clocks:
 938  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 939  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 940  */
 941 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 942  * they should just be treated as such.
 943  */
 944
 945 /* iva2_1_fck */
 946 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 947         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 948         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 949         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 950         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 951         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 952         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 953         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 954         { .div = 0 },
 955 };
 956
 957 static const struct clksel iva2_1_fck_clksel[] = {
 958         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 959         { .parent = NULL }
 960 };
 961
 962 static struct clk iva2_1_fck = {
 963         .name           = "iva2_1_fck",
 964         .parent         = &core_ck,
 965         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
 966                                 CONFIG_PARTICIPANT,
 967         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 968         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 969         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 970         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 971         .clksel         = iva2_1_fck_clksel,
 972         .recalc         = &omap2_clksel_recalc,
 973         .round_rate     = &omap2_clksel_round_rate,
 974         .set_rate       = &omap2_clksel_set_rate
 975 };
 976
 977 /* iva2_1_ick */
 978 static const struct clksel_rate iva2_1_ick_core_rates[] = {
 979         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 980         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 981         { .div = 3, .val = 3, .flags = RATE_IN_243X },
 982         { .div = 0 },
 983 };
 984
 985 static const struct clksel iva2_1_ick_clksel[] = {
 986         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
 987         { .parent = NULL }
 988 };
 989
 990 static struct clk iva2_1_ick = {
 991         .name           = "iva2_1_ick",
 992         .parent         = &iva2_1_fck,
 993         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
 994         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 995         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
 996         .clksel         = iva2_1_ick_clksel,
 997         .recalc         = &omap2_clksel_recalc,
 998         .round_rate     = &omap2_clksel_round_rate,
 999         .set_rate       = &omap2_clksel_set_rate
1000 };
1001
1002 /*
1003  * Won't be too specific here. The core clock comes into this block
1004  * it is divided then tee'ed. One branch goes directly to xyz enable
1005  * controls. The other branch gets further divided by 2 then possibly
1006  * routed into a synchronizer and out of clocks abc.
1007  */
1008 static const struct clksel_rate dsp_fck_core_rates[] = {
1009         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1010         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1011         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1012         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1013         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1014         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1015         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1016         { .div = 0 },
1017 };
1018
1019 static const struct clksel dsp_fck_clksel[] = {
1020         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1021         { .parent = NULL }
1022 };
1023
1024 static struct clk dsp_fck = {
1025         .name           = "dsp_fck",
1026         .parent         = &core_ck,
1027         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP |
1028                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1029         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1030         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1031         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1032         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1033         .clksel         = dsp_fck_clksel,
1034         .recalc         = &omap2_clksel_recalc,
1035         .round_rate     = &omap2_clksel_round_rate,
1036         .set_rate       = &omap2_clksel_set_rate
1037 };
1038
1039 static const struct clksel_rate dsp_ick_core_rates[] = {
1040         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1041         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1042         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1043         { .div = 0 },
1044 };
1045
1046 static const struct clksel dsp_ick_clksel[] = {
1047         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1048         { .parent = NULL }
1049 };
1050
1051 static struct clk dsp_ick = {
1052         .name           = "dsp_ick",     /* apparently ipi and isp */
1053         .parent         = &core_ck,
1054         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1055         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1056         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1057         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1058         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1059         .clksel         = dsp_ick_clksel,
1060         .recalc         = &omap2_clksel_recalc,
1061 };
1062
1063 static const struct clksel_rate iva1_ifck_core_rates[] = {
1064         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1065         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1066         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1067         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1068         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1069         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1070         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1071         { .div = 0 },
1072 };
1073
1074 static const struct clksel iva1_ifck_clksel[] = {
1075         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1076         { .parent = NULL }
1077 };
1078
1079 static struct clk iva1_ifck = {
1080         .name           = "iva1_ifck",
1081         .parent         = &core_ck,
1082         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1083                                 RATE_PROPAGATES | DELAYED_APP,
1084         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1085         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1086         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1087         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1088         .clksel         = iva1_ifck_clksel,
1089         .recalc         = &omap2_clksel_recalc,
1090         .round_rate     = &omap2_clksel_round_rate,
1091         .set_rate       = &omap2_clksel_set_rate
1092 };
1093
1094 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1095 static struct clk iva1_mpu_int_ifck = {
1096         .name           = "iva1_mpu_int_ifck",
1097         .parent         = &iva1_ifck,
1098         .flags          = CLOCK_IN_OMAP242X,
1099         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1100         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1101         .fixed_div      = 2,
1102         .recalc         = &omap2_fixed_divisor_recalc,
1103 };
1104
1105 /*
1106  * L3 clock domain
1107  * L3 clocks are used for both interface and functional clocks to
1108  * multiple entities. Some of these clocks are completely managed
1109  * by hardware, and some others allow software control. Hardware
1110  * managed ones general are based on directly CLK_REQ signals and
1111  * various auto idle settings. The functional spec sets many of these
1112  * as 'tie-high' for their enables.
1113  *
1114  * I-CLOCKS:
1115  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1116  *      CAM, HS-USB.
1117  * F-CLOCK
1118  *      SSI.
1119  *
1120  * GPMC memories and SDRC have timing and clock sensitive registers which
1121  * may very well need notification when the clock changes. Currently for low
1122  * operating points, these are taken care of in sleep.S.
1123  */
1124 static const struct clksel_rate core_l3_core_rates[] = {
1125         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1126         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1127         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1128         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1129         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1130         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1131         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1132         { .div = 0 }
1133 };
1134
1135 static const struct clksel core_l3_clksel[] = {
1136         { .parent = &core_ck, .rates = core_l3_core_rates },
1137         { .parent = NULL }
1138 };
1139
1140 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1141         .name           = "core_l3_ck",
1142         .parent         = &core_ck,
1143         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1144                                 ALWAYS_ENABLED | DELAYED_APP |
1145                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1146         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1147         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1148         .clksel         = core_l3_clksel,
1149         .recalc         = &omap2_clksel_recalc,
1150         .round_rate     = &omap2_clksel_round_rate,
1151         .set_rate       = &omap2_clksel_set_rate
1152 };
1153
1154 /* usb_l4_ick */
1155 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1156         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1157         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1158         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1159         { .div = 0 }
1160 };
1161
1162 static const struct clksel usb_l4_ick_clksel[] = {
1163         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1164         { .parent = NULL },
1165 };
1166
1167 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1168         .name           = "usb_l4_ick",
1169         .parent         = &core_l3_ck,
1170         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1171                                 DELAYED_APP | CONFIG_PARTICIPANT,
1172         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1173         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1174         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1175         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1176         .clksel         = usb_l4_ick_clksel,
1177         .recalc         = &omap2_clksel_recalc,
1178         .round_rate     = &omap2_clksel_round_rate,
1179         .set_rate       = &omap2_clksel_set_rate
1180 };
1181
1182 /*
1183  * SSI is in L3 management domain, its direct parent is core not l3,
1184  * many core power domain entities are grouped into the L3 clock
1185  * domain.
1186  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1187  *
1188  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1189  */
1190 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1191         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1192         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1193         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1194         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1195         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1196         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1197         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1198         { .div = 0 }
1199 };
1200
1201 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1202         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1203         { .parent = NULL }
1204 };
1205
1206 static struct clk ssi_ssr_sst_fck = {
1207         .name           = "ssi_fck",
1208         .parent         = &core_ck,
1209         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1210                                 DELAYED_APP,
1211         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1212         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1213         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1214         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1215         .clksel         = ssi_ssr_sst_fck_clksel,
1216         .recalc         = &omap2_clksel_recalc,
1217         .round_rate     = &omap2_clksel_round_rate,
1218         .set_rate       = &omap2_clksel_set_rate
1219 };
1220
1221 /*
1222  * GFX clock domain
1223  *      Clocks:
1224  * GFX_FCLK, GFX_ICLK
1225  * GFX_CG1(2d), GFX_CG2(3d)
1226  *
1227  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1228  * The 2d and 3d clocks run at a hardware determined
1229  * divided value of fclk.
1230  *
1231  */
1232 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1233
1234 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1235 static const struct clksel gfx_fck_clksel[] = {
1236         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1237         { .parent = NULL },
1238 };
1239
1240 static struct clk gfx_3d_fck = {
1241         .name           = "gfx_3d_fck",
1242         .parent         = &core_l3_ck,
1243         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1244         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1245         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1246         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1247         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1248         .clksel         = gfx_fck_clksel,
1249         .recalc         = &omap2_clksel_recalc,
1250         .round_rate     = &omap2_clksel_round_rate,
1251         .set_rate       = &omap2_clksel_set_rate
1252 };
1253
1254 static struct clk gfx_2d_fck = {
1255         .name           = "gfx_2d_fck",
1256         .parent         = &core_l3_ck,
1257         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1258         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1259         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1260         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1261         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1262         .clksel         = gfx_fck_clksel,
1263         .recalc         = &omap2_clksel_recalc,
1264         .round_rate     = &omap2_clksel_round_rate,
1265         .set_rate       = &omap2_clksel_set_rate
1266 };
1267
1268 static struct clk gfx_ick = {
1269         .name           = "gfx_ick",            /* From l3 */
1270         .parent         = &core_l3_ck,
1271         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1272         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1273         .enable_bit     = OMAP_EN_GFX_SHIFT,
1274         .recalc         = &followparent_recalc,
1275 };
1276
1277 /*
1278  * Modem clock domain (2430)
1279  *      CLOCKS:
1280  *              MDM_OSC_CLK
1281  *              MDM_ICLK
1282  * These clocks are usable in chassis mode only.
1283  */
1284 static const struct clksel_rate mdm_ick_core_rates[] = {
1285         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1286         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1287         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1288         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1289         { .div = 0 }
1290 };
1291
1292 static const struct clksel mdm_ick_clksel[] = {
1293         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1294         { .parent = NULL }
1295 };
1296
1297 static struct clk mdm_ick = {           /* used both as a ick and fck */
1298         .name           = "mdm_ick",
1299         .parent         = &core_ck,
1300         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1301         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1302         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1303         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1304         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1305         .clksel         = mdm_ick_clksel,
1306         .recalc         = &omap2_clksel_recalc,
1307         .round_rate     = &omap2_clksel_round_rate,
1308         .set_rate       = &omap2_clksel_set_rate
1309 };
1310
1311 static struct clk mdm_osc_ck = {
1312         .name           = "mdm_osc_ck",
1313         .parent         = &osc_ck,
1314         .flags          = CLOCK_IN_OMAP243X,
1315         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1316         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1317         .recalc         = &followparent_recalc,
1318 };
1319
1320 /*
1321  * L4 clock management domain
1322  *
1323  * This domain contains lots of interface clocks from the L4 interface, some
1324  * functional clocks.   Fixed APLL functional source clocks are managed in
1325  * this domain.
1326  */
1327 static const struct clksel_rate l4_core_l3_rates[] = {
1328         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1329         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1330         { .div = 0 }
1331 };
1332
1333 static const struct clksel l4_clksel[] = {
1334         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1335         { .parent = NULL }
1336 };
1337
1338 static struct clk l4_ck = {             /* used both as an ick and fck */
1339         .name           = "l4_ck",
1340         .parent         = &core_l3_ck,
1341         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1342                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1343         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1344         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1345         .clksel         = l4_clksel,
1346         .recalc         = &omap2_clksel_recalc,
1347         .round_rate     = &omap2_clksel_round_rate,
1348         .set_rate       = &omap2_clksel_set_rate
1349 };
1350
1351 static struct clk ssi_l4_ick = {
1352         .name           = "ssi_l4_ick",
1353         .parent         = &l4_ck,
1354         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1355         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1356         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1357         .recalc         = &followparent_recalc,
1358 };
1359
1360 /*
1361  * DSS clock domain
1362  * CLOCKs:
1363  * DSS_L4_ICLK, DSS_L3_ICLK,
1364  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1365  *
1366  * DSS is both initiator and target.
1367  */
1368 /* XXX Add RATE_NOT_VALIDATED */
1369
1370 static const struct clksel_rate dss1_fck_sys_rates[] = {
1371         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1372         { .div = 0 }
1373 };
1374
1375 static const struct clksel_rate dss1_fck_core_rates[] = {
1376         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1377         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1378         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1379         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1380         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1381         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1382         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1383         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1384         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1385         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1386         { .div = 0 }
1387 };
1388
1389 static const struct clksel dss1_fck_clksel[] = {
1390         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1391         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1392         { .parent = NULL },
1393 };
1394
1395 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1396         .name           = "dss_ick",
1397         .parent         = &l4_ck,       /* really both l3 and l4 */
1398         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1399         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1400         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1401         .recalc         = &followparent_recalc,
1402 };
1403
1404 static struct clk dss1_fck = {
1405         .name           = "dss1_fck",
1406         .parent         = &core_ck,             /* Core or sys */
1407         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1408                                 DELAYED_APP,
1409         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1410         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1411         .init           = &omap2_init_clksel_parent,
1412         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1413         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1414         .clksel         = dss1_fck_clksel,
1415         .recalc         = &omap2_clksel_recalc,
1416         .round_rate     = &omap2_clksel_round_rate,
1417         .set_rate       = &omap2_clksel_set_rate
1418 };
1419
1420 static const struct clksel_rate dss2_fck_sys_rates[] = {
1421         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1422         { .div = 0 }
1423 };
1424
1425 static const struct clksel_rate dss2_fck_48m_rates[] = {
1426         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1427         { .div = 0 }
1428 };
1429
1430 static const struct clksel dss2_fck_clksel[] = {
1431         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1432         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1433         { .parent = NULL }
1434 };
1435
1436 static struct clk dss2_fck = {          /* Alt clk used in power management */
1437         .name           = "dss2_fck",
1438         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1439         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1440                                 DELAYED_APP,
1441         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1442         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1443         .init           = &omap2_init_clksel_parent,
1444         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1445         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1446         .clksel         = dss2_fck_clksel,
1447         .recalc         = &followparent_recalc,
1448 };
1449
1450 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1451         .name           = "dss_54m_fck",        /* 54m tv clk */
1452         .parent         = &func_54m_ck,
1453         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1454         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1455         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 /*
1460  * CORE power domain ICLK & FCLK defines.
1461  * Many of the these can have more than one possible parent. Entries
1462  * here will likely have an L4 interface parent, and may have multiple
1463  * functional clock parents.
1464  */
1465 static const struct clksel_rate gpt_alt_rates[] = {
1466         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1467         { .div = 0 }
1468 };
1469
1470 static const struct clksel omap24xx_gpt_clksel[] = {
1471         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1472         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1473         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1474         { .parent = NULL },
1475 };
1476
1477 static struct clk gpt1_ick = {
1478         .name           = "gpt1_ick",
1479         .parent         = &l4_ck,
1480         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1481         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1482         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1483         .recalc         = &followparent_recalc,
1484 };
1485
1486 static struct clk gpt1_fck = {
1487         .name           = "gpt1_fck",
1488         .parent         = &func_32k_ck,
1489         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1490         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1491         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1492         .init           = &omap2_init_clksel_parent,
1493         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1494         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1495         .clksel         = omap24xx_gpt_clksel,
1496         .recalc         = &omap2_clksel_recalc,
1497         .round_rate     = &omap2_clksel_round_rate,
1498         .set_rate       = &omap2_clksel_set_rate
1499 };
1500
1501 static struct clk gpt2_ick = {
1502         .name           = "gpt2_ick",
1503         .parent         = &l4_ck,
1504         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1505         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1506         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1507         .recalc         = &followparent_recalc,
1508 };
1509
1510 static struct clk gpt2_fck = {
1511         .name           = "gpt2_fck",
1512         .parent         = &func_32k_ck,
1513         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1514         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1515         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1516         .init           = &omap2_init_clksel_parent,
1517         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1518         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1519         .clksel         = omap24xx_gpt_clksel,
1520         .recalc         = &omap2_clksel_recalc,
1521 };
1522
1523 static struct clk gpt3_ick = {
1524         .name           = "gpt3_ick",
1525         .parent         = &l4_ck,
1526         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1527         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1528         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1529         .recalc         = &followparent_recalc,
1530 };
1531
1532 static struct clk gpt3_fck = {
1533         .name           = "gpt3_fck",
1534         .parent         = &func_32k_ck,
1535         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1538         .init           = &omap2_init_clksel_parent,
1539         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1540         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1541         .clksel         = omap24xx_gpt_clksel,
1542         .recalc         = &omap2_clksel_recalc,
1543 };
1544
1545 static struct clk gpt4_ick = {
1546         .name           = "gpt4_ick",
1547         .parent         = &l4_ck,
1548         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1550         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 static struct clk gpt4_fck = {
1555         .name           = "gpt4_fck",
1556         .parent         = &func_32k_ck,
1557         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1558         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1560         .init           = &omap2_init_clksel_parent,
1561         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1562         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1563         .clksel         = omap24xx_gpt_clksel,
1564         .recalc         = &omap2_clksel_recalc,
1565 };
1566
1567 static struct clk gpt5_ick = {
1568         .name           = "gpt5_ick",
1569         .parent         = &l4_ck,
1570         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1572         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk gpt5_fck = {
1577         .name           = "gpt5_fck",
1578         .parent         = &func_32k_ck,
1579         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1581         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1582         .init           = &omap2_init_clksel_parent,
1583         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1584         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1585         .clksel         = omap24xx_gpt_clksel,
1586         .recalc         = &omap2_clksel_recalc,
1587 };
1588
1589 static struct clk gpt6_ick = {
1590         .name           = "gpt6_ick",
1591         .parent         = &l4_ck,
1592         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1593         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1594         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1595         .recalc         = &followparent_recalc,
1596 };
1597
1598 static struct clk gpt6_fck = {
1599         .name           = "gpt6_fck",
1600         .parent         = &func_32k_ck,
1601         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1602         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1603         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1604         .init           = &omap2_init_clksel_parent,
1605         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1606         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1607         .clksel         = omap24xx_gpt_clksel,
1608         .recalc         = &omap2_clksel_recalc,
1609 };
1610
1611 static struct clk gpt7_ick = {
1612         .name           = "gpt7_ick",
1613         .parent         = &l4_ck,
1614         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1615         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1616         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1617         .recalc         = &followparent_recalc,
1618 };
1619
1620 static struct clk gpt7_fck = {
1621         .name           = "gpt7_fck",
1622         .parent         = &func_32k_ck,
1623         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1624         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1625         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1626         .init           = &omap2_init_clksel_parent,
1627         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1628         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1629         .clksel         = omap24xx_gpt_clksel,
1630         .recalc         = &omap2_clksel_recalc,
1631 };
1632
1633 static struct clk gpt8_ick = {
1634         .name           = "gpt8_ick",
1635         .parent         = &l4_ck,
1636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1637         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1638         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1639         .recalc         = &followparent_recalc,
1640 };
1641
1642 static struct clk gpt8_fck = {
1643         .name           = "gpt8_fck",
1644         .parent         = &func_32k_ck,
1645         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1646         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1647         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1648         .init           = &omap2_init_clksel_parent,
1649         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1650         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1651         .clksel         = omap24xx_gpt_clksel,
1652         .recalc         = &omap2_clksel_recalc,
1653 };
1654
1655 static struct clk gpt9_ick = {
1656         .name           = "gpt9_ick",
1657         .parent         = &l4_ck,
1658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1659         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1660         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 static struct clk gpt9_fck = {
1665         .name           = "gpt9_fck",
1666         .parent         = &func_32k_ck,
1667         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1668         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1669         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1670         .init           = &omap2_init_clksel_parent,
1671         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1672         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1673         .clksel         = omap24xx_gpt_clksel,
1674         .recalc         = &omap2_clksel_recalc,
1675 };
1676
1677 static struct clk gpt10_ick = {
1678         .name           = "gpt10_ick",
1679         .parent         = &l4_ck,
1680         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1681         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1682         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1683         .recalc         = &followparent_recalc,
1684 };
1685
1686 static struct clk gpt10_fck = {
1687         .name           = "gpt10_fck",
1688         .parent         = &func_32k_ck,
1689         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1690         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1691         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1692         .init           = &omap2_init_clksel_parent,
1693         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1694         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1695         .clksel         = omap24xx_gpt_clksel,
1696         .recalc         = &omap2_clksel_recalc,
1697 };
1698
1699 static struct clk gpt11_ick = {
1700         .name           = "gpt11_ick",
1701         .parent         = &l4_ck,
1702         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1703         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1704         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1705         .recalc         = &followparent_recalc,
1706 };
1707
1708 static struct clk gpt11_fck = {
1709         .name           = "gpt11_fck",
1710         .parent         = &func_32k_ck,
1711         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1712         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1713         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1714         .init           = &omap2_init_clksel_parent,
1715         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1716         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1717         .clksel         = omap24xx_gpt_clksel,
1718         .recalc         = &omap2_clksel_recalc,
1719 };
1720
1721 static struct clk gpt12_ick = {
1722         .name           = "gpt12_ick",
1723         .parent         = &l4_ck,
1724         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1725         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1726         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1727         .recalc         = &followparent_recalc,
1728 };
1729
1730 static struct clk gpt12_fck = {
1731         .name           = "gpt12_fck",
1732         .parent         = &func_32k_ck,
1733         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1735         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1736         .init           = &omap2_init_clksel_parent,
1737         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1738         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1739         .clksel         = omap24xx_gpt_clksel,
1740         .recalc         = &omap2_clksel_recalc,
1741 };
1742
1743 static struct clk mcbsp1_ick = {
1744         .name           = "mcbsp1_ick",
1745         .parent         = &l4_ck,
1746         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1747         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1749         .recalc         = &followparent_recalc,
1750 };
1751
1752 static struct clk mcbsp1_fck = {
1753         .name           = "mcbsp1_fck",
1754         .parent         = &func_96m_ck,
1755         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1757         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1758         .recalc         = &followparent_recalc,
1759 };
1760
1761 static struct clk mcbsp2_ick = {
1762         .name           = "mcbsp2_ick",
1763         .parent         = &l4_ck,
1764         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1765         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1767         .recalc         = &followparent_recalc,
1768 };
1769
1770 static struct clk mcbsp2_fck = {
1771         .name           = "mcbsp2_fck",
1772         .parent         = &func_96m_ck,
1773         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1775         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1776         .recalc         = &followparent_recalc,
1777 };
1778
1779 static struct clk mcbsp3_ick = {
1780         .name           = "mcbsp3_ick",
1781         .parent         = &l4_ck,
1782         .flags          = CLOCK_IN_OMAP243X,
1783         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1784         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1785         .recalc         = &followparent_recalc,
1786 };
1787
1788 static struct clk mcbsp3_fck = {
1789         .name           = "mcbsp3_fck",
1790         .parent         = &func_96m_ck,
1791         .flags          = CLOCK_IN_OMAP243X,
1792         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1793         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1794         .recalc         = &followparent_recalc,
1795 };
1796
1797 static struct clk mcbsp4_ick = {
1798         .name           = "mcbsp4_ick",
1799         .parent         = &l4_ck,
1800         .flags          = CLOCK_IN_OMAP243X,
1801         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1802         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mcbsp4_fck = {
1807         .name           = "mcbsp4_fck",
1808         .parent         = &func_96m_ck,
1809         .flags          = CLOCK_IN_OMAP243X,
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1811         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mcbsp5_ick = {
1816         .name           = "mcbsp5_ick",
1817         .parent         = &l4_ck,
1818         .flags          = CLOCK_IN_OMAP243X,
1819         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1820         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk mcbsp5_fck = {
1825         .name           = "mcbsp5_fck",
1826         .parent         = &func_96m_ck,
1827         .flags          = CLOCK_IN_OMAP243X,
1828         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1829         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1830         .recalc         = &followparent_recalc,
1831 };
1832
1833 static struct clk mcspi1_ick = {
1834         .name           = "mcspi_ick",
1835         .id             = 1,
1836         .parent         = &l4_ck,
1837         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1838         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1839         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1840         .recalc         = &followparent_recalc,
1841 };
1842
1843 static struct clk mcspi1_fck = {
1844         .name           = "mcspi_fck",
1845         .id             = 1,
1846         .parent         = &func_48m_ck,
1847         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1848         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1849         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1850         .recalc         = &followparent_recalc,
1851 };
1852
1853 static struct clk mcspi2_ick = {
1854         .name           = "mcspi_ick",
1855         .id             = 2,
1856         .parent         = &l4_ck,
1857         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1858         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1859         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1860         .recalc         = &followparent_recalc,
1861 };
1862
1863 static struct clk mcspi2_fck = {
1864         .name           = "mcspi_fck",
1865         .id             = 2,
1866         .parent         = &func_48m_ck,
1867         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1868         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1869         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1870         .recalc         = &followparent_recalc,
1871 };
1872
1873 static struct clk mcspi3_ick = {
1874         .name           = "mcspi_ick",
1875         .id             = 3,
1876         .parent         = &l4_ck,
1877         .flags          = CLOCK_IN_OMAP243X,
1878         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1879         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1880         .recalc         = &followparent_recalc,
1881 };
1882
1883 static struct clk mcspi3_fck = {
1884         .name           = "mcspi_fck",
1885         .id             = 3,
1886         .parent         = &func_48m_ck,
1887         .flags          = CLOCK_IN_OMAP243X,
1888         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1889         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1890         .recalc         = &followparent_recalc,
1891 };
1892
1893 static struct clk uart1_ick = {
1894         .name           = "uart1_ick",
1895         .parent         = &l4_ck,
1896         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1898         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk uart1_fck = {
1903         .name           = "uart1_fck",
1904         .parent         = &func_48m_ck,
1905         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1907         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1908         .recalc         = &followparent_recalc,
1909 };
1910
1911 static struct clk uart2_ick = {
1912         .name           = "uart2_ick",
1913         .parent         = &l4_ck,
1914         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk uart2_fck = {
1921         .name           = "uart2_fck",
1922         .parent         = &func_48m_ck,
1923         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1924         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1925         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 static struct clk uart3_ick = {
1930         .name           = "uart3_ick",
1931         .parent         = &l4_ck,
1932         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1933         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1934         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk uart3_fck = {
1939         .name           = "uart3_fck",
1940         .parent         = &func_48m_ck,
1941         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1942         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1943         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1944         .recalc         = &followparent_recalc,
1945 };
1946
1947 static struct clk gpios_ick = {
1948         .name           = "gpios_ick",
1949         .parent         = &l4_ck,
1950         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1951         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1952         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk gpios_fck = {
1957         .name           = "gpios_fck",
1958         .parent         = &func_32k_ck,
1959         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1960         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1961         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk mpu_wdt_ick = {
1966         .name           = "mpu_wdt_ick",
1967         .parent         = &l4_ck,
1968         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1969         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1970         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1971         .recalc         = &followparent_recalc,
1972 };
1973
1974 static struct clk mpu_wdt_fck = {
1975         .name           = "mpu_wdt_fck",
1976         .parent         = &func_32k_ck,
1977         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1978         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1979         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1980         .recalc         = &followparent_recalc,
1981 };
1982
1983 static struct clk sync_32k_ick = {
1984         .name           = "sync_32k_ick",
1985         .parent         = &l4_ck,
1986         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1987         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1988         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1989         .recalc         = &followparent_recalc,
1990 };
1991 static struct clk wdt1_ick = {
1992         .name           = "wdt1_ick",
1993         .parent         = &l4_ck,
1994         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1995         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1996         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1997         .recalc         = &followparent_recalc,
1998 };
1999 static struct clk omapctrl_ick = {
2000         .name           = "omapctrl_ick",
2001         .parent         = &l4_ck,
2002         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2003         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2004         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2005         .recalc         = &followparent_recalc,
2006 };
2007 static struct clk icr_ick = {
2008         .name           = "icr_ick",
2009         .parent         = &l4_ck,
2010         .flags          = CLOCK_IN_OMAP243X,
2011         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2012         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2013         .recalc         = &followparent_recalc,
2014 };
2015
2016 static struct clk cam_ick = {
2017         .name           = "cam_ick",
2018         .parent         = &l4_ck,
2019         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2020         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2021         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2022         .recalc         = &followparent_recalc,
2023 };
2024
2025 static struct clk cam_fck = {
2026         .name           = "cam_fck",
2027         .parent         = &func_96m_ck,
2028         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2029         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2030         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2031         .recalc         = &followparent_recalc,
2032 };
2033
2034 static struct clk mailboxes_ick = {
2035         .name           = "mailboxes_ick",
2036         .parent         = &l4_ck,
2037         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2039         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2040         .recalc         = &followparent_recalc,
2041 };
2042
2043 static struct clk wdt4_ick = {
2044         .name           = "wdt4_ick",
2045         .parent         = &l4_ck,
2046         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2047         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2048         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2049         .recalc         = &followparent_recalc,
2050 };
2051
2052 static struct clk wdt4_fck = {
2053         .name           = "wdt4_fck",
2054         .parent         = &func_32k_ck,
2055         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2056         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2057         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2058         .recalc         = &followparent_recalc,
2059 };
2060
2061 static struct clk wdt3_ick = {
2062         .name           = "wdt3_ick",
2063         .parent         = &l4_ck,
2064         .flags          = CLOCK_IN_OMAP242X,
2065         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2066         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2067         .recalc         = &followparent_recalc,
2068 };
2069
2070 static struct clk wdt3_fck = {
2071         .name           = "wdt3_fck",
2072         .parent         = &func_32k_ck,
2073         .flags          = CLOCK_IN_OMAP242X,
2074         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2075         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2076         .recalc         = &followparent_recalc,
2077 };
2078
2079 static struct clk mspro_ick = {
2080         .name           = "mspro_ick",
2081         .parent         = &l4_ck,
2082         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2083         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2084         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2085         .recalc         = &followparent_recalc,
2086 };
2087
2088 static struct clk mspro_fck = {
2089         .name           = "mspro_fck",
2090         .parent         = &func_96m_ck,
2091         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2092         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2093         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2094         .recalc         = &followparent_recalc,
2095 };
2096
2097 static struct clk mmc_ick = {
2098         .name           = "mmc_ick",
2099         .parent         = &l4_ck,
2100         .flags          = CLOCK_IN_OMAP242X,
2101         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2102         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk mmc_fck = {
2107         .name           = "mmc_fck",
2108         .parent         = &func_96m_ck,
2109         .flags          = CLOCK_IN_OMAP242X,
2110         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2111         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2112         .recalc         = &followparent_recalc,
2113 };
2114
2115 static struct clk fac_ick = {
2116         .name           = "fac_ick",
2117         .parent         = &l4_ck,
2118         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2119         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2120         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 static struct clk fac_fck = {
2125         .name           = "fac_fck",
2126         .parent         = &func_12m_ck,
2127         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2128         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2129         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2130         .recalc         = &followparent_recalc,
2131 };
2132
2133 static struct clk eac_ick = {
2134         .name           = "eac_ick",
2135         .parent         = &l4_ck,
2136         .flags          = CLOCK_IN_OMAP242X,
2137         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2138         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2139         .recalc         = &followparent_recalc,
2140 };
2141
2142 static struct clk eac_fck = {
2143         .name           = "eac_fck",
2144         .parent         = &func_96m_ck,
2145         .flags          = CLOCK_IN_OMAP242X,
2146         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2147         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2148         .recalc         = &followparent_recalc,
2149 };
2150
2151 static struct clk hdq_ick = {
2152         .name           = "hdq_ick",
2153         .parent         = &l4_ck,
2154         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2156         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2157         .recalc         = &followparent_recalc,
2158 };
2159
2160 static struct clk hdq_fck = {
2161         .name           = "hdq_fck",
2162         .parent         = &func_12m_ck,
2163         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2164         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2165         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2166         .recalc         = &followparent_recalc,
2167 };
2168
2169 static struct clk i2c2_ick = {
2170         .name           = "i2c_ick",
2171         .id             = 2,
2172         .parent         = &l4_ck,
2173         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2174         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2175         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2176         .recalc         = &followparent_recalc,
2177 };
2178
2179 static struct clk i2c2_fck = {
2180         .name           = "i2c_fck",
2181         .id             = 2,
2182         .parent         = &func_12m_ck,
2183         .flags          = CLOCK_IN_OMAP242X,
2184         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2185         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2186         .recalc         = &followparent_recalc,
2187 };
2188
2189 static struct clk i2chs2_fck = {
2190         .name           = "i2chs_fck",
2191         .id             = 2,
2192         .parent         = &func_96m_ck,
2193         .flags          = CLOCK_IN_OMAP243X,
2194         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2195         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2196         .recalc         = &followparent_recalc,
2197 };
2198
2199 static struct clk i2c1_ick = {
2200         .name           = "i2c_ick",
2201         .id             = 1,
2202         .parent         = &l4_ck,
2203         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2204         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2205         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2206         .recalc         = &followparent_recalc,
2207 };
2208
2209 static struct clk i2c1_fck = {
2210         .name           = "i2c_fck",
2211         .id             = 1,
2212         .parent         = &func_12m_ck,
2213         .flags          = CLOCK_IN_OMAP242X,
2214         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2215         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2216         .recalc         = &followparent_recalc,
2217 };
2218
2219 static struct clk i2chs1_fck = {
2220         .name           = "i2chs_fck",
2221         .id             = 1,
2222         .parent         = &func_96m_ck,
2223         .flags          = CLOCK_IN_OMAP243X,
2224         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2225         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2226         .recalc         = &followparent_recalc,
2227 };
2228
2229 static struct clk gpmc_fck = {
2230         .name           = "gpmc_fck",
2231         .parent         = &core_l3_ck,
2232         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2233         .recalc         = &followparent_recalc,
2234 };
2235
2236 static struct clk sdma_fck = {
2237         .name           = "sdma_fck",
2238         .parent         = &core_l3_ck,
2239         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk sdma_ick = {
2244         .name           = "sdma_ick",
2245         .parent         = &l4_ck,
2246         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2247         .recalc         = &followparent_recalc,
2248 };
2249
2250 static struct clk vlynq_ick = {
2251         .name           = "vlynq_ick",
2252         .parent         = &core_l3_ck,
2253         .flags          = CLOCK_IN_OMAP242X,
2254         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2255         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2256         .recalc         = &followparent_recalc,
2257 };
2258
2259 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2260         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2261         { .div = 0 }
2262 };
2263
2264 static const struct clksel_rate vlynq_fck_core_rates[] = {
2265         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2266         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2267         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2268         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2269         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2270         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2271         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2272         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2273         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2274         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2275         { .div = 0 }
2276 };
2277
2278 static const struct clksel vlynq_fck_clksel[] = {
2279         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2280         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2281         { .parent = NULL }
2282 };
2283
2284 static struct clk vlynq_fck = {
2285         .name           = "vlynq_fck",
2286         .parent         = &func_96m_ck,
2287         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2288         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2289         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2290         .init           = &omap2_init_clksel_parent,
2291         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2292         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2293         .clksel         = vlynq_fck_clksel,
2294         .recalc         = &omap2_clksel_recalc,
2295         .round_rate     = &omap2_clksel_round_rate,
2296         .set_rate       = &omap2_clksel_set_rate
2297 };
2298
2299 static struct clk sdrc_ick = {
2300         .name           = "sdrc_ick",
2301         .parent         = &l4_ck,
2302         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2303         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2304         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2305         .recalc         = &followparent_recalc,
2306 };
2307
2308 static struct clk des_ick = {
2309         .name           = "des_ick",
2310         .parent         = &l4_ck,
2311         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2312         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2313         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2314         .recalc         = &followparent_recalc,
2315 };
2316
2317 static struct clk sha_ick = {
2318         .name           = "sha_ick",
2319         .parent         = &l4_ck,
2320         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2321         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2322         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2323         .recalc         = &followparent_recalc,
2324 };
2325
2326 static struct clk rng_ick = {
2327         .name           = "rng_ick",
2328         .parent         = &l4_ck,
2329         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2330         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2331         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2332         .recalc         = &followparent_recalc,
2333 };
2334
2335 static struct clk aes_ick = {
2336         .name           = "aes_ick",
2337         .parent         = &l4_ck,
2338         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2339         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2340         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2341         .recalc         = &followparent_recalc,
2342 };
2343
2344 static struct clk pka_ick = {
2345         .name           = "pka_ick",
2346         .parent         = &l4_ck,
2347         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2348         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2349         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2350         .recalc         = &followparent_recalc,
2351 };
2352
2353 static struct clk usb_fck = {
2354         .name           = "usb_fck",
2355         .parent         = &func_48m_ck,
2356         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2357         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2358         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk usbhs_ick = {
2363         .name           = "usbhs_ick",
2364         .parent         = &core_l3_ck,
2365         .flags          = CLOCK_IN_OMAP243X,
2366         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2367         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2368         .recalc         = &followparent_recalc,
2369 };
2370
2371 static struct clk mmchs1_ick = {
2372         .name           = "mmchs1_ick",
2373         .parent         = &l4_ck,
2374         .flags          = CLOCK_IN_OMAP243X,
2375         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2376         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2377         .recalc         = &followparent_recalc,
2378 };
2379
2380 static struct clk mmchs1_fck = {
2381         .name           = "mmchs1_fck",
2382         .parent         = &func_96m_ck,
2383         .flags          = CLOCK_IN_OMAP243X,
2384         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2385         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2386         .recalc         = &followparent_recalc,
2387 };
2388
2389 static struct clk mmchs2_ick = {
2390         .name           = "mmchs2_ick",
2391         .parent         = &l4_ck,
2392         .flags          = CLOCK_IN_OMAP243X,
2393         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2394         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static struct clk mmchs2_fck = {
2399         .name           = "mmchs2_fck",
2400         .parent         = &func_96m_ck,
2401         .flags          = CLOCK_IN_OMAP243X,
2402         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2403         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2404         .recalc         = &followparent_recalc,
2405 };
2406
2407 static struct clk gpio5_ick = {
2408         .name           = "gpio5_ick",
2409         .parent         = &l4_ck,
2410         .flags          = CLOCK_IN_OMAP243X,
2411         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2412         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2413         .recalc         = &followparent_recalc,
2414 };
2415
2416 static struct clk gpio5_fck = {
2417         .name           = "gpio5_fck",
2418         .parent         = &func_32k_ck,
2419         .flags          = CLOCK_IN_OMAP243X,
2420         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2421         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2422         .recalc         = &followparent_recalc,
2423 };
2424
2425 static struct clk mdm_intc_ick = {
2426         .name           = "mdm_intc_ick",
2427         .parent         = &l4_ck,
2428         .flags          = CLOCK_IN_OMAP243X,
2429         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2430         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2431         .recalc         = &followparent_recalc,
2432 };
2433
2434 static struct clk mmchsdb1_fck = {
2435         .name           = "mmchsdb1_fck",
2436         .parent         = &func_32k_ck,
2437         .flags          = CLOCK_IN_OMAP243X,
2438         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2439         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2440         .recalc         = &followparent_recalc,
2441 };
2442
2443 static struct clk mmchsdb2_fck = {
2444         .name           = "mmchsdb2_fck",
2445         .parent         = &func_32k_ck,
2446         .flags          = CLOCK_IN_OMAP243X,
2447         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2448         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2449         .recalc         = &followparent_recalc,
2450 };
2451
2452 /*
2453  * This clock is a composite clock which does entire set changes then
2454  * forces a rebalance. It keys on the MPU speed, but it really could
2455  * be any key speed part of a set in the rate table.
2456  *
2457  * to really change a set, you need memory table sets which get changed
2458  * in sram, pre-notifiers & post notifiers, changing the top set, without
2459  * having low level display recalc's won't work... this is why dpm notifiers
2460  * work, isr's off, walk a list of clocks already _off_ and not messing with
2461  * the bus.
2462  *
2463  * This clock should have no parent. It embodies the entire upper level
2464  * active set. A parent will mess up some of the init also.
2465  */
2466 static struct clk virt_prcm_set = {
2467         .name           = "virt_prcm_set",
2468         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2469                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2470         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2471         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2472         .set_rate       = &omap2_select_table_rate,
2473         .round_rate     = &omap2_round_to_table_rate,
2474 };
2475
2476 static struct clk *onchip_24xx_clks[] __initdata = {
2477         /* external root sources */
2478         &func_32k_ck,
2479         &osc_ck,
2480         &sys_ck,
2481         &alt_ck,
2482         /* internal analog sources */
2483         &dpll_ck,
2484         &apll96_ck,
2485         &apll54_ck,
2486         /* internal prcm root sources */
2487         &func_54m_ck,
2488         &core_ck,
2489         &func_96m_ck,
2490         &func_48m_ck,
2491         &func_12m_ck,
2492         &wdt1_osc_ck,
2493         &sys_clkout_src,
2494         &sys_clkout,
2495         &sys_clkout2_src,
2496         &sys_clkout2,
2497         &emul_ck,
2498         /* mpu domain clocks */
2499         &mpu_ck,
2500         /* dsp domain clocks */
2501         &iva2_1_fck,            /* 2430 */
2502         &iva2_1_ick,
2503         &dsp_ick,               /* 2420 */
2504         &dsp_fck,
2505         &iva1_ifck,
2506         &iva1_mpu_int_ifck,
2507         /* GFX domain clocks */
2508         &gfx_3d_fck,
2509         &gfx_2d_fck,
2510         &gfx_ick,
2511         /* Modem domain clocks */
2512         &mdm_ick,
2513         &mdm_osc_ck,
2514         /* DSS domain clocks */
2515         &dss_ick,
2516         &dss1_fck,
2517         &dss2_fck,
2518         &dss_54m_fck,
2519         /* L3 domain clocks */
2520         &core_l3_ck,
2521         &ssi_ssr_sst_fck,
2522         &usb_l4_ick,
2523         /* L4 domain clocks */
2524         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2525         &ssi_l4_ick,
2526         /* virtual meta-group clock */
2527         &virt_prcm_set,
2528         /* general l4 interface ck, multi-parent functional clk */
2529         &gpt1_ick,
2530         &gpt1_fck,
2531         &gpt2_ick,
2532         &gpt2_fck,
2533         &gpt3_ick,
2534         &gpt3_fck,
2535         &gpt4_ick,
2536         &gpt4_fck,
2537         &gpt5_ick,
2538         &gpt5_fck,
2539         &gpt6_ick,
2540         &gpt6_fck,
2541         &gpt7_ick,
2542         &gpt7_fck,
2543         &gpt8_ick,
2544         &gpt8_fck,
2545         &gpt9_ick,
2546         &gpt9_fck,
2547         &gpt10_ick,
2548         &gpt10_fck,
2549         &gpt11_ick,
2550         &gpt11_fck,
2551         &gpt12_ick,
2552         &gpt12_fck,
2553         &mcbsp1_ick,
2554         &mcbsp1_fck,
2555         &mcbsp2_ick,
2556         &mcbsp2_fck,
2557         &mcbsp3_ick,
2558         &mcbsp3_fck,
2559         &mcbsp4_ick,
2560         &mcbsp4_fck,
2561         &mcbsp5_ick,
2562         &mcbsp5_fck,
2563         &mcspi1_ick,
2564         &mcspi1_fck,
2565         &mcspi2_ick,
2566         &mcspi2_fck,
2567         &mcspi3_ick,
2568         &mcspi3_fck,
2569         &uart1_ick,
2570         &uart1_fck,
2571         &uart2_ick,
2572         &uart2_fck,
2573         &uart3_ick,
2574         &uart3_fck,
2575         &gpios_ick,
2576         &gpios_fck,
2577         &mpu_wdt_ick,
2578         &mpu_wdt_fck,
2579         &sync_32k_ick,
2580         &wdt1_ick,
2581         &omapctrl_ick,
2582         &icr_ick,
2583         &cam_fck,
2584         &cam_ick,
2585         &mailboxes_ick,
2586         &wdt4_ick,
2587         &wdt4_fck,
2588         &wdt3_ick,
2589         &wdt3_fck,
2590         &mspro_ick,
2591         &mspro_fck,
2592         &mmc_ick,
2593         &mmc_fck,
2594         &fac_ick,
2595         &fac_fck,
2596         &eac_ick,
2597         &eac_fck,
2598         &hdq_ick,
2599         &hdq_fck,
2600         &i2c1_ick,
2601         &i2c1_fck,
2602         &i2chs1_fck,
2603         &i2c2_ick,
2604         &i2c2_fck,
2605         &i2chs2_fck,
2606         &gpmc_fck,
2607         &sdma_fck,
2608         &sdma_ick,
2609         &vlynq_ick,
2610         &vlynq_fck,
2611         &sdrc_ick,
2612         &des_ick,
2613         &sha_ick,
2614         &rng_ick,
2615         &aes_ick,
2616         &pka_ick,
2617         &usb_fck,
2618         &usbhs_ick,
2619         &mmchs1_ick,
2620         &mmchs1_fck,
2621         &mmchs2_ick,
2622         &mmchs2_fck,
2623         &gpio5_ick,
2624         &gpio5_fck,
2625         &mdm_intc_ick,
2626         &mmchsdb1_fck,
2627         &mmchsdb2_fck,
2628 };
2629
2630 #endif
2631