arch/arm/mach-omap2/clock24xx.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
  12  *  Gordon McNutt and RidgeRun, Inc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #undef DEBUG
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/list.h>
  24 #include <linux/errno.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/bitops.h>
  28 #include <linux/io.h>
  29 #include <linux/cpufreq.h>
  30
  31 #include <mach/common.h>
  32 #include <mach/clock.h>
  33 #include <mach/sram.h>
  34 #include <asm/div64.h>
  35
  36 #include <mach/sdrc.h>
  37 #include "clock.h"
  38 #include "clock24xx.h"
  39 #include "prm.h"
  40 #include "prm-regbits-24xx.h"
  41 #include "cm.h"
  42 #include "cm-regbits-24xx.h"
  43
  44 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
  45 #define EN_APLL_STOPPED                 0
  46 #define EN_APLL_LOCKED                  3
  47
  48 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
  49 #define APLLS_CLKIN_19_2MHZ             0
  50 #define APLLS_CLKIN_13MHZ               2
  51 #define APLLS_CLKIN_12MHZ               3
  52
  53 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
  54
  55 static struct prcm_config *curr_prcm_set;
  56 static struct clk *vclk;
  57 static struct clk *sclk;
  58
  59 /*-------------------------------------------------------------------------
  60  * Omap24xx specific clock functions
  61  *-------------------------------------------------------------------------*/
  62
  63 /* This actually returns the rate of core_ck, not dpll_ck. */
  64 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
  65 {
  66         long long dpll_clk;
  67         u8 amult;
  68
  69         dpll_clk = omap2_get_dpll_rate(tclk);
  70
  71         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  72         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  73         dpll_clk *= amult;
  74
  75         return dpll_clk;
  76 }
  77
  78 static int omap2_enable_osc_ck(struct clk *clk)
  79 {
  80         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 0,
  81                         OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
  82
  83         return 0;
  84 }
  85
  86 static void omap2_disable_osc_ck(struct clk *clk)
  87 {
  88         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP_AUTOEXTCLKMODE_MASK,
  89                         OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
  90 }
  91
  92 /* Enable an APLL if off */
  93 static int omap2_clk_fixed_enable(struct clk *clk)
  94 {
  95         u32 cval, apll_mask;
  96
  97         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
  98
  99         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 100
 101         if ((cval & apll_mask) == apll_mask)
 102                 return 0;   /* apll already enabled */
 103
 104         cval &= ~apll_mask;
 105         cval |= apll_mask;
 106         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 107
 108         if (clk == &apll96_ck)
 109                 cval = OMAP24XX_ST_96M_APLL;
 110         else if (clk == &apll54_ck)
 111                 cval = OMAP24XX_ST_54M_APLL;
 112
 113         omap2_wait_clock_ready(PLL_MOD, CM_IDLEST, cval, clk->name);
 114
 115         /*
 116          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
 117          * fails?
 118          */
 119         return 0;
 120 }
 121
 122 /* Stop APLL */
 123 static void omap2_clk_fixed_disable(struct clk *clk)
 124 {
 125         u32 cval;
 126
 127         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 128         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 129         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 130 }
 131
 132 /*
 133  * Uses the current prcm set to tell if a rate is valid.
 134  * You can go slower, but not faster within a given rate set.
 135  */
 136 static long omap2_dpllcore_round_rate(unsigned long target_rate)
 137 {
 138         u32 high, low, core_clk_src;
 139
 140         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 141         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 142
 143         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
 144                 high = curr_prcm_set->dpll_speed * 2;
 145                 low = curr_prcm_set->dpll_speed;
 146         } else {                                /* DPLL clockout x 2 */
 147                 high = curr_prcm_set->dpll_speed;
 148                 low = curr_prcm_set->dpll_speed / 2;
 149         }
 150
 151 #ifdef DOWN_VARIABLE_DPLL
 152         if (target_rate > high)
 153                 return high;
 154         else
 155                 return target_rate;
 156 #else
 157         if (target_rate > low)
 158                 return high;
 159         else
 160                 return low;
 161 #endif
 162
 163 }
 164
 165 static void omap2_dpllcore_recalc(struct clk *clk)
 166 {
 167         clk->rate = omap2_get_dpll_rate_24xx(clk);
 168
 169         propagate_rate(clk);
 170 }
 171
 172 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 173 {
 174         u32 cur_rate, low, mult, div, valid_rate, done_rate;
 175         u32 bypass = 0;
 176         struct prcm_config tmpset;
 177         const struct dpll_data *dd;
 178         unsigned long flags;
 179         int ret = -EINVAL;
 180
 181         local_irq_save(flags);
 182         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 183         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 184         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 185
 186         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 187                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
 188         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 189                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 190         } else if (rate != cur_rate) {
 191                 valid_rate = omap2_dpllcore_round_rate(rate);
 192                 if (valid_rate != rate)
 193                         goto dpll_exit;
 194
 195                 if (mult == 1)
 196                         low = curr_prcm_set->dpll_speed;
 197                 else
 198                         low = curr_prcm_set->dpll_speed / 2;
 199
 200                 dd = clk->dpll_data;
 201                 if (!dd)
 202                         goto dpll_exit;
 203
 204                 tmpset.cm_clksel1_pll = cm_read_mod_reg(clk->prcm_mod,
 205                                                         dd->mult_div1_reg);
 206                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
 207                                            dd->div1_mask);
 208                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 209                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 210                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 211                 if (rate > low) {
 212                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
 213                         mult = ((rate / 2) / 1000000);
 214                         done_rate = CORE_CLK_SRC_DPLL_X2;
 215                 } else {
 216                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
 217                         mult = (rate / 1000000);
 218                         done_rate = CORE_CLK_SRC_DPLL;
 219                 }
 220                 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
 221                 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
 222
 223                 /* Worst case */
 224                 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
 225
 226                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 227                         bypass = 1;
 228
 229                 /* For omap2xxx_sdrc_init_params() */
 230                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 231
 232                 /* Force dll lock mode */
 233                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 234                                bypass);
 235
 236                 /* Errata: ret dll entry state */
 237                 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
 238                 omap2xxx_sdrc_reprogram(done_rate, 0);
 239         }
 240         omap2_dpllcore_recalc(&dpll_ck);
 241         ret = 0;
 242
 243 dpll_exit:
 244         local_irq_restore(flags);
 245         return(ret);
 246 }
 247
 248 /**
 249  * omap2_table_mpu_recalc - just return the MPU speed
 250  * @clk: virt_prcm_set struct clk
 251  *
 252  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 253  */
 254 static void omap2_table_mpu_recalc(struct clk *clk)
 255 {
 256         clk->rate = curr_prcm_set->mpu_speed;
 257 }
 258
 259 /*
 260  * Look for a rate equal or less than the target rate given a configuration set.
 261  *
 262  * What's not entirely clear is "which" field represents the key field.
 263  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 264  * just uses the ARM rates.
 265  */
 266 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 267 {
 268         struct prcm_config *ptr;
 269         long highest_rate;
 270
 271         if (clk != &virt_prcm_set)
 272                 return -EINVAL;
 273
 274         highest_rate = -EINVAL;
 275
 276         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 277                 if (!(ptr->flags & cpu_mask))
 278                         continue;
 279                 if (ptr->xtal_speed != sys_ck.rate)
 280                         continue;
 281
 282                 highest_rate = ptr->mpu_speed;
 283
 284                 /* Can check only after xtal frequency check */
 285                 if (ptr->mpu_speed <= rate)
 286                         break;
 287         }
 288         return highest_rate;
 289 }
 290
 291 /* Sets basic clocks based on the specified rate */
 292 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 293 {
 294         u32 cur_rate, done_rate, bypass = 0, tmp;
 295         struct prcm_config *prcm;
 296         unsigned long found_speed = 0;
 297         unsigned long flags;
 298
 299         if (clk != &virt_prcm_set)
 300                 return -EINVAL;
 301
 302         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 303                 if (!(prcm->flags & cpu_mask))
 304                         continue;
 305
 306                 if (prcm->xtal_speed != sys_ck.rate)
 307                         continue;
 308
 309                 if (prcm->mpu_speed <= rate) {
 310                         found_speed = prcm->mpu_speed;
 311                         break;
 312                 }
 313         }
 314
 315         if (!found_speed) {
 316                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 317                        rate / 1000000);
 318                 return -EINVAL;
 319         }
 320
 321         curr_prcm_set = prcm;
 322         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 323
 324         if (prcm->dpll_speed == cur_rate / 2) {
 325                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
 326         } else if (prcm->dpll_speed == cur_rate * 2) {
 327                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 328         } else if (prcm->dpll_speed != cur_rate) {
 329                 local_irq_save(flags);
 330
 331                 if (prcm->dpll_speed == prcm->xtal_speed)
 332                         bypass = 1;
 333
 334                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
 335                     CORE_CLK_SRC_DPLL_X2)
 336                         done_rate = CORE_CLK_SRC_DPLL_X2;
 337                 else
 338                         done_rate = CORE_CLK_SRC_DPLL;
 339
 340                 /* MPU divider */
 341                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 342
 343                 /* dsp + iva1 div(2420), iva2.1(2430) */
 344                 cm_write_mod_reg(prcm->cm_clksel_dsp,
 345                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 346
 347                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 348
 349                 /* Major subsystem dividers */
 350                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
 351                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
 352                                  CM_CLKSEL1);
 353
 354                 if (cpu_is_omap2430())
 355                         cm_write_mod_reg(prcm->cm_clksel_mdm,
 356                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 357
 358                 /* x2 to enter omap2xxx_sdrc_init_params() */
 359                 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 360
 361                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 362                                bypass);
 363
 364                 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
 365                 omap2xxx_sdrc_reprogram(done_rate, 0);
 366
 367                 local_irq_restore(flags);
 368         }
 369         omap2_dpllcore_recalc(&dpll_ck);
 370
 371         return 0;
 372 }
 373
 374 #ifdef CONFIG_CPU_FREQ
 375 /*
 376  * Walk PRCM rate table and fillout cpufreq freq_table
 377  */
 378 static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
 379
 380 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 381 {
 382         struct prcm_config *prcm;
 383         int i = 0;
 384
 385         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 386                 if (!(prcm->flags & cpu_mask))
 387                         continue;
 388                 if (prcm->xtal_speed != sys_ck.rate)
 389                         continue;
 390
 391                 /* don't put bypass rates in table */
 392                 if (prcm->dpll_speed == prcm->xtal_speed)
 393                         continue;
 394
 395                 freq_table[i].index = i;
 396                 freq_table[i].frequency = prcm->mpu_speed / 1000;
 397                 i++;
 398         }
 399
 400         if (i == 0) {
 401                 printk(KERN_WARNING "%s: failed to initialize frequency "
 402                        "table\n", __func__);
 403                 return;
 404         }
 405
 406         freq_table[i].index = i;
 407         freq_table[i].frequency = CPUFREQ_TABLE_END;
 408
 409         *table = &freq_table[0];
 410 }
 411 #endif
 412
 413 static struct clk_functions omap2_clk_functions = {
 414         .clk_enable             = omap2_clk_enable,
 415         .clk_disable            = omap2_clk_disable,
 416         .clk_round_rate         = omap2_clk_round_rate,
 417         .clk_set_rate           = omap2_clk_set_rate,
 418         .clk_set_parent         = omap2_clk_set_parent,
 419         .clk_disable_unused     = omap2_clk_disable_unused,
 420 #ifdef  CONFIG_CPU_FREQ
 421         .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
 422 #endif
 423 };
 424
 425 static u32 omap2_get_apll_clkin(void)
 426 {
 427         u32 aplls, srate = 0;
 428
 429         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 430         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 431         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 432
 433         if (aplls == APLLS_CLKIN_19_2MHZ)
 434                 srate = 19200000;
 435         else if (aplls == APLLS_CLKIN_13MHZ)
 436                 srate = 13000000;
 437         else if (aplls == APLLS_CLKIN_12MHZ)
 438                 srate = 12000000;
 439
 440         return srate;
 441 }
 442
 443 static u32 omap2_get_sysclkdiv(void)
 444 {
 445         u32 div;
 446
 447         div = prm_read_mod_reg(OMAP24XX_GR_MOD,
 448                                 OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET);
 449         div &= OMAP_SYSCLKDIV_MASK;
 450         div >>= OMAP_SYSCLKDIV_SHIFT;
 451
 452         return div;
 453 }
 454
 455 static void omap2_osc_clk_recalc(struct clk *clk)
 456 {
 457         clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
 458         propagate_rate(clk);
 459 }
 460
 461 static void omap2_sys_clk_recalc(struct clk *clk)
 462 {
 463         clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
 464         propagate_rate(clk);
 465 }
 466
 467 /*
 468  * Set clocks for bypass mode for reboot to work.
 469  */
 470 void omap2_clk_prepare_for_reboot(void)
 471 {
 472         u32 rate;
 473
 474         if (vclk == NULL || sclk == NULL)
 475                 return;
 476
 477         rate = clk_get_rate(sclk);
 478         clk_set_rate(vclk, rate);
 479 }
 480
 481 /*
 482  * Switch the MPU rate if specified on cmdline.
 483  * We cannot do this early until cmdline is parsed.
 484  */
 485 static int __init omap2_clk_arch_init(void)
 486 {
 487         if (!mpurate)
 488                 return -EINVAL;
 489
 490         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
 491                 printk(KERN_ERR "Could not find matching MPU rate\n");
 492
 493         recalculate_root_clocks();
 494
 495         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
 496                "%ld.%01ld/%ld/%ld MHz\n",
 497                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 498                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 499
 500         return 0;
 501 }
 502 arch_initcall(omap2_clk_arch_init);
 503
 504 int __init omap2_clk_init(void)
 505 {
 506         struct prcm_config *prcm;
 507         struct clk **clkp;
 508         u32 clkrate;
 509
 510         if (cpu_is_omap242x())
 511                 cpu_mask = RATE_IN_242X;
 512         else if (cpu_is_omap2430())
 513                 cpu_mask = RATE_IN_243X;
 514
 515         clk_init(&omap2_clk_functions);
 516
 517         omap2_osc_clk_recalc(&osc_ck);
 518         omap2_sys_clk_recalc(&sys_ck);
 519
 520         for (clkp = onchip_24xx_clks;
 521              clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
 522              clkp++) {
 523
 524                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
 525                         clk_register(*clkp);
 526                         omap2_init_clk_clkdm(*clkp);
 527                         continue;
 528                 }
 529
 530                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
 531                         clk_register(*clkp);
 532                         omap2_init_clk_clkdm(*clkp);
 533                         continue;
 534                 }
 535         }
 536
 537         /* Check the MPU rate set by bootloader */
 538         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
 539         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 540                 if (!(prcm->flags & cpu_mask))
 541                         continue;
 542                 if (prcm->xtal_speed != sys_ck.rate)
 543                         continue;
 544                 if (prcm->dpll_speed <= clkrate)
 545                          break;
 546         }
 547         curr_prcm_set = prcm;
 548
 549         recalculate_root_clocks();
 550
 551         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
 552                "%ld.%01ld/%ld/%ld MHz\n",
 553                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 554                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 555
 556         /*
 557          * Only enable those clocks we will need, let the drivers
 558          * enable other clocks as necessary
 559          */
 560         clk_enable_init_clocks();
 561
 562         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
 563         vclk = clk_get(NULL, "virt_prcm_set");
 564         sclk = clk_get(NULL, "sys_ck");
 565
 566         return 0;
 567 }