2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <mach/control.h>
33 #include <asm/div64.h>
35 #include <mach/sdrc.h>
39 #include "prm-regbits-24xx.h"
41 #include "cm-regbits-24xx.h"
42 #include "cm-regbits-34xx.h"
44 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
47 #define DPLL_MIN_MULTIPLIER 1
48 #define DPLL_MIN_DIVIDER 1
50 /* Possible error results from _dpll_test_mult */
51 #define DPLL_MULT_UNDERFLOW (1 << 0)
54 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
55 * The higher the scale factor, the greater the risk of arithmetic overflow,
56 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
57 * must be a power of DPLL_SCALE_BASE.
59 #define DPLL_SCALE_FACTOR 64
60 #define DPLL_SCALE_BASE 2
61 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
62 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /* Some OMAP2xxx CM_CLKSEL_PLL.ST_CORE_CLK bits - for omap2_get_dpll_rate() */
65 #define ST_CORE_CLK_REF 0x1
66 #define ST_CORE_CLK_32K 0x3
68 /* Bitmask to isolate the register type of clk.enable_reg */
69 #define PRCM_REGTYPE_MASK 0xf0
70 /* various CM register type options */
71 #define CM_FCLKEN_REGTYPE 0x00
72 #define CM_ICLKEN_REGTYPE 0x10
73 #define CM_IDLEST_REGTYPE 0x20
77 /*-------------------------------------------------------------------------
78 * OMAP2/3 specific clock functions
79 *-------------------------------------------------------------------------*/
82 * _omap2_clk_read_reg - read a clock register
85 * Given a struct clk *, returns the value of the clock's register.
87 static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
89 if (clk->prcm_mod & CLK_REG_IN_SCM)
90 return omap_ctrl_readl(reg_offset);
91 else if (clk->prcm_mod & CLK_REG_IN_PRM)
92 return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
95 return cm_read_mod_reg(clk->prcm_mod, reg_offset);
99 * _omap2_clk_write_reg - write a clock's register
100 * @v: value to write to the clock's enable_reg
103 * Given a register value @v and struct clk * @clk, writes the value of @v to
104 * the clock's enable register. No return value.
106 static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
108 if (clk->prcm_mod & CLK_REG_IN_SCM)
109 omap_ctrl_writel(v, reg_offset);
110 else if (clk->prcm_mod & CLK_REG_IN_PRM)
111 prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
114 cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
119 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
120 * @clk: OMAP clock struct ptr to use
122 * Convert a clockdomain name stored in a struct clk 'clk' into a
123 * clockdomain pointer, and save it into the struct clk. Intended to be
124 * called during clk_register(). No return value.
126 void omap2_init_clk_clkdm(struct clk *clk)
128 struct clockdomain *clkdm;
130 if (!clk->clkdm.name) {
131 pr_err("clock: %s: missing clockdomain", clk->name);
135 clkdm = clkdm_lookup(clk->clkdm.name);
137 pr_debug("clock: associated clk %s to clkdm %s\n",
138 clk->name, clk->clkdm.name);
139 clk->clkdm.ptr = clkdm;
141 pr_err("clock: %s: could not associate to clkdm %s\n",
142 clk->name, clk->clkdm.name);
147 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
148 * @clk: OMAP clock struct ptr to use
150 * Given a pointer to a source-selectable struct clk, read the hardware
151 * register and determine what its parent is currently set to. Update the
152 * clk->parent field with the appropriate clk ptr.
154 void omap2_init_clksel_parent(struct clk *clk)
156 const struct clksel *clks;
157 const struct clksel_rate *clkr;
163 r = _omap2_clk_read_reg(clk->clksel_reg, clk);
164 r &= clk->clksel_mask;
165 r >>= __ffs(clk->clksel_mask);
167 for (clks = clk->clksel; clks->parent && !found; clks++) {
168 for (clkr = clks->rates; clkr->div && !found; clkr++) {
169 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
170 if (clk->parent != clks->parent) {
171 pr_debug("clock: inited %s parent "
173 clk->name, clks->parent->name,
175 clk->parent->name : "NULL"));
176 clk->parent = clks->parent;
184 printk(KERN_ERR "clock: init parent: could not find "
185 "regval %0x for clock %s\n", r, clk->name);
191 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
192 * @clk: struct clk * of a DPLL
194 * DPLLs can be locked or bypassed - basically, enabled or disabled.
195 * When locked, the DPLL output depends on the M and N values. When
196 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
197 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
198 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
199 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
200 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
201 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
202 * if the clock @clk is not a DPLL.
204 u32 omap2_get_dpll_rate(struct clk *clk)
207 u32 dpll_mult, dpll_div, v;
208 struct dpll_data *dd;
214 /* Return bypass rate if DPLL is bypassed */
215 v = cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg);
216 v &= dd->idlest_mask;
217 v >>= __ffs(dd->idlest_mask);
218 if (cpu_is_omap24xx()) {
220 if (v == ST_CORE_CLK_REF)
221 return clk->parent->rate; /* sys_clk */
222 else if (v == ST_CORE_CLK_32K)
225 } else if (cpu_is_omap34xx()) {
228 return dd->bypass_clk->rate;
232 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
233 dpll_mult = v & dd->mult_mask;
234 dpll_mult >>= __ffs(dd->mult_mask);
235 dpll_div = v & dd->div1_mask;
236 dpll_div >>= __ffs(dd->div1_mask);
238 dpll_clk = (long long)clk->parent->rate * dpll_mult;
239 do_div(dpll_clk, dpll_div + 1);
245 * Used for clocks that have the same value as the parent clock,
246 * divided by some factor
248 void omap2_fixed_divisor_recalc(struct clk *clk)
250 WARN_ON(!clk->fixed_div);
252 clk->rate = clk->parent->rate / clk->fixed_div;
254 if (clk->flags & RATE_PROPAGATES)
259 * omap2_wait_clock_ready - wait for clock to enable
260 * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
261 * @reg_index: offset of CM register address from prcm_mod
262 * @mask: value to mask against to determine if the clock is active
263 * @name: name of the clock (for printk)
265 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
266 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
268 int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
274 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
275 * 34xx reverses this, just to keep us on our toes
277 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
279 else if (cpu_mask & RATE_IN_343X)
283 while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
284 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
288 if (i < MAX_CLOCK_ENABLE_WAIT)
289 pr_debug("Clock %s stable after %d loops\n", name, i);
291 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
292 name, MAX_CLOCK_ENABLE_WAIT);
294 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
299 * Note: We don't need special code here for INVERT_ENABLE
300 * for the time being since INVERT_ENABLE only applies to clocks enabled by
303 * REVISIT: This code is ugly and does not belong here.
305 static void omap2_clk_wait_ready(struct clk *clk)
307 u16 other_reg, idlest_reg;
308 u32 other_bit, idlest_bit;
310 /* Only CM-controlled clocks affect module IDLEST */
311 if (clk->prcm_mod & ~PRCM_MOD_ADDR_MASK)
314 other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK;
316 /* If we are enabling an iclk, also test the fclk; and vice versa */
317 if (clk->enable_reg & CM_ICLKEN_REGTYPE)
318 other_reg |= CM_FCLKEN_REGTYPE;
320 other_reg |= CM_ICLKEN_REGTYPE;
322 /* Covers most of the cases - a few exceptions are below */
323 other_bit = 1 << clk->enable_bit;
324 idlest_bit = other_bit;
326 /* 24xx: DSS and CAM have no idlest bits for their target agents */
327 if (cpu_is_omap24xx() && clk->prcm_mod == CORE_MOD &&
328 (clk->enable_reg == CM_FCLKEN1 || clk->enable_reg == CM_ICLKEN1)) {
330 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
331 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
332 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
337 /* REVISIT: What are the appropriate exclusions for 34XX? */
338 if (cpu_is_omap34xx()) {
341 if (clk->prcm_mod == CORE_MOD &&
342 (clk->enable_reg == CM_FCLKEN1 ||
343 clk->enable_reg == CM_ICLKEN1) &&
344 clk->enable_bit == OMAP3430_EN_SSI_SHIFT) {
346 if (system_rev == OMAP3430_REV_ES1_0)
349 idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
353 if (clk->prcm_mod == OMAP3430_DSS_MOD) {
355 /* 3430ES1 DSS has no target idlest bits */
356 if (system_rev == OMAP3430_REV_ES1_0)
360 * For 3430ES2+ DSS, only wait once (dss1_alwon_fclk,
361 * dss_l3_iclk, dss_l4_iclk) are enabled
363 if (clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
366 idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
370 if (system_rev > OMAP3430_REV_ES1_0 &&
371 clk->prcm_mod == OMAP3430ES2_USBHOST_MOD) {
374 * The 120MHz clock apparently has nothing to do with
375 * USBHOST module accessibility
377 if (clk->enable_bit == OMAP3430ES2_EN_USBHOST2_SHIFT)
380 idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT;
385 /* Check if both functional and interface clocks are running. */
386 if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit))
389 idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
390 idlest_reg |= CM_IDLEST_REGTYPE;
392 omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, idlest_bit,
396 /* Enables clock without considering parent dependencies or use count
397 * REVISIT: Maybe change this to use clk->enable like on omap1?
399 static int _omap2_clk_enable(struct clk *clk)
403 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
407 return clk->enable(clk);
409 v = _omap2_clk_read_reg(clk->enable_reg, clk);
410 if (clk->flags & INVERT_ENABLE)
411 v &= ~(1 << clk->enable_bit);
413 v |= (1 << clk->enable_bit);
414 _omap2_clk_write_reg(v, clk->enable_reg, clk);
417 omap2_clk_wait_ready(clk);
422 /* Disables clock without considering parent dependencies or use count */
423 static void _omap2_clk_disable(struct clk *clk)
427 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
435 v = _omap2_clk_read_reg(clk->enable_reg, clk);
436 if (clk->flags & INVERT_ENABLE)
437 v |= (1 << clk->enable_bit);
439 v &= ~(1 << clk->enable_bit);
440 _omap2_clk_write_reg(v, clk->enable_reg, clk);
444 void omap2_clk_disable(struct clk *clk)
446 if (clk->usecount > 0 && !(--clk->usecount)) {
447 _omap2_clk_disable(clk);
449 omap2_clk_disable(clk->parent);
451 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
456 int omap2_clk_enable(struct clk *clk)
460 if (clk->usecount++ == 0) {
462 ret = omap2_clk_enable(clk->parent);
470 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
472 ret = _omap2_clk_enable(clk);
476 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
479 omap2_clk_disable(clk->parent);
489 * Used for clocks that are part of CLKSEL_xyz governed clocks.
490 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
492 void omap2_clksel_recalc(struct clk *clk)
496 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
498 div = omap2_clksel_get_divisor(clk);
502 if (clk->rate == (clk->parent->rate / div))
504 clk->rate = clk->parent->rate / div;
506 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
508 if (clk->flags & RATE_PROPAGATES)
513 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
514 * @clk: OMAP struct clk ptr to inspect
515 * @src_clk: OMAP struct clk ptr of the parent clk to search for
517 * Scan the struct clksel array associated with the clock to find
518 * the element associated with the supplied parent clock address.
519 * Returns a pointer to the struct clksel on success or NULL on error.
521 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
524 const struct clksel *clks;
529 for (clks = clk->clksel; clks->parent; clks++) {
530 if (clks->parent == src_clk)
531 break; /* Found the requested parent */
535 printk(KERN_ERR "clock: Could not find parent clock %s in "
536 "clksel array of clock %s\n", src_clk->name,
545 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
546 * @clk: OMAP struct clk to use
547 * @target_rate: desired clock rate
548 * @new_div: ptr to where we should store the divisor
550 * Finds 'best' divider value in an array based on the source and target
551 * rates. The divider array must be sorted with smallest divider first.
552 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
553 * they are only settable as part of virtual_prcm set.
555 * Returns the rounded clock rate or returns 0xffffffff on error.
557 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
560 unsigned long test_rate;
561 const struct clksel *clks;
562 const struct clksel_rate *clkr;
565 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
566 clk->name, target_rate);
570 clks = omap2_get_clksel_by_parent(clk, clk->parent);
574 for (clkr = clks->rates; clkr->div; clkr++) {
575 if (!(clkr->flags & cpu_mask))
579 if (clkr->div <= last_div)
580 printk(KERN_ERR "clock: clksel_rate table not sorted "
581 "for clock %s", clk->name);
583 last_div = clkr->div;
585 test_rate = clk->parent->rate / clkr->div;
587 if (test_rate <= target_rate)
588 break; /* found it */
592 printk(KERN_ERR "clock: Could not find divisor for target "
593 "rate %ld for clock %s parent %s\n", target_rate,
594 clk->name, clk->parent->name);
598 *new_div = clkr->div;
600 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
601 (clk->parent->rate / clkr->div));
603 return (clk->parent->rate / clkr->div);
607 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
608 * @clk: OMAP struct clk to use
609 * @target_rate: desired clock rate
611 * Compatibility wrapper for OMAP clock framework
612 * Finds best target rate based on the source clock and possible dividers.
613 * rates. The divider array must be sorted with smallest divider first.
614 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
615 * they are only settable as part of virtual_prcm set.
617 * Returns the rounded clock rate or returns 0xffffffff on error.
619 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
623 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
627 /* Given a clock and a rate apply a clock specific rounding function */
628 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
630 if (clk->round_rate != NULL)
631 return clk->round_rate(clk, rate);
633 if (clk->flags & RATE_FIXED)
634 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
635 "on fixed-rate clock %s\n", clk->name);
641 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
642 * @clk: OMAP struct clk to use
643 * @field_val: register field value to find
645 * Given a struct clk of a rate-selectable clksel clock, and a register field
646 * value to search for, find the corresponding clock divisor. The register
647 * field value should be pre-masked and shifted down so the LSB is at bit 0
648 * before calling. Returns 0 on error
650 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
652 const struct clksel *clks;
653 const struct clksel_rate *clkr;
655 clks = omap2_get_clksel_by_parent(clk, clk->parent);
659 for (clkr = clks->rates; clkr->div; clkr++) {
660 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
665 printk(KERN_ERR "clock: Could not find fieldval %d for "
666 "clock %s parent %s\n", field_val, clk->name,
675 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
676 * @clk: OMAP struct clk to use
677 * @div: integer divisor to search for
679 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
680 * find the corresponding register field value. The return register value is
681 * the value before left-shifting. Returns 0xffffffff on error
683 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
685 const struct clksel *clks;
686 const struct clksel_rate *clkr;
688 /* should never happen */
691 clks = omap2_get_clksel_by_parent(clk, clk->parent);
695 for (clkr = clks->rates; clkr->div; clkr++) {
696 if ((clkr->flags & cpu_mask) && (clkr->div == div))
701 printk(KERN_ERR "clock: Could not find divisor %d for "
702 "clock %s parent %s\n", div, clk->name,
711 * omap2_clksel_get_divisor - get current divider applied to parent clock.
712 * @clk: OMAP struct clk to use.
714 * Returns the integer divisor upon success or 0 on error.
716 u32 omap2_clksel_get_divisor(struct clk *clk)
720 if (!clk->clksel_mask)
723 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
724 v &= clk->clksel_mask;
725 v >>= __ffs(clk->clksel_mask);
727 return omap2_clksel_to_divisor(clk, v);
730 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
732 u32 v, field_val, validrate, new_div = 0;
734 if (!clk->clksel_mask)
737 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
738 if (validrate != rate)
741 field_val = omap2_divisor_to_clksel(clk, new_div);
745 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
746 v &= ~clk->clksel_mask;
747 v |= field_val << __ffs(clk->clksel_mask);
748 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
752 clk->rate = clk->parent->rate / new_div;
754 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
755 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
756 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
764 /* Set the clock rate for a clock source */
765 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
769 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
771 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
772 rate table mechanism, driven by mpu_speed */
773 if (clk->flags & CONFIG_PARTICIPANT)
776 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
777 if (clk->set_rate != NULL)
778 ret = clk->set_rate(clk, rate);
780 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
787 * Converts encoded control register address into a full address
788 * On error, the return value (parent_div) will be 0.
790 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
793 const struct clksel *clks;
794 const struct clksel_rate *clkr;
796 clks = omap2_get_clksel_by_parent(clk, src_clk);
800 for (clkr = clks->rates; clkr->div; clkr++) {
801 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
802 break; /* Found the default rate for this platform */
806 printk(KERN_ERR "clock: Could not find default rate for "
807 "clock %s parent %s\n", clk->name,
808 src_clk->parent->name);
812 /* Should never happen. Add a clksel mask to the struct clk. */
813 WARN_ON(clk->clksel_mask == 0);
815 *field_val = clkr->val;
820 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
822 u32 field_val, v, parent_div;
824 if (clk->flags & CONFIG_PARTICIPANT)
830 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
834 if (clk->usecount > 0)
835 _omap2_clk_disable(clk);
837 /* Set new source value (previous dividers if any in effect) */
838 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
839 v &= ~clk->clksel_mask;
840 v |= field_val << __ffs(clk->clksel_mask);
841 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
844 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
845 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
846 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
850 if (clk->usecount > 0)
851 _omap2_clk_enable(clk);
853 clk->parent = new_parent;
855 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
856 clk->rate = new_parent->rate;
859 clk->rate /= parent_div;
861 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
862 clk->name, clk->parent->name, clk->rate);
864 if (clk->flags & RATE_PROPAGATES)
870 /* DPLL rate rounding code */
873 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
874 * @clk: struct clk * of the DPLL
875 * @tolerance: maximum rate error tolerance
877 * Set the maximum DPLL rate error tolerance for the rate rounding
878 * algorithm. The rate tolerance is an attempt to balance DPLL power
879 * saving (the least divider value "n") vs. rate fidelity (the least
880 * difference between the desired DPLL target rate and the rounded
881 * rate out of the algorithm). So, increasing the tolerance is likely
882 * to decrease DPLL power consumption and increase DPLL rate error.
883 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
884 * DPLL; or 0 upon success.
886 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
888 if (!clk || !clk->dpll_data)
891 clk->dpll_data->rate_tolerance = tolerance;
896 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
897 unsigned int m, unsigned int n)
899 unsigned long long num;
901 num = (unsigned long long)parent_rate * m;
907 * _dpll_test_mult - test a DPLL multiplier value
908 * @m: pointer to the DPLL m (multiplier) value under test
909 * @n: current DPLL n (divider) value under test
910 * @new_rate: pointer to storage for the resulting rounded rate
911 * @target_rate: the desired DPLL rate
912 * @parent_rate: the DPLL's parent clock rate
914 * This code tests a DPLL multiplier value, ensuring that the
915 * resulting rate will not be higher than the target_rate, and that
916 * the multiplier value itself is valid for the DPLL. Initially, the
917 * integer pointed to by the m argument should be prescaled by
918 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
919 * a non-scaled m upon return. This non-scaled m will result in a
920 * new_rate as close as possible to target_rate (but not greater than
921 * target_rate) given the current (parent_rate, n, prescaled m)
922 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
923 * non-scaled m attempted to underflow, which can allow the calling
924 * function to bail out early; or 0 upon success.
926 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
927 unsigned long target_rate,
928 unsigned long parent_rate)
930 int flags = 0, carry = 0;
932 /* Unscale m and round if necessary */
933 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
935 *m = (*m / DPLL_SCALE_FACTOR) + carry;
938 * The new rate must be <= the target rate to avoid programming
939 * a rate that is impossible for the hardware to handle
941 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
942 if (*new_rate > target_rate) {
947 /* Guard against m underflow */
948 if (*m < DPLL_MIN_MULTIPLIER) {
949 *m = DPLL_MIN_MULTIPLIER;
951 flags = DPLL_MULT_UNDERFLOW;
955 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
961 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
962 * @clk: struct clk * for a DPLL
963 * @target_rate: desired DPLL clock rate
965 * Given a DPLL, a desired target rate, and a rate tolerance, round
966 * the target rate to a possible, programmable rate for this DPLL.
967 * Rate tolerance is assumed to be set by the caller before this
968 * function is called. Attempts to select the minimum possible n
969 * within the tolerance to reduce power consumption. Stores the
970 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
971 * will not need to call this (expensive) function again. Returns ~0
972 * if the target rate cannot be rounded, either because the rate is
973 * too low or because the rate tolerance is set too tightly; or the
974 * rounded rate upon success.
976 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
978 int m, n, r, e, scaled_max_m;
979 unsigned long scaled_rt_rp, new_rate;
980 int min_e = -1, min_e_m = -1, min_e_n = -1;
982 if (!clk || !clk->dpll_data)
985 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
986 "%ld\n", clk->name, target_rate);
988 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
989 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
991 clk->dpll_data->last_rounded_rate = 0;
993 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
995 /* Compute the scaled DPLL multiplier, based on the divider */
996 m = scaled_rt_rp * n;
999 * Since we're counting n down, a m overflow means we can
1000 * can immediately skip to the next n
1002 if (m > scaled_max_m)
1005 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1008 e = target_rate - new_rate;
1009 pr_debug("clock: n = %d: m = %d: rate error is %d "
1010 "(new_rate = %ld)\n", n, m, e, new_rate);
1013 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
1018 pr_debug("clock: found new least error %d\n", min_e);
1022 * Since we're counting n down, a m underflow means we
1023 * can bail out completely (since as n decreases in
1024 * the next iteration, there's no way that m can
1025 * increase beyond the current m)
1027 if (r & DPLL_MULT_UNDERFLOW)
1032 pr_debug("clock: error: target rate or tolerance too low\n");
1036 clk->dpll_data->last_rounded_m = min_e_m;
1037 clk->dpll_data->last_rounded_n = min_e_n;
1038 clk->dpll_data->last_rounded_rate =
1039 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
1041 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1042 min_e, min_e_m, min_e_n);
1043 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1044 clk->dpll_data->last_rounded_rate, target_rate);
1046 return clk->dpll_data->last_rounded_rate;
1049 /*-------------------------------------------------------------------------
1050 * Omap2 clock reset and init functions
1051 *-------------------------------------------------------------------------*/
1053 #ifdef CONFIG_OMAP_RESET_CLOCKS
1054 void omap2_clk_disable_unused(struct clk *clk)
1058 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1060 regval32 = _omap2_clk_read_reg(clk->enable_reg, clk);
1061 if ((regval32 & (1 << clk->enable_bit)) == v)
1064 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1065 _omap2_clk_disable(clk);