2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <mach/control.h>
33 #include <asm/div64.h>
35 #include <mach/sdrc.h>
39 #include "prm-regbits-24xx.h"
41 #include "cm-regbits-24xx.h"
42 #include "cm-regbits-34xx.h"
44 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
47 #define DPLL_MIN_MULTIPLIER 1
48 #define DPLL_MIN_DIVIDER 1
50 /* Possible error results from _dpll_test_mult */
51 #define DPLL_MULT_UNDERFLOW -1
54 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
55 * The higher the scale factor, the greater the risk of arithmetic overflow,
56 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
57 * must be a power of DPLL_SCALE_BASE.
59 #define DPLL_SCALE_FACTOR 64
60 #define DPLL_SCALE_BASE 2
61 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
62 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
65 #define DPLL_FINT_BAND1_MIN 750000
66 #define DPLL_FINT_BAND1_MAX 2100000
67 #define DPLL_FINT_BAND2_MIN 7500000
68 #define DPLL_FINT_BAND2_MAX 21000000
70 /* _dpll_test_fint() return codes */
71 #define DPLL_FINT_UNDERFLOW -1
72 #define DPLL_FINT_INVALID -2
74 /* Bitmask to isolate the register type of clk.enable_reg */
75 #define PRCM_REGTYPE_MASK 0xf0
76 /* various CM register type options */
77 #define CM_FCLKEN_REGTYPE 0x00
78 #define CM_ICLKEN_REGTYPE 0x10
79 #define CM_IDLEST_REGTYPE 0x20
83 /*-------------------------------------------------------------------------
84 * OMAP2/3 specific clock functions
85 *-------------------------------------------------------------------------*/
88 * _omap2_clk_read_reg - read a clock register
91 * Given a struct clk *, returns the value of the clock's register.
93 static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
95 if (clk->prcm_mod & CLK_REG_IN_SCM)
96 return omap_ctrl_readl(reg_offset);
97 else if (clk->prcm_mod & CLK_REG_IN_PRM)
98 return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
101 return cm_read_mod_reg(clk->prcm_mod, reg_offset);
105 * _omap2_clk_write_reg - write a clock's register
106 * @v: value to write to the clock's enable_reg
109 * Given a register value @v and struct clk * @clk, writes the value of @v to
110 * the clock's enable register. No return value.
112 static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
114 if (clk->prcm_mod & CLK_REG_IN_SCM)
115 omap_ctrl_writel(v, reg_offset);
116 else if (clk->prcm_mod & CLK_REG_IN_PRM)
117 prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
120 cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
124 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
127 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
128 * don't take effect until the VALID_CONFIG bit is written, write the
129 * VALID_CONFIG bit and wait for the write to complete. No return value.
131 static void _omap2xxx_clk_commit(struct clk *clk)
133 if (!cpu_is_omap24xx())
136 if (!(clk->flags & DELAYED_APP))
139 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
140 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
142 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
146 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
147 * @clk: DPLL struct clk to test
148 * @n: divider value (N) to test
150 * Tests whether a particular divider @n will result in a valid DPLL
151 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
152 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
153 * (assuming that it is counting N upwards), or -2 if the enclosing loop
154 * should skip to the next iteration (again assuming N is increasing).
156 static int _dpll_test_fint(struct clk *clk, u8 n)
158 struct dpll_data *dd;
164 /* DPLL divider must result in a valid jitter correction val */
165 fint = clk->parent->rate / (n + 1);
166 if (fint < DPLL_FINT_BAND1_MIN) {
168 pr_debug("rejecting n=%d due to Fint failure, "
169 "lowering max_divider\n", n);
171 ret = DPLL_FINT_UNDERFLOW;
173 } else if (fint > DPLL_FINT_BAND1_MAX &&
174 fint < DPLL_FINT_BAND2_MIN) {
176 pr_debug("rejecting n=%d due to Fint failure\n", n);
177 ret = DPLL_FINT_INVALID;
179 } else if (fint > DPLL_FINT_BAND2_MAX) {
181 pr_debug("rejecting n=%d due to Fint failure, "
182 "boosting min_divider\n", n);
184 ret = DPLL_FINT_INVALID;
192 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
193 * @clk: OMAP clock struct ptr to use
195 * Convert a clockdomain name stored in a struct clk 'clk' into a
196 * clockdomain pointer, and save it into the struct clk. Intended to be
197 * called during clk_register(). No return value.
199 void omap2_init_clk_clkdm(struct clk *clk)
201 struct clockdomain *clkdm;
203 if (!clk->clkdm.name) {
204 pr_err("clock: %s: missing clockdomain", clk->name);
208 clkdm = clkdm_lookup(clk->clkdm.name);
210 pr_debug("clock: associated clk %s to clkdm %s\n",
211 clk->name, clk->clkdm.name);
212 clk->clkdm.ptr = clkdm;
214 pr_err("clock: %s: could not associate to clkdm %s\n",
215 clk->name, clk->clkdm.name);
220 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
221 * @clk: OMAP clock struct ptr to use
223 * Given a pointer to a source-selectable struct clk, read the hardware
224 * register and determine what its parent is currently set to. Update the
225 * clk->parent field with the appropriate clk ptr.
227 void omap2_init_clksel_parent(struct clk *clk)
229 const struct clksel *clks;
230 const struct clksel_rate *clkr;
236 r = _omap2_clk_read_reg(clk->clksel_reg, clk);
237 r &= clk->clksel_mask;
238 r >>= __ffs(clk->clksel_mask);
240 for (clks = clk->clksel; clks->parent && !found; clks++) {
241 for (clkr = clks->rates; clkr->div && !found; clkr++) {
242 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
243 if (clk->parent != clks->parent) {
244 pr_debug("clock: inited %s parent "
246 clk->name, clks->parent->name,
248 clk->parent->name : "NULL"));
250 omap_clk_del_child(clk->parent,
252 clk->parent = clks->parent;
253 omap_clk_add_child(clk->parent, clk);
261 printk(KERN_ERR "clock: init parent: could not find "
262 "regval %0x for clock %s\n", r, clk->name);
268 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
269 * @clk: struct clk * of a DPLL
270 * @parent_rate: rate of the parent of the DPLL clock
272 * DPLLs can be locked or bypassed - basically, enabled or disabled.
273 * When locked, the DPLL output depends on the M and N values. When
274 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
275 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
276 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
277 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
278 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
279 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
280 * if the clock @clk is not a DPLL.
282 u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate)
285 u32 dpll_mult, dpll_div, v;
286 struct dpll_data *dd;
292 /* Return bypass rate if DPLL is bypassed */
293 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
294 v &= dd->enable_mask;
295 v >>= __ffs(dd->enable_mask);
297 if (cpu_is_omap24xx()) {
299 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
300 v == OMAP2XXX_EN_DPLL_FRBYPASS)
303 } else if (cpu_is_omap34xx()) {
305 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
306 v == OMAP3XXX_EN_DPLL_FRBYPASS)
307 return dd->bypass_clk->rate;
311 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
312 dpll_mult = v & dd->mult_mask;
313 dpll_mult >>= __ffs(dd->mult_mask);
314 dpll_div = v & dd->div1_mask;
315 dpll_div >>= __ffs(dd->div1_mask);
317 dpll_clk = (long long)parent_rate * dpll_mult;
318 do_div(dpll_clk, dpll_div + 1);
324 * Used for clocks that have the same value as the parent clock,
325 * divided by some factor
327 void omap2_fixed_divisor_recalc(struct clk *clk, unsigned long parent_rate,
332 WARN_ON(!clk->fixed_div); /* XXX move this to init */
334 rate = parent_rate / clk->fixed_div;
336 if (rate_storage == CURRENT_RATE)
338 else if (rate_storage == TEMP_RATE)
339 clk->temp_rate = rate;
343 * omap2_wait_clock_ready - wait for clock to enable
344 * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
345 * @reg_index: offset of CM register address from prcm_mod
346 * @mask: value to mask against to determine if the clock is active
347 * @name: name of the clock (for printk)
349 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
350 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
352 int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
358 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
359 * 34xx reverses this, just to keep us on our toes
361 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
363 else if (cpu_mask & RATE_IN_343X)
367 while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
368 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
372 if (i < MAX_CLOCK_ENABLE_WAIT)
373 pr_debug("Clock %s stable after %d loops\n", name, i);
375 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
376 name, MAX_CLOCK_ENABLE_WAIT);
378 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
383 * omap2_clk_wait_ready - wait for a OMAP module to come out of target idle
384 * @clk: struct clk * recently enabled to indicate the module to test
386 * Wait for an OMAP module with a target idle state bit to come out of
387 * idle once both its interface clock and primary functional clock are
388 * both enabled. Any register read or write to the device before it
389 * returns from idle will cause an abort. Not all modules have target
390 * idle state bits (for example, DSS and CAM on OMAP24xx); so we don't
391 * wait for those. No return value.
393 * We don't need special code here for INVERT_ENABLE for the time
394 * being since INVERT_ENABLE only applies to clocks enabled by
397 * REVISIT: This function is misnamed: it should be something like
398 * "omap2_module_wait_ready", and in the long-term, it does not belong
399 * in the clock framework. It also shouldn't be doing register
400 * arithmetic to determine the companion clock.
402 static void omap2_clk_wait_ready(struct clk *clk)
404 u16 other_reg, idlest_reg;
407 if (!(clk->flags & WAIT_READY))
410 /* If we are enabling an iclk, also test the fclk; and vice versa */
411 other_bit = 1 << clk->enable_bit;
412 other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK;
414 if (clk->enable_reg & CM_ICLKEN_REGTYPE)
415 other_reg |= CM_FCLKEN_REGTYPE;
417 other_reg |= CM_ICLKEN_REGTYPE;
419 /* Ensure functional and interface clocks are running. */
420 if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit))
423 idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
424 idlest_reg |= CM_IDLEST_REGTYPE;
426 omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, 1 << clk->idlest_bit,
430 /* Enables clock without considering parent dependencies or use count
431 * REVISIT: Maybe change this to use clk->enable like on omap1?
433 static int _omap2_clk_enable(struct clk *clk)
437 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
441 return clk->enable(clk);
443 v = _omap2_clk_read_reg(clk->enable_reg, clk);
444 if (clk->flags & INVERT_ENABLE)
445 v &= ~(1 << clk->enable_bit);
447 v |= (1 << clk->enable_bit);
448 _omap2_clk_write_reg(v, clk->enable_reg, clk);
449 v = _omap2_clk_read_reg(clk->enable_reg, clk); /* OCP barrier */
451 omap2_clk_wait_ready(clk);
456 /* Disables clock without considering parent dependencies or use count */
457 static void _omap2_clk_disable(struct clk *clk)
461 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
469 v = _omap2_clk_read_reg(clk->enable_reg, clk);
470 if (clk->flags & INVERT_ENABLE)
471 v |= (1 << clk->enable_bit);
473 v &= ~(1 << clk->enable_bit);
474 _omap2_clk_write_reg(v, clk->enable_reg, clk);
475 /* No OCP barrier needed here since it is a disable operation */
478 void omap2_clk_disable(struct clk *clk)
480 if (clk->usecount > 0 && !(--clk->usecount)) {
481 _omap2_clk_disable(clk);
483 omap2_clk_disable(clk->parent);
485 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
490 int omap2_clk_enable(struct clk *clk)
494 if (clk->usecount++ == 0) {
496 ret = omap2_clk_enable(clk->parent);
504 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
506 ret = _omap2_clk_enable(clk);
510 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
513 omap2_clk_disable(clk->parent);
523 * Used for clocks that are part of CLKSEL_xyz governed clocks.
524 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
526 void omap2_clksel_recalc(struct clk *clk, unsigned long parent_rate,
532 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
534 div = omap2_clksel_get_divisor(clk);
538 rate = parent_rate / div;
540 if (rate_storage == CURRENT_RATE)
542 else if (rate_storage == TEMP_RATE)
543 clk->temp_rate = rate;
545 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
549 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
550 * @clk: OMAP struct clk ptr to inspect
551 * @src_clk: OMAP struct clk ptr of the parent clk to search for
553 * Scan the struct clksel array associated with the clock to find
554 * the element associated with the supplied parent clock address.
555 * Returns a pointer to the struct clksel on success or NULL on error.
557 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
560 const struct clksel *clks;
565 for (clks = clk->clksel; clks->parent; clks++) {
566 if (clks->parent == src_clk)
567 break; /* Found the requested parent */
571 printk(KERN_ERR "clock: Could not find parent clock %s in "
572 "clksel array of clock %s\n", src_clk->name,
581 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
582 * @clk: OMAP struct clk to use
583 * @target_rate: desired clock rate
584 * @new_div: ptr to where we should store the divisor
586 * Finds 'best' divider value in an array based on the source and target
587 * rates. The divider array must be sorted with smallest divider first.
589 * Returns the rounded clock rate or returns 0xffffffff on error.
591 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
594 unsigned long test_rate;
595 const struct clksel *clks;
596 const struct clksel_rate *clkr;
599 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
600 clk->name, target_rate);
604 clks = omap2_get_clksel_by_parent(clk, clk->parent);
608 for (clkr = clks->rates; clkr->div; clkr++) {
609 if (!(clkr->flags & cpu_mask))
613 if (clkr->div <= last_div)
614 printk(KERN_ERR "clock: clksel_rate table not sorted "
615 "for clock %s", clk->name);
617 last_div = clkr->div;
619 test_rate = clk->parent->rate / clkr->div;
621 if (test_rate <= target_rate)
622 break; /* found it */
626 printk(KERN_ERR "clock: Could not find divisor for target "
627 "rate %ld for clock %s parent %s\n", target_rate,
628 clk->name, clk->parent->name);
632 *new_div = clkr->div;
634 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
635 (clk->parent->rate / clkr->div));
637 return (clk->parent->rate / clkr->div);
641 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
642 * @clk: OMAP struct clk to use
643 * @target_rate: desired clock rate
645 * Compatibility wrapper for OMAP clock framework
646 * Finds best target rate based on the source clock and possible dividers.
647 * rates. The divider array must be sorted with smallest divider first.
649 * Returns the rounded clock rate or returns 0xffffffff on error.
651 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
655 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
659 /* Given a clock and a rate apply a clock specific rounding function */
660 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
662 if (clk->round_rate != NULL)
663 return clk->round_rate(clk, rate);
669 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
670 * @clk: OMAP struct clk to use
671 * @field_val: register field value to find
673 * Given a struct clk of a rate-selectable clksel clock, and a register field
674 * value to search for, find the corresponding clock divisor. The register
675 * field value should be pre-masked and shifted down so the LSB is at bit 0
676 * before calling. Returns 0 on error
678 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
680 const struct clksel *clks;
681 const struct clksel_rate *clkr;
683 clks = omap2_get_clksel_by_parent(clk, clk->parent);
687 for (clkr = clks->rates; clkr->div; clkr++) {
688 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
693 printk(KERN_ERR "clock: Could not find fieldval %d for "
694 "clock %s parent %s\n", field_val, clk->name,
703 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
704 * @clk: OMAP struct clk to use
705 * @div: integer divisor to search for
707 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
708 * find the corresponding register field value. The return register value is
709 * the value before left-shifting. Returns 0xffffffff on error
711 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
713 const struct clksel *clks;
714 const struct clksel_rate *clkr;
716 /* should never happen */
719 clks = omap2_get_clksel_by_parent(clk, clk->parent);
723 for (clkr = clks->rates; clkr->div; clkr++) {
724 if ((clkr->flags & cpu_mask) && (clkr->div == div))
729 printk(KERN_ERR "clock: Could not find divisor %d for "
730 "clock %s parent %s\n", div, clk->name,
739 * omap2_clksel_get_divisor - get current divider applied to parent clock.
740 * @clk: OMAP struct clk to use.
742 * Returns the integer divisor upon success or 0 on error.
744 u32 omap2_clksel_get_divisor(struct clk *clk)
748 if (!clk->clksel_mask)
751 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
752 v &= clk->clksel_mask;
753 v >>= __ffs(clk->clksel_mask);
755 return omap2_clksel_to_divisor(clk, v);
758 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
760 u32 v, field_val, validrate, new_div = 0;
762 if (!clk->clksel_mask)
765 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
766 if (validrate != rate)
769 field_val = omap2_divisor_to_clksel(clk, new_div);
773 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
774 v &= ~clk->clksel_mask;
775 v |= field_val << __ffs(clk->clksel_mask);
776 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
777 v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
779 clk->rate = clk->parent->rate / new_div;
781 _omap2xxx_clk_commit(clk);
787 /* Set the clock rate for a clock source */
788 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
792 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
794 if (clk->set_rate != NULL)
795 ret = clk->set_rate(clk, rate);
801 * Converts encoded control register address into a full address
802 * On error, the return value (parent_div) will be 0.
804 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
807 const struct clksel *clks;
808 const struct clksel_rate *clkr;
810 clks = omap2_get_clksel_by_parent(clk, src_clk);
814 for (clkr = clks->rates; clkr->div; clkr++) {
815 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
816 break; /* Found the default rate for this platform */
820 printk(KERN_ERR "clock: Could not find default rate for "
821 "clock %s parent %s\n", clk->name,
822 src_clk->parent->name);
826 /* Should never happen. Add a clksel mask to the struct clk. */
827 WARN_ON(clk->clksel_mask == 0);
829 *field_val = clkr->val;
834 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
836 u32 field_val, v, parent_div;
841 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
845 if (clk->usecount > 0)
846 _omap2_clk_disable(clk);
848 /* Set new source value (previous dividers if any in effect) */
849 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
850 v &= ~clk->clksel_mask;
851 v |= field_val << __ffs(clk->clksel_mask);
852 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
853 v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
855 _omap2xxx_clk_commit(clk);
857 if (clk->usecount > 0)
858 _omap2_clk_enable(clk);
860 clk->parent = new_parent;
862 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
863 clk->rate = new_parent->rate;
866 clk->rate /= parent_div;
868 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
869 clk->name, clk->parent->name, clk->rate);
874 struct clk *omap2_clk_get_parent(struct clk *clk)
879 /* DPLL rate rounding code */
882 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
883 * @clk: struct clk * of the DPLL
884 * @tolerance: maximum rate error tolerance
886 * Set the maximum DPLL rate error tolerance for the rate rounding
887 * algorithm. The rate tolerance is an attempt to balance DPLL power
888 * saving (the least divider value "n") vs. rate fidelity (the least
889 * difference between the desired DPLL target rate and the rounded
890 * rate out of the algorithm). So, increasing the tolerance is likely
891 * to decrease DPLL power consumption and increase DPLL rate error.
892 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
893 * DPLL; or 0 upon success.
895 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
897 if (!clk || !clk->dpll_data)
900 clk->dpll_data->rate_tolerance = tolerance;
905 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
906 unsigned int m, unsigned int n)
908 unsigned long long num;
910 num = (unsigned long long)parent_rate * m;
916 * _dpll_test_mult - test a DPLL multiplier value
917 * @m: pointer to the DPLL m (multiplier) value under test
918 * @n: current DPLL n (divider) value under test
919 * @new_rate: pointer to storage for the resulting rounded rate
920 * @target_rate: the desired DPLL rate
921 * @parent_rate: the DPLL's parent clock rate
923 * This code tests a DPLL multiplier value, ensuring that the
924 * resulting rate will not be higher than the target_rate, and that
925 * the multiplier value itself is valid for the DPLL. Initially, the
926 * integer pointed to by the m argument should be prescaled by
927 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
928 * a non-scaled m upon return. This non-scaled m will result in a
929 * new_rate as close as possible to target_rate (but not greater than
930 * target_rate) given the current (parent_rate, n, prescaled m)
931 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
932 * non-scaled m attempted to underflow, which can allow the calling
933 * function to bail out early; or 0 upon success.
935 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
936 unsigned long target_rate,
937 unsigned long parent_rate)
939 int r = 0, carry = 0;
941 /* Unscale m and round if necessary */
942 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
944 *m = (*m / DPLL_SCALE_FACTOR) + carry;
947 * The new rate must be <= the target rate to avoid programming
948 * a rate that is impossible for the hardware to handle
950 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
951 if (*new_rate > target_rate) {
956 /* Guard against m underflow */
957 if (*m < DPLL_MIN_MULTIPLIER) {
958 *m = DPLL_MIN_MULTIPLIER;
960 r = DPLL_MULT_UNDERFLOW;
964 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
970 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
971 * @clk: struct clk * for a DPLL
972 * @target_rate: desired DPLL clock rate
974 * Given a DPLL, a desired target rate, and a rate tolerance, round
975 * the target rate to a possible, programmable rate for this DPLL.
976 * Rate tolerance is assumed to be set by the caller before this
977 * function is called. Attempts to select the minimum possible n
978 * within the tolerance to reduce power consumption. Stores the
979 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
980 * will not need to call this (expensive) function again. Returns ~0
981 * if the target rate cannot be rounded, either because the rate is
982 * too low or because the rate tolerance is set too tightly; or the
983 * rounded rate upon success.
985 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
987 int m, n, r, e, scaled_max_m;
988 unsigned long scaled_rt_rp, new_rate;
989 int min_e = -1, min_e_m = -1, min_e_n = -1;
990 struct dpll_data *dd;
992 if (!clk || !clk->dpll_data)
997 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
998 "%ld\n", clk->name, target_rate);
1000 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
1001 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
1003 dd->last_rounded_rate = 0;
1005 for (n = dd->min_divider; n <= dd->max_divider; n++) {
1007 /* Is the (input clk, divider) pair valid for the DPLL? */
1008 r = _dpll_test_fint(clk, n);
1009 if (r == DPLL_FINT_UNDERFLOW)
1011 else if (r == DPLL_FINT_INVALID)
1014 /* Compute the scaled DPLL multiplier, based on the divider */
1015 m = scaled_rt_rp * n;
1018 * Since we're counting n up, a m overflow means we
1019 * can bail out completely (since as n increases in
1020 * the next iteration, there's no way that m can
1021 * increase beyond the current m)
1023 if (m > scaled_max_m)
1026 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1029 /* m can't be set low enough for this n - try with a larger n */
1030 if (r == DPLL_MULT_UNDERFLOW)
1033 e = target_rate - new_rate;
1034 pr_debug("clock: n = %d: m = %d: rate error is %d "
1035 "(new_rate = %ld)\n", n, m, e, new_rate);
1038 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
1043 pr_debug("clock: found new least error %d\n", min_e);
1045 /* We found good settings -- bail out now */
1046 if (min_e <= dd->rate_tolerance)
1052 pr_debug("clock: error: target rate or tolerance too low\n");
1056 dd->last_rounded_m = min_e_m;
1057 dd->last_rounded_n = min_e_n;
1058 dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate,
1061 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1062 min_e, min_e_m, min_e_n);
1063 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1064 dd->last_rounded_rate, target_rate);
1066 return dd->last_rounded_rate;
1069 /*-------------------------------------------------------------------------
1070 * Omap2 clock reset and init functions
1071 *-------------------------------------------------------------------------*/
1073 #ifdef CONFIG_OMAP_RESET_CLOCKS
1074 void omap2_clk_disable_unused(struct clk *clk)
1078 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1080 regval32 = _omap2_clk_read_reg(clk->enable_reg, clk);
1081 if ((regval32 & (1 << clk->enable_bit)) == v)
1084 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1085 _omap2_clk_disable(clk);
1089 int omap2_clk_register(struct clk *clk)
1091 omap2_init_clk_clkdm(clk);