2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <asm/div64.h>
37 #include "prm-regbits-24xx.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
42 #define MAX_CLOCK_ENABLE_WAIT 100000
44 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
45 #define DPLL_MIN_MULTIPLIER 1
46 #define DPLL_MIN_DIVIDER 1
48 /* Possible error results from _dpll_test_mult */
49 #define DPLL_MULT_UNDERFLOW (1 << 0)
52 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
53 * The higher the scale factor, the greater the risk of arithmetic overflow,
54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
55 * must be a power of DPLL_SCALE_BASE.
57 #define DPLL_SCALE_FACTOR 64
58 #define DPLL_SCALE_BASE 2
59 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /*-------------------------------------------------------------------------
65 * OMAP2/3 specific clock functions
66 *-------------------------------------------------------------------------*/
69 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
70 * @clk: OMAP clock struct ptr to use
72 * Convert a clockdomain name stored in a struct clk 'clk' into a
73 * clockdomain pointer, and save it into the struct clk. Intended to be
74 * called during clk_register(). No return value.
76 void omap2_init_clk_clkdm(struct clk *clk)
78 struct clockdomain *clkdm;
83 clkdm = clkdm_lookup(clk->clkdm_name);
85 pr_debug("clock: associated clk %s to clkdm %s\n",
86 clk->name, clk->clkdm_name);
89 pr_debug("clock: could not associate clk %s to "
90 "clkdm %s\n", clk->name, clk->clkdm_name);
95 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
96 * @clk: OMAP clock struct ptr to use
98 * Given a pointer to a source-selectable struct clk, read the hardware
99 * register and determine what its parent is currently set to. Update the
100 * clk->parent field with the appropriate clk ptr.
102 void omap2_init_clksel_parent(struct clk *clk)
104 const struct clksel *clks;
105 const struct clksel_rate *clkr;
111 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
112 r >>= __ffs(clk->clksel_mask);
114 for (clks = clk->clksel; clks->parent && !found; clks++) {
115 for (clkr = clks->rates; clkr->div && !found; clkr++) {
116 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
117 if (clk->parent != clks->parent) {
118 pr_debug("clock: inited %s parent "
120 clk->name, clks->parent->name,
122 clk->parent->name : "NULL"));
123 clk->parent = clks->parent;
131 printk(KERN_ERR "clock: init parent: could not find "
132 "regval %0x for clock %s\n", r, clk->name);
137 /* Returns the DPLL rate */
138 u32 omap2_get_dpll_rate(struct clk *clk)
141 u32 dpll_mult, dpll_div, dpll;
142 struct dpll_data *dd;
145 /* REVISIT: What do we return on error? */
149 dpll = __raw_readl(dd->mult_div1_reg);
150 dpll_mult = dpll & dd->mult_mask;
151 dpll_mult >>= __ffs(dd->mult_mask);
152 dpll_div = dpll & dd->div1_mask;
153 dpll_div >>= __ffs(dd->div1_mask);
155 dpll_clk = (long long)clk->parent->rate * dpll_mult;
156 do_div(dpll_clk, dpll_div + 1);
162 * Used for clocks that have the same value as the parent clock,
163 * divided by some factor
165 void omap2_fixed_divisor_recalc(struct clk *clk)
167 WARN_ON(!clk->fixed_div);
169 clk->rate = clk->parent->rate / clk->fixed_div;
173 * omap2_wait_clock_ready - wait for clock to enable
174 * @reg: physical address of clock IDLEST register
175 * @mask: value to mask against to determine if the clock is active
176 * @name: name of the clock (for printk)
178 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
179 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
181 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
187 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
188 * 34xx reverses this, just to keep us on our toes
190 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
192 } else if (cpu_mask & RATE_IN_343X) {
197 while (((__raw_readl(reg) & mask) != ena) &&
198 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
202 if (i < MAX_CLOCK_ENABLE_WAIT)
203 pr_debug("Clock %s stable after %d loops\n", name, i);
205 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
206 name, MAX_CLOCK_ENABLE_WAIT);
209 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
214 * Note: We don't need special code here for INVERT_ENABLE
215 * for the time being since INVERT_ENABLE only applies to clocks enabled by
218 static void omap2_clk_wait_ready(struct clk *clk)
220 void __iomem *reg, *other_reg, *st_reg;
224 * REVISIT: This code is pretty ugly. It would be nice to generalize
225 * it and pull it into struct clk itself somehow.
227 reg = clk->enable_reg;
230 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
231 * it's just a matter of XORing the bits.
233 other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
235 /* Check if both functional and interface clocks
237 bit = 1 << clk->enable_bit;
238 if (!(__raw_readl(other_reg) & bit))
240 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
242 omap2_wait_clock_ready(st_reg, bit, clk->name);
245 static int omap2_dflt_clk_enable(struct clk *clk)
249 if (unlikely(clk->enable_reg == NULL)) {
250 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
252 return 0; /* REVISIT: -EINVAL */
255 regval32 = __raw_readl(clk->enable_reg);
256 if (clk->flags & INVERT_ENABLE)
257 regval32 &= ~(1 << clk->enable_bit);
259 regval32 |= (1 << clk->enable_bit);
260 __raw_writel(regval32, clk->enable_reg);
266 static int omap2_dflt_clk_enable_wait(struct clk *clk)
270 if (unlikely(clk->enable_reg == NULL)) {
271 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
273 return 0; /* REVISIT: -EINVAL */
276 ret = omap2_dflt_clk_enable(clk);
278 omap2_clk_wait_ready(clk);
282 static void omap2_dflt_clk_disable(struct clk *clk)
286 if (clk->enable_reg == NULL) {
288 * 'Independent' here refers to a clock which is not
289 * controlled by its parent.
291 printk(KERN_ERR "clock: clk_disable called on independent "
292 "clock %s which has no enable_reg\n", clk->name);
296 regval32 = __raw_readl(clk->enable_reg);
297 if (clk->flags & INVERT_ENABLE)
298 regval32 |= (1 << clk->enable_bit);
300 regval32 &= ~(1 << clk->enable_bit);
301 __raw_writel(regval32, clk->enable_reg);
305 const struct clkops clkops_omap2_dflt_wait = {
306 .enable = omap2_dflt_clk_enable_wait,
307 .disable = omap2_dflt_clk_disable,
310 const struct clkops clkops_omap2_dflt = {
311 .enable = omap2_dflt_clk_enable,
312 .disable = omap2_dflt_clk_disable,
315 /* Enables clock without considering parent dependencies or use count
316 * REVISIT: Maybe change this to use clk->enable like on omap1?
318 static int _omap2_clk_enable(struct clk *clk)
320 return clk->ops->enable(clk);
323 /* Disables clock without considering parent dependencies or use count */
324 static void _omap2_clk_disable(struct clk *clk)
326 clk->ops->disable(clk);
329 void omap2_clk_disable(struct clk *clk)
331 if (clk->usecount > 0 && !(--clk->usecount)) {
332 _omap2_clk_disable(clk);
333 if (likely((u32)clk->parent))
334 omap2_clk_disable(clk->parent);
336 omap2_clkdm_clk_disable(clk->clkdm, clk);
341 int omap2_clk_enable(struct clk *clk)
345 if (clk->usecount++ == 0) {
346 if (likely((u32)clk->parent))
347 ret = omap2_clk_enable(clk->parent);
349 if (unlikely(ret != 0)) {
355 omap2_clkdm_clk_enable(clk->clkdm, clk);
357 ret = _omap2_clk_enable(clk);
359 if (unlikely(ret != 0)) {
361 omap2_clkdm_clk_disable(clk->clkdm, clk);
364 omap2_clk_disable(clk->parent);
374 * Used for clocks that are part of CLKSEL_xyz governed clocks.
375 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
377 void omap2_clksel_recalc(struct clk *clk)
381 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
383 div = omap2_clksel_get_divisor(clk);
387 if (unlikely(clk->rate == clk->parent->rate / div))
389 clk->rate = clk->parent->rate / div;
391 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
395 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
396 * @clk: OMAP struct clk ptr to inspect
397 * @src_clk: OMAP struct clk ptr of the parent clk to search for
399 * Scan the struct clksel array associated with the clock to find
400 * the element associated with the supplied parent clock address.
401 * Returns a pointer to the struct clksel on success or NULL on error.
403 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
406 const struct clksel *clks;
411 for (clks = clk->clksel; clks->parent; clks++) {
412 if (clks->parent == src_clk)
413 break; /* Found the requested parent */
417 printk(KERN_ERR "clock: Could not find parent clock %s in "
418 "clksel array of clock %s\n", src_clk->name,
427 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
428 * @clk: OMAP struct clk to use
429 * @target_rate: desired clock rate
430 * @new_div: ptr to where we should store the divisor
432 * Finds 'best' divider value in an array based on the source and target
433 * rates. The divider array must be sorted with smallest divider first.
434 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
435 * they are only settable as part of virtual_prcm set.
437 * Returns the rounded clock rate or returns 0xffffffff on error.
439 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
442 unsigned long test_rate;
443 const struct clksel *clks;
444 const struct clksel_rate *clkr;
447 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
448 clk->name, target_rate);
452 clks = omap2_get_clksel_by_parent(clk, clk->parent);
456 for (clkr = clks->rates; clkr->div; clkr++) {
457 if (!(clkr->flags & cpu_mask))
461 if (clkr->div <= last_div)
462 printk(KERN_ERR "clock: clksel_rate table not sorted "
463 "for clock %s", clk->name);
465 last_div = clkr->div;
467 test_rate = clk->parent->rate / clkr->div;
469 if (test_rate <= target_rate)
470 break; /* found it */
474 printk(KERN_ERR "clock: Could not find divisor for target "
475 "rate %ld for clock %s parent %s\n", target_rate,
476 clk->name, clk->parent->name);
480 *new_div = clkr->div;
482 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
483 (clk->parent->rate / clkr->div));
485 return (clk->parent->rate / clkr->div);
489 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
490 * @clk: OMAP struct clk to use
491 * @target_rate: desired clock rate
493 * Compatibility wrapper for OMAP clock framework
494 * Finds best target rate based on the source clock and possible dividers.
495 * rates. The divider array must be sorted with smallest divider first.
496 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
497 * they are only settable as part of virtual_prcm set.
499 * Returns the rounded clock rate or returns 0xffffffff on error.
501 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
505 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
509 /* Given a clock and a rate apply a clock specific rounding function */
510 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
512 if (clk->round_rate != NULL)
513 return clk->round_rate(clk, rate);
515 if (clk->flags & RATE_FIXED)
516 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
517 "on fixed-rate clock %s\n", clk->name);
523 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
524 * @clk: OMAP struct clk to use
525 * @field_val: register field value to find
527 * Given a struct clk of a rate-selectable clksel clock, and a register field
528 * value to search for, find the corresponding clock divisor. The register
529 * field value should be pre-masked and shifted down so the LSB is at bit 0
530 * before calling. Returns 0 on error
532 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
534 const struct clksel *clks;
535 const struct clksel_rate *clkr;
537 clks = omap2_get_clksel_by_parent(clk, clk->parent);
541 for (clkr = clks->rates; clkr->div; clkr++) {
542 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
547 printk(KERN_ERR "clock: Could not find fieldval %d for "
548 "clock %s parent %s\n", field_val, clk->name,
557 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
558 * @clk: OMAP struct clk to use
559 * @div: integer divisor to search for
561 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
562 * find the corresponding register field value. The return register value is
563 * the value before left-shifting. Returns 0xffffffff on error
565 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
567 const struct clksel *clks;
568 const struct clksel_rate *clkr;
570 /* should never happen */
573 clks = omap2_get_clksel_by_parent(clk, clk->parent);
577 for (clkr = clks->rates; clkr->div; clkr++) {
578 if ((clkr->flags & cpu_mask) && (clkr->div == div))
583 printk(KERN_ERR "clock: Could not find divisor %d for "
584 "clock %s parent %s\n", div, clk->name,
593 * omap2_get_clksel - find clksel register addr & field mask for a clk
594 * @clk: struct clk to use
595 * @field_mask: ptr to u32 to store the register field mask
597 * Returns the address of the clksel register upon success or NULL on error.
599 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
601 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
604 *field_mask = clk->clksel_mask;
606 return clk->clksel_reg;
610 * omap2_clksel_get_divisor - get current divider applied to parent clock.
611 * @clk: OMAP struct clk to use.
613 * Returns the integer divisor upon success or 0 on error.
615 u32 omap2_clksel_get_divisor(struct clk *clk)
617 u32 field_mask, field_val;
618 void __iomem *div_addr;
620 div_addr = omap2_get_clksel(clk, &field_mask);
621 if (div_addr == NULL)
624 field_val = __raw_readl(div_addr) & field_mask;
625 field_val >>= __ffs(field_mask);
627 return omap2_clksel_to_divisor(clk, field_val);
630 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
632 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
633 void __iomem *div_addr;
635 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
636 if (validrate != rate)
639 div_addr = omap2_get_clksel(clk, &field_mask);
640 if (div_addr == NULL)
643 field_val = omap2_divisor_to_clksel(clk, new_div);
647 reg_val = __raw_readl(div_addr);
648 reg_val &= ~field_mask;
649 reg_val |= (field_val << __ffs(field_mask));
650 __raw_writel(reg_val, div_addr);
653 clk->rate = clk->parent->rate / new_div;
655 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
656 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
657 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
665 /* Set the clock rate for a clock source */
666 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
670 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
672 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
673 rate table mechanism, driven by mpu_speed */
674 if (clk->flags & CONFIG_PARTICIPANT)
677 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
678 if (clk->set_rate != NULL)
679 ret = clk->set_rate(clk, rate);
685 * Converts encoded control register address into a full address
686 * On error, *src_addr will be returned as 0.
688 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
689 struct clk *src_clk, u32 *field_mask,
690 struct clk *clk, u32 *parent_div)
692 const struct clksel *clks;
693 const struct clksel_rate *clkr;
698 clks = omap2_get_clksel_by_parent(clk, src_clk);
702 for (clkr = clks->rates; clkr->div; clkr++) {
703 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
704 break; /* Found the default rate for this platform */
708 printk(KERN_ERR "clock: Could not find default rate for "
709 "clock %s parent %s\n", clk->name,
710 src_clk->parent->name);
714 /* Should never happen. Add a clksel mask to the struct clk. */
715 WARN_ON(clk->clksel_mask == 0);
717 *field_mask = clk->clksel_mask;
718 *src_addr = clk->clksel_reg;
719 *parent_div = clkr->div;
724 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
726 void __iomem *src_addr;
727 u32 field_val, field_mask, reg_val, parent_div;
729 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
735 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
736 &field_mask, clk, &parent_div);
737 if (src_addr == NULL)
740 if (clk->usecount > 0)
741 _omap2_clk_disable(clk);
743 /* Set new source value (previous dividers if any in effect) */
744 reg_val = __raw_readl(src_addr) & ~field_mask;
745 reg_val |= (field_val << __ffs(field_mask));
746 __raw_writel(reg_val, src_addr);
749 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
750 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
754 if (clk->usecount > 0)
755 _omap2_clk_enable(clk);
757 clk->parent = new_parent;
759 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
760 clk->rate = new_parent->rate;
763 clk->rate /= parent_div;
765 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
766 clk->name, clk->parent->name, clk->rate);
771 /* DPLL rate rounding code */
774 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
775 * @clk: struct clk * of the DPLL
776 * @tolerance: maximum rate error tolerance
778 * Set the maximum DPLL rate error tolerance for the rate rounding
779 * algorithm. The rate tolerance is an attempt to balance DPLL power
780 * saving (the least divider value "n") vs. rate fidelity (the least
781 * difference between the desired DPLL target rate and the rounded
782 * rate out of the algorithm). So, increasing the tolerance is likely
783 * to decrease DPLL power consumption and increase DPLL rate error.
784 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
785 * DPLL; or 0 upon success.
787 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
789 if (!clk || !clk->dpll_data)
792 clk->dpll_data->rate_tolerance = tolerance;
797 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
799 unsigned long long num;
801 num = (unsigned long long)parent_rate * m;
807 * _dpll_test_mult - test a DPLL multiplier value
808 * @m: pointer to the DPLL m (multiplier) value under test
809 * @n: current DPLL n (divider) value under test
810 * @new_rate: pointer to storage for the resulting rounded rate
811 * @target_rate: the desired DPLL rate
812 * @parent_rate: the DPLL's parent clock rate
814 * This code tests a DPLL multiplier value, ensuring that the
815 * resulting rate will not be higher than the target_rate, and that
816 * the multiplier value itself is valid for the DPLL. Initially, the
817 * integer pointed to by the m argument should be prescaled by
818 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
819 * a non-scaled m upon return. This non-scaled m will result in a
820 * new_rate as close as possible to target_rate (but not greater than
821 * target_rate) given the current (parent_rate, n, prescaled m)
822 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
823 * non-scaled m attempted to underflow, which can allow the calling
824 * function to bail out early; or 0 upon success.
826 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
827 unsigned long target_rate,
828 unsigned long parent_rate)
830 int flags = 0, carry = 0;
832 /* Unscale m and round if necessary */
833 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
835 *m = (*m / DPLL_SCALE_FACTOR) + carry;
838 * The new rate must be <= the target rate to avoid programming
839 * a rate that is impossible for the hardware to handle
841 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
842 if (*new_rate > target_rate) {
847 /* Guard against m underflow */
848 if (*m < DPLL_MIN_MULTIPLIER) {
849 *m = DPLL_MIN_MULTIPLIER;
851 flags = DPLL_MULT_UNDERFLOW;
855 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
861 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
862 * @clk: struct clk * for a DPLL
863 * @target_rate: desired DPLL clock rate
865 * Given a DPLL, a desired target rate, and a rate tolerance, round
866 * the target rate to a possible, programmable rate for this DPLL.
867 * Rate tolerance is assumed to be set by the caller before this
868 * function is called. Attempts to select the minimum possible n
869 * within the tolerance to reduce power consumption. Stores the
870 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
871 * will not need to call this (expensive) function again. Returns ~0
872 * if the target rate cannot be rounded, either because the rate is
873 * too low or because the rate tolerance is set too tightly; or the
874 * rounded rate upon success.
876 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
878 int m, n, r, e, scaled_max_m;
879 unsigned long scaled_rt_rp, new_rate;
880 int min_e = -1, min_e_m = -1, min_e_n = -1;
882 if (!clk || !clk->dpll_data)
885 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
886 "%ld\n", clk->name, target_rate);
888 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
889 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
891 clk->dpll_data->last_rounded_rate = 0;
893 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
895 /* Compute the scaled DPLL multiplier, based on the divider */
896 m = scaled_rt_rp * n;
899 * Since we're counting n down, a m overflow means we can
900 * can immediately skip to the next n
902 if (m > scaled_max_m)
905 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
908 e = target_rate - new_rate;
909 pr_debug("clock: n = %d: m = %d: rate error is %d "
910 "(new_rate = %ld)\n", n, m, e, new_rate);
913 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
918 pr_debug("clock: found new least error %d\n", min_e);
922 * Since we're counting n down, a m underflow means we
923 * can bail out completely (since as n decreases in
924 * the next iteration, there's no way that m can
925 * increase beyond the current m)
927 if (r & DPLL_MULT_UNDERFLOW)
932 pr_debug("clock: error: target rate or tolerance too low\n");
936 clk->dpll_data->last_rounded_m = min_e_m;
937 clk->dpll_data->last_rounded_n = min_e_n;
938 clk->dpll_data->last_rounded_rate =
939 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
941 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
942 min_e, min_e_m, min_e_n);
943 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
944 clk->dpll_data->last_rounded_rate, target_rate);
946 return clk->dpll_data->last_rounded_rate;
949 /*-------------------------------------------------------------------------
950 * Omap2 clock reset and init functions
951 *-------------------------------------------------------------------------*/
953 #ifdef CONFIG_OMAP_RESET_CLOCKS
954 void omap2_clk_disable_unused(struct clk *clk)
958 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
960 regval32 = __raw_readl(clk->enable_reg);
961 if ((regval32 & (1 << clk->enable_bit)) == v)
964 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
965 _omap2_clk_disable(clk);