2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <mach/control.h>
33 #include <asm/div64.h>
35 #include <mach/sdrc.h>
39 #include "prm-regbits-24xx.h"
41 #include "cm-regbits-24xx.h"
42 #include "cm-regbits-34xx.h"
44 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
47 #define DPLL_MIN_MULTIPLIER 1
48 #define DPLL_MIN_DIVIDER 1
50 /* Possible error results from _dpll_test_mult */
51 #define DPLL_MULT_UNDERFLOW -1
54 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
55 * The higher the scale factor, the greater the risk of arithmetic overflow,
56 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
57 * must be a power of DPLL_SCALE_BASE.
59 #define DPLL_SCALE_FACTOR 64
60 #define DPLL_SCALE_BASE 2
61 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
62 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
65 #define DPLL_FINT_BAND1_MIN 750000
66 #define DPLL_FINT_BAND1_MAX 2100000
67 #define DPLL_FINT_BAND2_MIN 7500000
68 #define DPLL_FINT_BAND2_MAX 21000000
70 /* _dpll_test_fint() return codes */
71 #define DPLL_FINT_UNDERFLOW -1
72 #define DPLL_FINT_INVALID -2
74 /* Bitmask to isolate the register type of clk.enable_reg */
75 #define PRCM_REGTYPE_MASK 0xf0
76 /* various CM register type options */
77 #define CM_FCLKEN_REGTYPE 0x00
78 #define CM_ICLKEN_REGTYPE 0x10
79 #define CM_IDLEST_REGTYPE 0x20
83 /*-------------------------------------------------------------------------
84 * OMAP2/3 specific clock functions
85 *-------------------------------------------------------------------------*/
88 * _omap2_clk_read_reg - read a clock register
91 * Given a struct clk *, returns the value of the clock's register.
93 static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
95 if (clk->prcm_mod & CLK_REG_IN_SCM)
96 return omap_ctrl_readl(reg_offset);
97 else if (clk->prcm_mod & CLK_REG_IN_PRM)
98 return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
101 return cm_read_mod_reg(clk->prcm_mod, reg_offset);
105 * _omap2_clk_write_reg - write a clock's register
106 * @v: value to write to the clock's enable_reg
109 * Given a register value @v and struct clk * @clk, writes the value of @v to
110 * the clock's enable register. No return value.
112 static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
114 if (clk->prcm_mod & CLK_REG_IN_SCM)
115 omap_ctrl_writel(v, reg_offset);
116 else if (clk->prcm_mod & CLK_REG_IN_PRM)
117 prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
120 cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
124 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
125 * @clk: DPLL struct clk to test
126 * @n: divider value (N) to test
128 * Tests whether a particular divider @n will result in a valid DPLL
129 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
130 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
131 * (assuming that it is counting N upwards), or -2 if the enclosing loop
132 * should skip to the next iteration (again assuming N is increasing).
134 static int _dpll_test_fint(struct clk *clk, u8 n)
136 struct dpll_data *dd;
142 /* DPLL divider must result in a valid jitter correction val */
143 fint = clk->parent->rate / (n + 1);
144 if (fint < DPLL_FINT_BAND1_MIN) {
146 pr_debug("rejecting n=%d due to Fint failure, "
147 "lowering max_divider\n", n);
149 ret = DPLL_FINT_UNDERFLOW;
151 } else if (fint > DPLL_FINT_BAND1_MAX &&
152 fint < DPLL_FINT_BAND2_MIN) {
154 pr_debug("rejecting n=%d due to Fint failure\n", n);
155 ret = DPLL_FINT_INVALID;
157 } else if (fint > DPLL_FINT_BAND2_MAX) {
159 pr_debug("rejecting n=%d due to Fint failure, "
160 "boosting min_divider\n", n);
162 ret = DPLL_FINT_INVALID;
170 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
171 * @clk: OMAP clock struct ptr to use
173 * Convert a clockdomain name stored in a struct clk 'clk' into a
174 * clockdomain pointer, and save it into the struct clk. Intended to be
175 * called during clk_register(). No return value.
177 void omap2_init_clk_clkdm(struct clk *clk)
179 struct clockdomain *clkdm;
181 if (!clk->clkdm.name) {
182 pr_err("clock: %s: missing clockdomain", clk->name);
186 clkdm = clkdm_lookup(clk->clkdm.name);
188 pr_debug("clock: associated clk %s to clkdm %s\n",
189 clk->name, clk->clkdm.name);
190 clk->clkdm.ptr = clkdm;
192 pr_err("clock: %s: could not associate to clkdm %s\n",
193 clk->name, clk->clkdm.name);
198 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
199 * @clk: OMAP clock struct ptr to use
201 * Given a pointer to a source-selectable struct clk, read the hardware
202 * register and determine what its parent is currently set to. Update the
203 * clk->parent field with the appropriate clk ptr.
205 void omap2_init_clksel_parent(struct clk *clk)
207 const struct clksel *clks;
208 const struct clksel_rate *clkr;
214 r = _omap2_clk_read_reg(clk->clksel_reg, clk);
215 r &= clk->clksel_mask;
216 r >>= __ffs(clk->clksel_mask);
218 for (clks = clk->clksel; clks->parent && !found; clks++) {
219 for (clkr = clks->rates; clkr->div && !found; clkr++) {
220 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
221 if (clk->parent != clks->parent) {
222 pr_debug("clock: inited %s parent "
224 clk->name, clks->parent->name,
226 clk->parent->name : "NULL"));
228 omap_clk_del_child(clk->parent,
230 clk->parent = clks->parent;
231 omap_clk_add_child(clk->parent, clk);
239 printk(KERN_ERR "clock: init parent: could not find "
240 "regval %0x for clock %s\n", r, clk->name);
246 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
247 * @clk: struct clk * of a DPLL
248 * @parent_rate: rate of the parent of the DPLL clock
250 * DPLLs can be locked or bypassed - basically, enabled or disabled.
251 * When locked, the DPLL output depends on the M and N values. When
252 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
253 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
254 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
255 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
256 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
257 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
258 * if the clock @clk is not a DPLL.
260 u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate)
263 u32 dpll_mult, dpll_div, v;
264 struct dpll_data *dd;
270 /* Return bypass rate if DPLL is bypassed */
271 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
272 v &= dd->enable_mask;
273 v >>= __ffs(dd->enable_mask);
275 if (cpu_is_omap24xx()) {
277 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
278 v == OMAP2XXX_EN_DPLL_FRBYPASS)
281 } else if (cpu_is_omap34xx()) {
283 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
284 v == OMAP3XXX_EN_DPLL_FRBYPASS)
285 return dd->bypass_clk->rate;
289 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
290 dpll_mult = v & dd->mult_mask;
291 dpll_mult >>= __ffs(dd->mult_mask);
292 dpll_div = v & dd->div1_mask;
293 dpll_div >>= __ffs(dd->div1_mask);
295 dpll_clk = (long long)parent_rate * dpll_mult;
296 do_div(dpll_clk, dpll_div + 1);
302 * Used for clocks that have the same value as the parent clock,
303 * divided by some factor
305 void omap2_fixed_divisor_recalc(struct clk *clk, unsigned long parent_rate,
310 WARN_ON(!clk->fixed_div); /* XXX move this to init */
312 rate = parent_rate / clk->fixed_div;
314 if (rate_storage == CURRENT_RATE)
316 else if (rate_storage == TEMP_RATE)
317 clk->temp_rate = rate;
321 * omap2_wait_clock_ready - wait for clock to enable
322 * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
323 * @reg_index: offset of CM register address from prcm_mod
324 * @mask: value to mask against to determine if the clock is active
325 * @name: name of the clock (for printk)
327 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
328 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
330 int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
336 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
337 * 34xx reverses this, just to keep us on our toes
339 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
341 else if (cpu_mask & RATE_IN_343X)
345 while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
346 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
350 if (i < MAX_CLOCK_ENABLE_WAIT)
351 pr_debug("Clock %s stable after %d loops\n", name, i);
353 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
354 name, MAX_CLOCK_ENABLE_WAIT);
356 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
361 * omap2_clk_wait_ready - wait for a OMAP module to come out of target idle
362 * @clk: struct clk * recently enabled to indicate the module to test
364 * Wait for an OMAP module with a target idle state bit to come out of
365 * idle once both its interface clock and primary functional clock are
366 * both enabled. Any register read or write to the device before it
367 * returns from idle will cause an abort. Not all modules have target
368 * idle state bits (for example, DSS and CAM on OMAP24xx); so we don't
369 * wait for those. No return value.
371 * We don't need special code here for INVERT_ENABLE for the time
372 * being since INVERT_ENABLE only applies to clocks enabled by
375 * REVISIT: This function is misnamed: it should be something like
376 * "omap2_module_wait_ready", and in the long-term, it does not belong
377 * in the clock framework. It also shouldn't be doing register
378 * arithmetic to determine the companion clock.
380 static void omap2_clk_wait_ready(struct clk *clk)
382 u16 other_reg, idlest_reg;
385 if (!(clk->flags & WAIT_READY))
388 /* If we are enabling an iclk, also test the fclk; and vice versa */
389 other_bit = 1 << clk->enable_bit;
390 other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK;
392 if (clk->enable_reg & CM_ICLKEN_REGTYPE)
393 other_reg |= CM_FCLKEN_REGTYPE;
395 other_reg |= CM_ICLKEN_REGTYPE;
397 /* Ensure functional and interface clocks are running. */
398 if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit))
401 idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
402 idlest_reg |= CM_IDLEST_REGTYPE;
404 omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, 1 << clk->idlest_bit,
408 /* Enables clock without considering parent dependencies or use count
409 * REVISIT: Maybe change this to use clk->enable like on omap1?
411 static int _omap2_clk_enable(struct clk *clk)
415 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
419 return clk->enable(clk);
421 v = _omap2_clk_read_reg(clk->enable_reg, clk);
422 if (clk->flags & INVERT_ENABLE)
423 v &= ~(1 << clk->enable_bit);
425 v |= (1 << clk->enable_bit);
426 _omap2_clk_write_reg(v, clk->enable_reg, clk);
429 omap2_clk_wait_ready(clk);
434 /* Disables clock without considering parent dependencies or use count */
435 static void _omap2_clk_disable(struct clk *clk)
439 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
447 v = _omap2_clk_read_reg(clk->enable_reg, clk);
448 if (clk->flags & INVERT_ENABLE)
449 v |= (1 << clk->enable_bit);
451 v &= ~(1 << clk->enable_bit);
452 _omap2_clk_write_reg(v, clk->enable_reg, clk);
456 void omap2_clk_disable(struct clk *clk)
458 if (clk->usecount > 0 && !(--clk->usecount)) {
459 _omap2_clk_disable(clk);
461 omap2_clk_disable(clk->parent);
463 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
468 int omap2_clk_enable(struct clk *clk)
472 if (clk->usecount++ == 0) {
474 ret = omap2_clk_enable(clk->parent);
482 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
484 ret = _omap2_clk_enable(clk);
488 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
491 omap2_clk_disable(clk->parent);
501 * Used for clocks that are part of CLKSEL_xyz governed clocks.
502 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
504 void omap2_clksel_recalc(struct clk *clk, unsigned long parent_rate,
510 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
512 div = omap2_clksel_get_divisor(clk);
516 rate = parent_rate / div;
518 if (rate_storage == CURRENT_RATE)
520 else if (rate_storage == TEMP_RATE)
521 clk->temp_rate = rate;
523 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
527 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
528 * @clk: OMAP struct clk ptr to inspect
529 * @src_clk: OMAP struct clk ptr of the parent clk to search for
531 * Scan the struct clksel array associated with the clock to find
532 * the element associated with the supplied parent clock address.
533 * Returns a pointer to the struct clksel on success or NULL on error.
535 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
538 const struct clksel *clks;
543 for (clks = clk->clksel; clks->parent; clks++) {
544 if (clks->parent == src_clk)
545 break; /* Found the requested parent */
549 printk(KERN_ERR "clock: Could not find parent clock %s in "
550 "clksel array of clock %s\n", src_clk->name,
559 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
560 * @clk: OMAP struct clk to use
561 * @target_rate: desired clock rate
562 * @new_div: ptr to where we should store the divisor
564 * Finds 'best' divider value in an array based on the source and target
565 * rates. The divider array must be sorted with smallest divider first.
566 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
567 * they are only settable as part of virtual_prcm set.
569 * Returns the rounded clock rate or returns 0xffffffff on error.
571 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
574 unsigned long test_rate;
575 const struct clksel *clks;
576 const struct clksel_rate *clkr;
579 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
580 clk->name, target_rate);
584 clks = omap2_get_clksel_by_parent(clk, clk->parent);
588 for (clkr = clks->rates; clkr->div; clkr++) {
589 if (!(clkr->flags & cpu_mask))
593 if (clkr->div <= last_div)
594 printk(KERN_ERR "clock: clksel_rate table not sorted "
595 "for clock %s", clk->name);
597 last_div = clkr->div;
599 test_rate = clk->parent->rate / clkr->div;
601 if (test_rate <= target_rate)
602 break; /* found it */
606 printk(KERN_ERR "clock: Could not find divisor for target "
607 "rate %ld for clock %s parent %s\n", target_rate,
608 clk->name, clk->parent->name);
612 *new_div = clkr->div;
614 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
615 (clk->parent->rate / clkr->div));
617 return (clk->parent->rate / clkr->div);
621 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
622 * @clk: OMAP struct clk to use
623 * @target_rate: desired clock rate
625 * Compatibility wrapper for OMAP clock framework
626 * Finds best target rate based on the source clock and possible dividers.
627 * rates. The divider array must be sorted with smallest divider first.
628 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
629 * they are only settable as part of virtual_prcm set.
631 * Returns the rounded clock rate or returns 0xffffffff on error.
633 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
637 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
641 /* Given a clock and a rate apply a clock specific rounding function */
642 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
644 if (clk->round_rate != NULL)
645 return clk->round_rate(clk, rate);
647 if (clk->flags & RATE_FIXED)
648 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
649 "on fixed-rate clock %s\n", clk->name);
655 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
656 * @clk: OMAP struct clk to use
657 * @field_val: register field value to find
659 * Given a struct clk of a rate-selectable clksel clock, and a register field
660 * value to search for, find the corresponding clock divisor. The register
661 * field value should be pre-masked and shifted down so the LSB is at bit 0
662 * before calling. Returns 0 on error
664 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
666 const struct clksel *clks;
667 const struct clksel_rate *clkr;
669 clks = omap2_get_clksel_by_parent(clk, clk->parent);
673 for (clkr = clks->rates; clkr->div; clkr++) {
674 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
679 printk(KERN_ERR "clock: Could not find fieldval %d for "
680 "clock %s parent %s\n", field_val, clk->name,
689 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
690 * @clk: OMAP struct clk to use
691 * @div: integer divisor to search for
693 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
694 * find the corresponding register field value. The return register value is
695 * the value before left-shifting. Returns 0xffffffff on error
697 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
699 const struct clksel *clks;
700 const struct clksel_rate *clkr;
702 /* should never happen */
705 clks = omap2_get_clksel_by_parent(clk, clk->parent);
709 for (clkr = clks->rates; clkr->div; clkr++) {
710 if ((clkr->flags & cpu_mask) && (clkr->div == div))
715 printk(KERN_ERR "clock: Could not find divisor %d for "
716 "clock %s parent %s\n", div, clk->name,
725 * omap2_clksel_get_divisor - get current divider applied to parent clock.
726 * @clk: OMAP struct clk to use.
728 * Returns the integer divisor upon success or 0 on error.
730 u32 omap2_clksel_get_divisor(struct clk *clk)
734 if (!clk->clksel_mask)
737 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
738 v &= clk->clksel_mask;
739 v >>= __ffs(clk->clksel_mask);
741 return omap2_clksel_to_divisor(clk, v);
744 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
746 u32 v, field_val, validrate, new_div = 0;
748 if (!clk->clksel_mask)
751 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
752 if (validrate != rate)
755 field_val = omap2_divisor_to_clksel(clk, new_div);
759 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
760 v &= ~clk->clksel_mask;
761 v |= field_val << __ffs(clk->clksel_mask);
762 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
766 clk->rate = clk->parent->rate / new_div;
768 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
769 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
770 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
778 /* Set the clock rate for a clock source */
779 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
783 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
785 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
786 rate table mechanism, driven by mpu_speed */
787 if (clk->flags & CONFIG_PARTICIPANT)
790 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
791 if (clk->set_rate != NULL)
792 ret = clk->set_rate(clk, rate);
798 * Converts encoded control register address into a full address
799 * On error, the return value (parent_div) will be 0.
801 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
804 const struct clksel *clks;
805 const struct clksel_rate *clkr;
807 clks = omap2_get_clksel_by_parent(clk, src_clk);
811 for (clkr = clks->rates; clkr->div; clkr++) {
812 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
813 break; /* Found the default rate for this platform */
817 printk(KERN_ERR "clock: Could not find default rate for "
818 "clock %s parent %s\n", clk->name,
819 src_clk->parent->name);
823 /* Should never happen. Add a clksel mask to the struct clk. */
824 WARN_ON(clk->clksel_mask == 0);
826 *field_val = clkr->val;
831 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
833 u32 field_val, v, parent_div;
835 if (clk->flags & CONFIG_PARTICIPANT)
841 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
845 if (clk->usecount > 0)
846 _omap2_clk_disable(clk);
848 /* Set new source value (previous dividers if any in effect) */
849 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
850 v &= ~clk->clksel_mask;
851 v |= field_val << __ffs(clk->clksel_mask);
852 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
855 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
856 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
857 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
861 if (clk->usecount > 0)
862 _omap2_clk_enable(clk);
864 clk->parent = new_parent;
866 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
867 clk->rate = new_parent->rate;
870 clk->rate /= parent_div;
872 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
873 clk->name, clk->parent->name, clk->rate);
878 struct clk *omap2_clk_get_parent(struct clk *clk)
883 /* DPLL rate rounding code */
886 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
887 * @clk: struct clk * of the DPLL
888 * @tolerance: maximum rate error tolerance
890 * Set the maximum DPLL rate error tolerance for the rate rounding
891 * algorithm. The rate tolerance is an attempt to balance DPLL power
892 * saving (the least divider value "n") vs. rate fidelity (the least
893 * difference between the desired DPLL target rate and the rounded
894 * rate out of the algorithm). So, increasing the tolerance is likely
895 * to decrease DPLL power consumption and increase DPLL rate error.
896 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
897 * DPLL; or 0 upon success.
899 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
901 if (!clk || !clk->dpll_data)
904 clk->dpll_data->rate_tolerance = tolerance;
909 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
910 unsigned int m, unsigned int n)
912 unsigned long long num;
914 num = (unsigned long long)parent_rate * m;
920 * _dpll_test_mult - test a DPLL multiplier value
921 * @m: pointer to the DPLL m (multiplier) value under test
922 * @n: current DPLL n (divider) value under test
923 * @new_rate: pointer to storage for the resulting rounded rate
924 * @target_rate: the desired DPLL rate
925 * @parent_rate: the DPLL's parent clock rate
927 * This code tests a DPLL multiplier value, ensuring that the
928 * resulting rate will not be higher than the target_rate, and that
929 * the multiplier value itself is valid for the DPLL. Initially, the
930 * integer pointed to by the m argument should be prescaled by
931 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
932 * a non-scaled m upon return. This non-scaled m will result in a
933 * new_rate as close as possible to target_rate (but not greater than
934 * target_rate) given the current (parent_rate, n, prescaled m)
935 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
936 * non-scaled m attempted to underflow, which can allow the calling
937 * function to bail out early; or 0 upon success.
939 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
940 unsigned long target_rate,
941 unsigned long parent_rate)
943 int r = 0, carry = 0;
945 /* Unscale m and round if necessary */
946 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
948 *m = (*m / DPLL_SCALE_FACTOR) + carry;
951 * The new rate must be <= the target rate to avoid programming
952 * a rate that is impossible for the hardware to handle
954 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
955 if (*new_rate > target_rate) {
960 /* Guard against m underflow */
961 if (*m < DPLL_MIN_MULTIPLIER) {
962 *m = DPLL_MIN_MULTIPLIER;
964 r = DPLL_MULT_UNDERFLOW;
968 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
974 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
975 * @clk: struct clk * for a DPLL
976 * @target_rate: desired DPLL clock rate
978 * Given a DPLL, a desired target rate, and a rate tolerance, round
979 * the target rate to a possible, programmable rate for this DPLL.
980 * Rate tolerance is assumed to be set by the caller before this
981 * function is called. Attempts to select the minimum possible n
982 * within the tolerance to reduce power consumption. Stores the
983 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
984 * will not need to call this (expensive) function again. Returns ~0
985 * if the target rate cannot be rounded, either because the rate is
986 * too low or because the rate tolerance is set too tightly; or the
987 * rounded rate upon success.
989 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
991 int m, n, r, e, scaled_max_m;
992 unsigned long scaled_rt_rp, new_rate;
993 int min_e = -1, min_e_m = -1, min_e_n = -1;
994 struct dpll_data *dd;
996 if (!clk || !clk->dpll_data)
1001 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
1002 "%ld\n", clk->name, target_rate);
1004 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
1005 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
1007 dd->last_rounded_rate = 0;
1009 for (n = dd->min_divider; n <= dd->max_divider; n++) {
1011 /* Is the (input clk, divider) pair valid for the DPLL? */
1012 r = _dpll_test_fint(clk, n);
1013 if (r == DPLL_FINT_UNDERFLOW)
1015 else if (r == DPLL_FINT_INVALID)
1018 /* Compute the scaled DPLL multiplier, based on the divider */
1019 m = scaled_rt_rp * n;
1022 * Since we're counting n up, a m overflow means we
1023 * can bail out completely (since as n increases in
1024 * the next iteration, there's no way that m can
1025 * increase beyond the current m)
1027 if (m > scaled_max_m)
1030 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1033 /* m can't be set low enough for this n - try with a larger n */
1034 if (r == DPLL_MULT_UNDERFLOW)
1037 e = target_rate - new_rate;
1038 pr_debug("clock: n = %d: m = %d: rate error is %d "
1039 "(new_rate = %ld)\n", n, m, e, new_rate);
1042 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
1047 pr_debug("clock: found new least error %d\n", min_e);
1049 /* We found good settings -- bail out now */
1050 if (min_e <= dd->rate_tolerance)
1056 pr_debug("clock: error: target rate or tolerance too low\n");
1060 dd->last_rounded_m = min_e_m;
1061 dd->last_rounded_n = min_e_n;
1062 dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate,
1065 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1066 min_e, min_e_m, min_e_n);
1067 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1068 dd->last_rounded_rate, target_rate);
1070 return dd->last_rounded_rate;
1073 /*-------------------------------------------------------------------------
1074 * Omap2 clock reset and init functions
1075 *-------------------------------------------------------------------------*/
1077 #ifdef CONFIG_OMAP_RESET_CLOCKS
1078 void omap2_clk_disable_unused(struct clk *clk)
1082 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1084 regval32 = _omap2_clk_read_reg(clk->enable_reg, clk);
1085 if ((regval32 & (1 << clk->enable_bit)) == v)
1088 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1089 _omap2_clk_disable(clk);