2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <mach/control.h>
33 #include <asm/div64.h>
35 #include <mach/sdrc.h>
39 #include "prm-regbits-24xx.h"
41 #include "cm-regbits-24xx.h"
42 #include "cm-regbits-34xx.h"
44 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
47 #define DPLL_MIN_MULTIPLIER 1
48 #define DPLL_MIN_DIVIDER 1
50 /* Possible error results from _dpll_test_mult */
51 #define DPLL_MULT_UNDERFLOW -1
54 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
55 * The higher the scale factor, the greater the risk of arithmetic overflow,
56 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
57 * must be a power of DPLL_SCALE_BASE.
59 #define DPLL_SCALE_FACTOR 64
60 #define DPLL_SCALE_BASE 2
61 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
62 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
65 #define DPLL_FINT_BAND1_MIN 750000
66 #define DPLL_FINT_BAND1_MAX 2100000
67 #define DPLL_FINT_BAND2_MIN 7500000
68 #define DPLL_FINT_BAND2_MAX 21000000
70 /* _dpll_test_fint() return codes */
71 #define DPLL_FINT_UNDERFLOW -1
72 #define DPLL_FINT_INVALID -2
74 /* Some OMAP2xxx CM_CLKSEL_PLL.ST_CORE_CLK bits - for omap2_get_dpll_rate() */
75 #define ST_CORE_CLK_REF 0x1
76 #define ST_CORE_CLK_32K 0x3
78 /* Bitmask to isolate the register type of clk.enable_reg */
79 #define PRCM_REGTYPE_MASK 0xf0
80 /* various CM register type options */
81 #define CM_FCLKEN_REGTYPE 0x00
82 #define CM_ICLKEN_REGTYPE 0x10
83 #define CM_IDLEST_REGTYPE 0x20
87 /*-------------------------------------------------------------------------
88 * OMAP2/3 specific clock functions
89 *-------------------------------------------------------------------------*/
92 * _omap2_clk_read_reg - read a clock register
95 * Given a struct clk *, returns the value of the clock's register.
97 static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
99 if (clk->prcm_mod & CLK_REG_IN_SCM)
100 return omap_ctrl_readl(reg_offset);
101 else if (clk->prcm_mod & CLK_REG_IN_PRM)
102 return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
105 return cm_read_mod_reg(clk->prcm_mod, reg_offset);
109 * _omap2_clk_write_reg - write a clock's register
110 * @v: value to write to the clock's enable_reg
113 * Given a register value @v and struct clk * @clk, writes the value of @v to
114 * the clock's enable register. No return value.
116 static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
118 if (clk->prcm_mod & CLK_REG_IN_SCM)
119 omap_ctrl_writel(v, reg_offset);
120 else if (clk->prcm_mod & CLK_REG_IN_PRM)
121 prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
124 cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
128 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
129 * @clk: DPLL struct clk to test
130 * @n: divider value (N) to test
132 * Tests whether a particular divider @n will result in a valid DPLL
133 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
134 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
135 * (assuming that it is counting N upwards), or -2 if the enclosing loop
136 * should skip to the next iteration (again assuming N is increasing).
138 static int _dpll_test_fint(struct clk *clk, u8 n)
140 struct dpll_data *dd;
146 /* DPLL divider must result in a valid jitter correction val */
147 fint = clk->parent->rate / (n + 1);
148 if (fint < DPLL_FINT_BAND1_MIN) {
150 pr_debug("rejecting n=%d due to Fint failure, "
151 "lowering max_divider\n", n);
153 ret = DPLL_FINT_UNDERFLOW;
155 } else if (fint > DPLL_FINT_BAND1_MAX &&
156 fint < DPLL_FINT_BAND2_MIN) {
158 pr_debug("rejecting n=%d due to Fint failure\n", n);
159 ret = DPLL_FINT_INVALID;
161 } else if (fint > DPLL_FINT_BAND2_MAX) {
163 pr_debug("rejecting n=%d due to Fint failure, "
164 "boosting min_divider\n", n);
166 ret = DPLL_FINT_INVALID;
174 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
175 * @clk: OMAP clock struct ptr to use
177 * Convert a clockdomain name stored in a struct clk 'clk' into a
178 * clockdomain pointer, and save it into the struct clk. Intended to be
179 * called during clk_register(). No return value.
181 void omap2_init_clk_clkdm(struct clk *clk)
183 struct clockdomain *clkdm;
185 if (!clk->clkdm.name) {
186 pr_err("clock: %s: missing clockdomain", clk->name);
190 clkdm = clkdm_lookup(clk->clkdm.name);
192 pr_debug("clock: associated clk %s to clkdm %s\n",
193 clk->name, clk->clkdm.name);
194 clk->clkdm.ptr = clkdm;
196 pr_err("clock: %s: could not associate to clkdm %s\n",
197 clk->name, clk->clkdm.name);
202 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
203 * @clk: OMAP clock struct ptr to use
205 * Given a pointer to a source-selectable struct clk, read the hardware
206 * register and determine what its parent is currently set to. Update the
207 * clk->parent field with the appropriate clk ptr.
209 void omap2_init_clksel_parent(struct clk *clk)
211 const struct clksel *clks;
212 const struct clksel_rate *clkr;
218 r = _omap2_clk_read_reg(clk->clksel_reg, clk);
219 r &= clk->clksel_mask;
220 r >>= __ffs(clk->clksel_mask);
222 for (clks = clk->clksel; clks->parent && !found; clks++) {
223 for (clkr = clks->rates; clkr->div && !found; clkr++) {
224 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
225 if (clk->parent != clks->parent) {
226 pr_debug("clock: inited %s parent "
228 clk->name, clks->parent->name,
230 clk->parent->name : "NULL"));
231 clk->parent = clks->parent;
239 printk(KERN_ERR "clock: init parent: could not find "
240 "regval %0x for clock %s\n", r, clk->name);
246 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
247 * @clk: struct clk * of a DPLL
249 * DPLLs can be locked or bypassed - basically, enabled or disabled.
250 * When locked, the DPLL output depends on the M and N values. When
251 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
252 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
253 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
254 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
255 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
256 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
257 * if the clock @clk is not a DPLL.
259 u32 omap2_get_dpll_rate(struct clk *clk)
262 u32 dpll_mult, dpll_div, v;
263 struct dpll_data *dd;
269 /* Return bypass rate if DPLL is bypassed */
270 v = cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg);
271 v &= dd->idlest_mask;
272 v >>= __ffs(dd->idlest_mask);
273 if (cpu_is_omap24xx()) {
275 if (v == ST_CORE_CLK_REF)
276 return clk->parent->rate; /* sys_clk */
277 else if (v == ST_CORE_CLK_32K)
280 } else if (cpu_is_omap34xx()) {
283 return dd->bypass_clk->rate;
287 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
288 dpll_mult = v & dd->mult_mask;
289 dpll_mult >>= __ffs(dd->mult_mask);
290 dpll_div = v & dd->div1_mask;
291 dpll_div >>= __ffs(dd->div1_mask);
293 dpll_clk = (long long)clk->parent->rate * dpll_mult;
294 do_div(dpll_clk, dpll_div + 1);
300 * Used for clocks that have the same value as the parent clock,
301 * divided by some factor
303 void omap2_fixed_divisor_recalc(struct clk *clk)
305 WARN_ON(!clk->fixed_div);
307 clk->rate = clk->parent->rate / clk->fixed_div;
309 if (clk->flags & RATE_PROPAGATES)
314 * omap2_wait_clock_ready - wait for clock to enable
315 * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
316 * @reg_index: offset of CM register address from prcm_mod
317 * @mask: value to mask against to determine if the clock is active
318 * @name: name of the clock (for printk)
320 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
321 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
323 int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
329 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
330 * 34xx reverses this, just to keep us on our toes
332 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
334 else if (cpu_mask & RATE_IN_343X)
338 while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
339 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
343 if (i < MAX_CLOCK_ENABLE_WAIT)
344 pr_debug("Clock %s stable after %d loops\n", name, i);
346 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
347 name, MAX_CLOCK_ENABLE_WAIT);
349 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
354 * omap2_clk_wait_ready - wait for a OMAP module to come out of target idle
355 * @clk: struct clk * recently enabled to indicate the module to test
357 * Wait for an OMAP module with a target idle state bit to come out of
358 * idle once both its interface clock and primary functional clock are
359 * both enabled. Any register read or write to the device before it
360 * returns from idle will cause an abort. Not all modules have target
361 * idle state bits (for example, DSS and CAM on OMAP24xx); so we don't
362 * wait for those. No return value.
364 * We don't need special code here for INVERT_ENABLE for the time
365 * being since INVERT_ENABLE only applies to clocks enabled by
368 * REVISIT: This function is misnamed: it should be something like
369 * "omap2_module_wait_ready", and in the long-term, it does not belong
370 * in the clock framework. It also shouldn't be doing register
371 * arithmetic to determine the companion clock.
373 static void omap2_clk_wait_ready(struct clk *clk)
375 u16 other_reg, idlest_reg;
378 if (!(clk->flags & WAIT_READY))
381 /* If we are enabling an iclk, also test the fclk; and vice versa */
382 other_bit = 1 << clk->enable_bit;
383 other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK;
385 if (clk->enable_reg & CM_ICLKEN_REGTYPE)
386 other_reg |= CM_FCLKEN_REGTYPE;
388 other_reg |= CM_ICLKEN_REGTYPE;
390 /* Ensure functional and interface clocks are running. */
391 if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit))
394 idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
395 idlest_reg |= CM_IDLEST_REGTYPE;
397 omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, 1 << clk->idlest_bit,
401 /* Enables clock without considering parent dependencies or use count
402 * REVISIT: Maybe change this to use clk->enable like on omap1?
404 static int _omap2_clk_enable(struct clk *clk)
408 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
412 return clk->enable(clk);
414 v = _omap2_clk_read_reg(clk->enable_reg, clk);
415 if (clk->flags & INVERT_ENABLE)
416 v &= ~(1 << clk->enable_bit);
418 v |= (1 << clk->enable_bit);
419 _omap2_clk_write_reg(v, clk->enable_reg, clk);
422 omap2_clk_wait_ready(clk);
427 /* Disables clock without considering parent dependencies or use count */
428 static void _omap2_clk_disable(struct clk *clk)
432 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
440 v = _omap2_clk_read_reg(clk->enable_reg, clk);
441 if (clk->flags & INVERT_ENABLE)
442 v |= (1 << clk->enable_bit);
444 v &= ~(1 << clk->enable_bit);
445 _omap2_clk_write_reg(v, clk->enable_reg, clk);
449 void omap2_clk_disable(struct clk *clk)
451 if (clk->usecount > 0 && !(--clk->usecount)) {
452 _omap2_clk_disable(clk);
454 omap2_clk_disable(clk->parent);
456 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
461 int omap2_clk_enable(struct clk *clk)
465 if (clk->usecount++ == 0) {
467 ret = omap2_clk_enable(clk->parent);
475 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
477 ret = _omap2_clk_enable(clk);
481 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
484 omap2_clk_disable(clk->parent);
494 * Used for clocks that are part of CLKSEL_xyz governed clocks.
495 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
497 void omap2_clksel_recalc(struct clk *clk)
501 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
503 div = omap2_clksel_get_divisor(clk);
507 if (clk->rate == (clk->parent->rate / div))
509 clk->rate = clk->parent->rate / div;
511 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
513 if (clk->flags & RATE_PROPAGATES)
518 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
519 * @clk: OMAP struct clk ptr to inspect
520 * @src_clk: OMAP struct clk ptr of the parent clk to search for
522 * Scan the struct clksel array associated with the clock to find
523 * the element associated with the supplied parent clock address.
524 * Returns a pointer to the struct clksel on success or NULL on error.
526 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
529 const struct clksel *clks;
534 for (clks = clk->clksel; clks->parent; clks++) {
535 if (clks->parent == src_clk)
536 break; /* Found the requested parent */
540 printk(KERN_ERR "clock: Could not find parent clock %s in "
541 "clksel array of clock %s\n", src_clk->name,
550 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
551 * @clk: OMAP struct clk to use
552 * @target_rate: desired clock rate
553 * @new_div: ptr to where we should store the divisor
555 * Finds 'best' divider value in an array based on the source and target
556 * rates. The divider array must be sorted with smallest divider first.
557 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
558 * they are only settable as part of virtual_prcm set.
560 * Returns the rounded clock rate or returns 0xffffffff on error.
562 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
565 unsigned long test_rate;
566 const struct clksel *clks;
567 const struct clksel_rate *clkr;
570 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
571 clk->name, target_rate);
575 clks = omap2_get_clksel_by_parent(clk, clk->parent);
579 for (clkr = clks->rates; clkr->div; clkr++) {
580 if (!(clkr->flags & cpu_mask))
584 if (clkr->div <= last_div)
585 printk(KERN_ERR "clock: clksel_rate table not sorted "
586 "for clock %s", clk->name);
588 last_div = clkr->div;
590 test_rate = clk->parent->rate / clkr->div;
592 if (test_rate <= target_rate)
593 break; /* found it */
597 printk(KERN_ERR "clock: Could not find divisor for target "
598 "rate %ld for clock %s parent %s\n", target_rate,
599 clk->name, clk->parent->name);
603 *new_div = clkr->div;
605 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
606 (clk->parent->rate / clkr->div));
608 return (clk->parent->rate / clkr->div);
612 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
613 * @clk: OMAP struct clk to use
614 * @target_rate: desired clock rate
616 * Compatibility wrapper for OMAP clock framework
617 * Finds best target rate based on the source clock and possible dividers.
618 * rates. The divider array must be sorted with smallest divider first.
619 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
620 * they are only settable as part of virtual_prcm set.
622 * Returns the rounded clock rate or returns 0xffffffff on error.
624 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
628 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
632 /* Given a clock and a rate apply a clock specific rounding function */
633 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
635 if (clk->round_rate != NULL)
636 return clk->round_rate(clk, rate);
638 if (clk->flags & RATE_FIXED)
639 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
640 "on fixed-rate clock %s\n", clk->name);
646 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
647 * @clk: OMAP struct clk to use
648 * @field_val: register field value to find
650 * Given a struct clk of a rate-selectable clksel clock, and a register field
651 * value to search for, find the corresponding clock divisor. The register
652 * field value should be pre-masked and shifted down so the LSB is at bit 0
653 * before calling. Returns 0 on error
655 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
657 const struct clksel *clks;
658 const struct clksel_rate *clkr;
660 clks = omap2_get_clksel_by_parent(clk, clk->parent);
664 for (clkr = clks->rates; clkr->div; clkr++) {
665 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
670 printk(KERN_ERR "clock: Could not find fieldval %d for "
671 "clock %s parent %s\n", field_val, clk->name,
680 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
681 * @clk: OMAP struct clk to use
682 * @div: integer divisor to search for
684 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
685 * find the corresponding register field value. The return register value is
686 * the value before left-shifting. Returns 0xffffffff on error
688 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
690 const struct clksel *clks;
691 const struct clksel_rate *clkr;
693 /* should never happen */
696 clks = omap2_get_clksel_by_parent(clk, clk->parent);
700 for (clkr = clks->rates; clkr->div; clkr++) {
701 if ((clkr->flags & cpu_mask) && (clkr->div == div))
706 printk(KERN_ERR "clock: Could not find divisor %d for "
707 "clock %s parent %s\n", div, clk->name,
716 * omap2_clksel_get_divisor - get current divider applied to parent clock.
717 * @clk: OMAP struct clk to use.
719 * Returns the integer divisor upon success or 0 on error.
721 u32 omap2_clksel_get_divisor(struct clk *clk)
725 if (!clk->clksel_mask)
728 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
729 v &= clk->clksel_mask;
730 v >>= __ffs(clk->clksel_mask);
732 return omap2_clksel_to_divisor(clk, v);
735 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
737 u32 v, field_val, validrate, new_div = 0;
739 if (!clk->clksel_mask)
742 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
743 if (validrate != rate)
746 field_val = omap2_divisor_to_clksel(clk, new_div);
750 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
751 v &= ~clk->clksel_mask;
752 v |= field_val << __ffs(clk->clksel_mask);
753 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
757 clk->rate = clk->parent->rate / new_div;
759 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
760 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
761 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
769 /* Set the clock rate for a clock source */
770 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
774 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
776 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
777 rate table mechanism, driven by mpu_speed */
778 if (clk->flags & CONFIG_PARTICIPANT)
781 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
782 if (clk->set_rate != NULL)
783 ret = clk->set_rate(clk, rate);
785 if (ret == 0 && (clk->flags & RATE_PROPAGATES))
792 * Converts encoded control register address into a full address
793 * On error, the return value (parent_div) will be 0.
795 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
798 const struct clksel *clks;
799 const struct clksel_rate *clkr;
801 clks = omap2_get_clksel_by_parent(clk, src_clk);
805 for (clkr = clks->rates; clkr->div; clkr++) {
806 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
807 break; /* Found the default rate for this platform */
811 printk(KERN_ERR "clock: Could not find default rate for "
812 "clock %s parent %s\n", clk->name,
813 src_clk->parent->name);
817 /* Should never happen. Add a clksel mask to the struct clk. */
818 WARN_ON(clk->clksel_mask == 0);
820 *field_val = clkr->val;
825 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
827 u32 field_val, v, parent_div;
829 if (clk->flags & CONFIG_PARTICIPANT)
835 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
839 if (clk->usecount > 0)
840 _omap2_clk_disable(clk);
842 /* Set new source value (previous dividers if any in effect) */
843 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
844 v &= ~clk->clksel_mask;
845 v |= field_val << __ffs(clk->clksel_mask);
846 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
849 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
850 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
851 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
855 if (clk->usecount > 0)
856 _omap2_clk_enable(clk);
858 clk->parent = new_parent;
860 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
861 clk->rate = new_parent->rate;
864 clk->rate /= parent_div;
866 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
867 clk->name, clk->parent->name, clk->rate);
869 if (clk->flags & RATE_PROPAGATES)
875 /* DPLL rate rounding code */
878 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
879 * @clk: struct clk * of the DPLL
880 * @tolerance: maximum rate error tolerance
882 * Set the maximum DPLL rate error tolerance for the rate rounding
883 * algorithm. The rate tolerance is an attempt to balance DPLL power
884 * saving (the least divider value "n") vs. rate fidelity (the least
885 * difference between the desired DPLL target rate and the rounded
886 * rate out of the algorithm). So, increasing the tolerance is likely
887 * to decrease DPLL power consumption and increase DPLL rate error.
888 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
889 * DPLL; or 0 upon success.
891 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
893 if (!clk || !clk->dpll_data)
896 clk->dpll_data->rate_tolerance = tolerance;
901 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
902 unsigned int m, unsigned int n)
904 unsigned long long num;
906 num = (unsigned long long)parent_rate * m;
912 * _dpll_test_mult - test a DPLL multiplier value
913 * @m: pointer to the DPLL m (multiplier) value under test
914 * @n: current DPLL n (divider) value under test
915 * @new_rate: pointer to storage for the resulting rounded rate
916 * @target_rate: the desired DPLL rate
917 * @parent_rate: the DPLL's parent clock rate
919 * This code tests a DPLL multiplier value, ensuring that the
920 * resulting rate will not be higher than the target_rate, and that
921 * the multiplier value itself is valid for the DPLL. Initially, the
922 * integer pointed to by the m argument should be prescaled by
923 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
924 * a non-scaled m upon return. This non-scaled m will result in a
925 * new_rate as close as possible to target_rate (but not greater than
926 * target_rate) given the current (parent_rate, n, prescaled m)
927 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
928 * non-scaled m attempted to underflow, which can allow the calling
929 * function to bail out early; or 0 upon success.
931 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
932 unsigned long target_rate,
933 unsigned long parent_rate)
935 int r = 0, carry = 0;
937 /* Unscale m and round if necessary */
938 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
940 *m = (*m / DPLL_SCALE_FACTOR) + carry;
943 * The new rate must be <= the target rate to avoid programming
944 * a rate that is impossible for the hardware to handle
946 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
947 if (*new_rate > target_rate) {
952 /* Guard against m underflow */
953 if (*m < DPLL_MIN_MULTIPLIER) {
954 *m = DPLL_MIN_MULTIPLIER;
956 r = DPLL_MULT_UNDERFLOW;
960 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
966 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
967 * @clk: struct clk * for a DPLL
968 * @target_rate: desired DPLL clock rate
970 * Given a DPLL, a desired target rate, and a rate tolerance, round
971 * the target rate to a possible, programmable rate for this DPLL.
972 * Rate tolerance is assumed to be set by the caller before this
973 * function is called. Attempts to select the minimum possible n
974 * within the tolerance to reduce power consumption. Stores the
975 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
976 * will not need to call this (expensive) function again. Returns ~0
977 * if the target rate cannot be rounded, either because the rate is
978 * too low or because the rate tolerance is set too tightly; or the
979 * rounded rate upon success.
981 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
983 int m, n, r, e, scaled_max_m;
984 unsigned long scaled_rt_rp, new_rate;
985 int min_e = -1, min_e_m = -1, min_e_n = -1;
986 struct dpll_data *dd;
988 if (!clk || !clk->dpll_data)
993 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
994 "%ld\n", clk->name, target_rate);
996 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
997 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
999 dd->last_rounded_rate = 0;
1001 for (n = dd->min_divider; n <= dd->max_divider; n++) {
1003 /* Is the (input clk, divider) pair valid for the DPLL? */
1004 r = _dpll_test_fint(clk, n);
1005 if (r == DPLL_FINT_UNDERFLOW)
1007 else if (r == DPLL_FINT_INVALID)
1010 /* Compute the scaled DPLL multiplier, based on the divider */
1011 m = scaled_rt_rp * n;
1014 * Since we're counting n up, a m overflow means we
1015 * can bail out completely (since as n increases in
1016 * the next iteration, there's no way that m can
1017 * increase beyond the current m)
1019 if (m > scaled_max_m)
1022 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1025 /* m can't be set low enough for this n - try with a larger n */
1026 if (r == DPLL_MULT_UNDERFLOW)
1029 e = target_rate - new_rate;
1030 pr_debug("clock: n = %d: m = %d: rate error is %d "
1031 "(new_rate = %ld)\n", n, m, e, new_rate);
1034 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
1039 pr_debug("clock: found new least error %d\n", min_e);
1041 /* We found good settings -- bail out now */
1042 if (min_e <= dd->rate_tolerance)
1048 pr_debug("clock: error: target rate or tolerance too low\n");
1052 dd->last_rounded_m = min_e_m;
1053 dd->last_rounded_n = min_e_n;
1054 dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate,
1057 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1058 min_e, min_e_m, min_e_n);
1059 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1060 dd->last_rounded_rate, target_rate);
1062 return dd->last_rounded_rate;
1065 /*-------------------------------------------------------------------------
1066 * Omap2 clock reset and init functions
1067 *-------------------------------------------------------------------------*/
1069 #ifdef CONFIG_OMAP_RESET_CLOCKS
1070 void omap2_clk_disable_unused(struct clk *clk)
1074 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1076 regval32 = _omap2_clk_read_reg(clk->enable_reg, clk);
1077 if ((regval32 & (1 << clk->enable_bit)) == v)
1080 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1081 _omap2_clk_disable(clk);