2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <mach/control.h>
33 #include <asm/div64.h>
35 #include <mach/sdrc.h>
39 #include "prm-regbits-24xx.h"
41 #include "cm-regbits-24xx.h"
42 #include "cm-regbits-34xx.h"
44 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
47 #define DPLL_MIN_MULTIPLIER 1
48 #define DPLL_MIN_DIVIDER 1
50 /* Possible error results from _dpll_test_mult */
51 #define DPLL_MULT_UNDERFLOW -1
54 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
55 * The higher the scale factor, the greater the risk of arithmetic overflow,
56 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
57 * must be a power of DPLL_SCALE_BASE.
59 #define DPLL_SCALE_FACTOR 64
60 #define DPLL_SCALE_BASE 2
61 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
62 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
65 #define DPLL_FINT_BAND1_MIN 750000
66 #define DPLL_FINT_BAND1_MAX 2100000
67 #define DPLL_FINT_BAND2_MIN 7500000
68 #define DPLL_FINT_BAND2_MAX 21000000
70 /* _dpll_test_fint() return codes */
71 #define DPLL_FINT_UNDERFLOW -1
72 #define DPLL_FINT_INVALID -2
74 /* Bitmask to isolate the register type of clk.enable_reg */
75 #define PRCM_REGTYPE_MASK 0xf0
76 /* various CM register type options */
77 #define CM_FCLKEN_REGTYPE 0x00
78 #define CM_ICLKEN_REGTYPE 0x10
79 #define CM_IDLEST_REGTYPE 0x20
83 /*-------------------------------------------------------------------------
84 * OMAP2/3 specific clock functions
85 *-------------------------------------------------------------------------*/
88 * _omap2_clk_read_reg - read a clock register
91 * Given a struct clk *, returns the value of the clock's register.
93 static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
95 if (clk->prcm_mod & CLK_REG_IN_SCM)
96 return omap_ctrl_readl(reg_offset);
97 else if (clk->prcm_mod & CLK_REG_IN_PRM)
98 return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
101 return cm_read_mod_reg(clk->prcm_mod, reg_offset);
105 * _omap2_clk_write_reg - write a clock's register
106 * @v: value to write to the clock's enable_reg
109 * Given a register value @v and struct clk * @clk, writes the value of @v to
110 * the clock's enable register. No return value.
112 static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
114 if (clk->prcm_mod & CLK_REG_IN_SCM)
115 omap_ctrl_writel(v, reg_offset);
116 else if (clk->prcm_mod & CLK_REG_IN_PRM)
117 prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
120 cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
124 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
125 * @clk: DPLL struct clk to test
126 * @n: divider value (N) to test
128 * Tests whether a particular divider @n will result in a valid DPLL
129 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
130 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
131 * (assuming that it is counting N upwards), or -2 if the enclosing loop
132 * should skip to the next iteration (again assuming N is increasing).
134 static int _dpll_test_fint(struct clk *clk, u8 n)
136 struct dpll_data *dd;
142 /* DPLL divider must result in a valid jitter correction val */
143 fint = clk->parent->rate / (n + 1);
144 if (fint < DPLL_FINT_BAND1_MIN) {
146 pr_debug("rejecting n=%d due to Fint failure, "
147 "lowering max_divider\n", n);
149 ret = DPLL_FINT_UNDERFLOW;
151 } else if (fint > DPLL_FINT_BAND1_MAX &&
152 fint < DPLL_FINT_BAND2_MIN) {
154 pr_debug("rejecting n=%d due to Fint failure\n", n);
155 ret = DPLL_FINT_INVALID;
157 } else if (fint > DPLL_FINT_BAND2_MAX) {
159 pr_debug("rejecting n=%d due to Fint failure, "
160 "boosting min_divider\n", n);
162 ret = DPLL_FINT_INVALID;
170 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
171 * @clk: OMAP clock struct ptr to use
173 * Convert a clockdomain name stored in a struct clk 'clk' into a
174 * clockdomain pointer, and save it into the struct clk. Intended to be
175 * called during clk_register(). No return value.
177 void omap2_init_clk_clkdm(struct clk *clk)
179 struct clockdomain *clkdm;
181 if (!clk->clkdm.name) {
182 pr_err("clock: %s: missing clockdomain", clk->name);
186 clkdm = clkdm_lookup(clk->clkdm.name);
188 pr_debug("clock: associated clk %s to clkdm %s\n",
189 clk->name, clk->clkdm.name);
190 clk->clkdm.ptr = clkdm;
192 pr_err("clock: %s: could not associate to clkdm %s\n",
193 clk->name, clk->clkdm.name);
198 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
199 * @clk: OMAP clock struct ptr to use
201 * Given a pointer to a source-selectable struct clk, read the hardware
202 * register and determine what its parent is currently set to. Update the
203 * clk->parent field with the appropriate clk ptr.
205 void omap2_init_clksel_parent(struct clk *clk)
207 const struct clksel *clks;
208 const struct clksel_rate *clkr;
214 r = _omap2_clk_read_reg(clk->clksel_reg, clk);
215 r &= clk->clksel_mask;
216 r >>= __ffs(clk->clksel_mask);
218 for (clks = clk->clksel; clks->parent && !found; clks++) {
219 for (clkr = clks->rates; clkr->div && !found; clkr++) {
220 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
221 if (clk->parent != clks->parent) {
222 pr_debug("clock: inited %s parent "
224 clk->name, clks->parent->name,
226 clk->parent->name : "NULL"));
227 clk->parent = clks->parent;
235 printk(KERN_ERR "clock: init parent: could not find "
236 "regval %0x for clock %s\n", r, clk->name);
242 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
243 * @clk: struct clk * of a DPLL
245 * DPLLs can be locked or bypassed - basically, enabled or disabled.
246 * When locked, the DPLL output depends on the M and N values. When
247 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
248 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
249 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
250 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
251 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
252 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
253 * if the clock @clk is not a DPLL.
255 u32 omap2_get_dpll_rate(struct clk *clk)
258 u32 dpll_mult, dpll_div, v;
259 struct dpll_data *dd;
265 /* Return bypass rate if DPLL is bypassed */
266 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
267 v &= dd->enable_mask;
268 v >>= __ffs(dd->enable_mask);
270 if (cpu_is_omap24xx()) {
272 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
273 v == OMAP2XXX_EN_DPLL_FRBYPASS)
274 return clk->parent->rate;
276 } else if (cpu_is_omap34xx()) {
278 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
279 v == OMAP3XXX_EN_DPLL_FRBYPASS)
280 return dd->bypass_clk->rate;
284 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
285 dpll_mult = v & dd->mult_mask;
286 dpll_mult >>= __ffs(dd->mult_mask);
287 dpll_div = v & dd->div1_mask;
288 dpll_div >>= __ffs(dd->div1_mask);
290 dpll_clk = (long long)clk->parent->rate * dpll_mult;
291 do_div(dpll_clk, dpll_div + 1);
297 * Used for clocks that have the same value as the parent clock,
298 * divided by some factor
300 void omap2_fixed_divisor_recalc(struct clk *clk)
302 WARN_ON(!clk->fixed_div);
304 clk->rate = clk->parent->rate / clk->fixed_div;
308 * omap2_wait_clock_ready - wait for clock to enable
309 * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
310 * @reg_index: offset of CM register address from prcm_mod
311 * @mask: value to mask against to determine if the clock is active
312 * @name: name of the clock (for printk)
314 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
315 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
317 int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
323 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
324 * 34xx reverses this, just to keep us on our toes
326 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
328 else if (cpu_mask & RATE_IN_343X)
332 while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
333 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
337 if (i < MAX_CLOCK_ENABLE_WAIT)
338 pr_debug("Clock %s stable after %d loops\n", name, i);
340 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
341 name, MAX_CLOCK_ENABLE_WAIT);
343 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
348 * omap2_clk_wait_ready - wait for a OMAP module to come out of target idle
349 * @clk: struct clk * recently enabled to indicate the module to test
351 * Wait for an OMAP module with a target idle state bit to come out of
352 * idle once both its interface clock and primary functional clock are
353 * both enabled. Any register read or write to the device before it
354 * returns from idle will cause an abort. Not all modules have target
355 * idle state bits (for example, DSS and CAM on OMAP24xx); so we don't
356 * wait for those. No return value.
358 * We don't need special code here for INVERT_ENABLE for the time
359 * being since INVERT_ENABLE only applies to clocks enabled by
362 * REVISIT: This function is misnamed: it should be something like
363 * "omap2_module_wait_ready", and in the long-term, it does not belong
364 * in the clock framework. It also shouldn't be doing register
365 * arithmetic to determine the companion clock.
367 static void omap2_clk_wait_ready(struct clk *clk)
369 u16 other_reg, idlest_reg;
372 if (!(clk->flags & WAIT_READY))
375 /* If we are enabling an iclk, also test the fclk; and vice versa */
376 other_bit = 1 << clk->enable_bit;
377 other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK;
379 if (clk->enable_reg & CM_ICLKEN_REGTYPE)
380 other_reg |= CM_FCLKEN_REGTYPE;
382 other_reg |= CM_ICLKEN_REGTYPE;
384 /* Ensure functional and interface clocks are running. */
385 if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit))
388 idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
389 idlest_reg |= CM_IDLEST_REGTYPE;
391 omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, 1 << clk->idlest_bit,
395 /* Enables clock without considering parent dependencies or use count
396 * REVISIT: Maybe change this to use clk->enable like on omap1?
398 static int _omap2_clk_enable(struct clk *clk)
402 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
406 return clk->enable(clk);
408 v = _omap2_clk_read_reg(clk->enable_reg, clk);
409 if (clk->flags & INVERT_ENABLE)
410 v &= ~(1 << clk->enable_bit);
412 v |= (1 << clk->enable_bit);
413 _omap2_clk_write_reg(v, clk->enable_reg, clk);
416 omap2_clk_wait_ready(clk);
421 /* Disables clock without considering parent dependencies or use count */
422 static void _omap2_clk_disable(struct clk *clk)
426 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
434 v = _omap2_clk_read_reg(clk->enable_reg, clk);
435 if (clk->flags & INVERT_ENABLE)
436 v |= (1 << clk->enable_bit);
438 v &= ~(1 << clk->enable_bit);
439 _omap2_clk_write_reg(v, clk->enable_reg, clk);
443 void omap2_clk_disable(struct clk *clk)
445 if (clk->usecount > 0 && !(--clk->usecount)) {
446 _omap2_clk_disable(clk);
448 omap2_clk_disable(clk->parent);
450 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
455 int omap2_clk_enable(struct clk *clk)
459 if (clk->usecount++ == 0) {
461 ret = omap2_clk_enable(clk->parent);
469 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
471 ret = _omap2_clk_enable(clk);
475 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
478 omap2_clk_disable(clk->parent);
488 * Used for clocks that are part of CLKSEL_xyz governed clocks.
489 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
491 void omap2_clksel_recalc(struct clk *clk)
495 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
497 div = omap2_clksel_get_divisor(clk);
501 if (clk->rate == (clk->parent->rate / div))
503 clk->rate = clk->parent->rate / div;
505 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
509 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
510 * @clk: OMAP struct clk ptr to inspect
511 * @src_clk: OMAP struct clk ptr of the parent clk to search for
513 * Scan the struct clksel array associated with the clock to find
514 * the element associated with the supplied parent clock address.
515 * Returns a pointer to the struct clksel on success or NULL on error.
517 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
520 const struct clksel *clks;
525 for (clks = clk->clksel; clks->parent; clks++) {
526 if (clks->parent == src_clk)
527 break; /* Found the requested parent */
531 printk(KERN_ERR "clock: Could not find parent clock %s in "
532 "clksel array of clock %s\n", src_clk->name,
541 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
542 * @clk: OMAP struct clk to use
543 * @target_rate: desired clock rate
544 * @new_div: ptr to where we should store the divisor
546 * Finds 'best' divider value in an array based on the source and target
547 * rates. The divider array must be sorted with smallest divider first.
548 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
549 * they are only settable as part of virtual_prcm set.
551 * Returns the rounded clock rate or returns 0xffffffff on error.
553 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
556 unsigned long test_rate;
557 const struct clksel *clks;
558 const struct clksel_rate *clkr;
561 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
562 clk->name, target_rate);
566 clks = omap2_get_clksel_by_parent(clk, clk->parent);
570 for (clkr = clks->rates; clkr->div; clkr++) {
571 if (!(clkr->flags & cpu_mask))
575 if (clkr->div <= last_div)
576 printk(KERN_ERR "clock: clksel_rate table not sorted "
577 "for clock %s", clk->name);
579 last_div = clkr->div;
581 test_rate = clk->parent->rate / clkr->div;
583 if (test_rate <= target_rate)
584 break; /* found it */
588 printk(KERN_ERR "clock: Could not find divisor for target "
589 "rate %ld for clock %s parent %s\n", target_rate,
590 clk->name, clk->parent->name);
594 *new_div = clkr->div;
596 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
597 (clk->parent->rate / clkr->div));
599 return (clk->parent->rate / clkr->div);
603 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
604 * @clk: OMAP struct clk to use
605 * @target_rate: desired clock rate
607 * Compatibility wrapper for OMAP clock framework
608 * Finds best target rate based on the source clock and possible dividers.
609 * rates. The divider array must be sorted with smallest divider first.
610 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
611 * they are only settable as part of virtual_prcm set.
613 * Returns the rounded clock rate or returns 0xffffffff on error.
615 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
619 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
623 /* Given a clock and a rate apply a clock specific rounding function */
624 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
626 if (clk->round_rate != NULL)
627 return clk->round_rate(clk, rate);
629 if (clk->flags & RATE_FIXED)
630 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
631 "on fixed-rate clock %s\n", clk->name);
637 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
638 * @clk: OMAP struct clk to use
639 * @field_val: register field value to find
641 * Given a struct clk of a rate-selectable clksel clock, and a register field
642 * value to search for, find the corresponding clock divisor. The register
643 * field value should be pre-masked and shifted down so the LSB is at bit 0
644 * before calling. Returns 0 on error
646 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
648 const struct clksel *clks;
649 const struct clksel_rate *clkr;
651 clks = omap2_get_clksel_by_parent(clk, clk->parent);
655 for (clkr = clks->rates; clkr->div; clkr++) {
656 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
661 printk(KERN_ERR "clock: Could not find fieldval %d for "
662 "clock %s parent %s\n", field_val, clk->name,
671 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
672 * @clk: OMAP struct clk to use
673 * @div: integer divisor to search for
675 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
676 * find the corresponding register field value. The return register value is
677 * the value before left-shifting. Returns 0xffffffff on error
679 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
681 const struct clksel *clks;
682 const struct clksel_rate *clkr;
684 /* should never happen */
687 clks = omap2_get_clksel_by_parent(clk, clk->parent);
691 for (clkr = clks->rates; clkr->div; clkr++) {
692 if ((clkr->flags & cpu_mask) && (clkr->div == div))
697 printk(KERN_ERR "clock: Could not find divisor %d for "
698 "clock %s parent %s\n", div, clk->name,
707 * omap2_clksel_get_divisor - get current divider applied to parent clock.
708 * @clk: OMAP struct clk to use.
710 * Returns the integer divisor upon success or 0 on error.
712 u32 omap2_clksel_get_divisor(struct clk *clk)
716 if (!clk->clksel_mask)
719 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
720 v &= clk->clksel_mask;
721 v >>= __ffs(clk->clksel_mask);
723 return omap2_clksel_to_divisor(clk, v);
726 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
728 u32 v, field_val, validrate, new_div = 0;
730 if (!clk->clksel_mask)
733 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
734 if (validrate != rate)
737 field_val = omap2_divisor_to_clksel(clk, new_div);
741 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
742 v &= ~clk->clksel_mask;
743 v |= field_val << __ffs(clk->clksel_mask);
744 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
748 clk->rate = clk->parent->rate / new_div;
750 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
751 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
752 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
760 /* Set the clock rate for a clock source */
761 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
765 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
767 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
768 rate table mechanism, driven by mpu_speed */
769 if (clk->flags & CONFIG_PARTICIPANT)
772 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
773 if (clk->set_rate != NULL)
774 ret = clk->set_rate(clk, rate);
780 * Converts encoded control register address into a full address
781 * On error, the return value (parent_div) will be 0.
783 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
786 const struct clksel *clks;
787 const struct clksel_rate *clkr;
789 clks = omap2_get_clksel_by_parent(clk, src_clk);
793 for (clkr = clks->rates; clkr->div; clkr++) {
794 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
795 break; /* Found the default rate for this platform */
799 printk(KERN_ERR "clock: Could not find default rate for "
800 "clock %s parent %s\n", clk->name,
801 src_clk->parent->name);
805 /* Should never happen. Add a clksel mask to the struct clk. */
806 WARN_ON(clk->clksel_mask == 0);
808 *field_val = clkr->val;
813 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
815 u32 field_val, v, parent_div;
817 if (clk->flags & CONFIG_PARTICIPANT)
823 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
827 if (clk->usecount > 0)
828 _omap2_clk_disable(clk);
830 /* Set new source value (previous dividers if any in effect) */
831 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
832 v &= ~clk->clksel_mask;
833 v |= field_val << __ffs(clk->clksel_mask);
834 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
837 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
838 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
839 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
843 if (clk->usecount > 0)
844 _omap2_clk_enable(clk);
846 clk->parent = new_parent;
848 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
849 clk->rate = new_parent->rate;
852 clk->rate /= parent_div;
854 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
855 clk->name, clk->parent->name, clk->rate);
860 struct clk *omap2_clk_get_parent(struct clk *clk)
865 /* DPLL rate rounding code */
868 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
869 * @clk: struct clk * of the DPLL
870 * @tolerance: maximum rate error tolerance
872 * Set the maximum DPLL rate error tolerance for the rate rounding
873 * algorithm. The rate tolerance is an attempt to balance DPLL power
874 * saving (the least divider value "n") vs. rate fidelity (the least
875 * difference between the desired DPLL target rate and the rounded
876 * rate out of the algorithm). So, increasing the tolerance is likely
877 * to decrease DPLL power consumption and increase DPLL rate error.
878 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
879 * DPLL; or 0 upon success.
881 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
883 if (!clk || !clk->dpll_data)
886 clk->dpll_data->rate_tolerance = tolerance;
891 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
892 unsigned int m, unsigned int n)
894 unsigned long long num;
896 num = (unsigned long long)parent_rate * m;
902 * _dpll_test_mult - test a DPLL multiplier value
903 * @m: pointer to the DPLL m (multiplier) value under test
904 * @n: current DPLL n (divider) value under test
905 * @new_rate: pointer to storage for the resulting rounded rate
906 * @target_rate: the desired DPLL rate
907 * @parent_rate: the DPLL's parent clock rate
909 * This code tests a DPLL multiplier value, ensuring that the
910 * resulting rate will not be higher than the target_rate, and that
911 * the multiplier value itself is valid for the DPLL. Initially, the
912 * integer pointed to by the m argument should be prescaled by
913 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
914 * a non-scaled m upon return. This non-scaled m will result in a
915 * new_rate as close as possible to target_rate (but not greater than
916 * target_rate) given the current (parent_rate, n, prescaled m)
917 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
918 * non-scaled m attempted to underflow, which can allow the calling
919 * function to bail out early; or 0 upon success.
921 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
922 unsigned long target_rate,
923 unsigned long parent_rate)
925 int r = 0, carry = 0;
927 /* Unscale m and round if necessary */
928 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
930 *m = (*m / DPLL_SCALE_FACTOR) + carry;
933 * The new rate must be <= the target rate to avoid programming
934 * a rate that is impossible for the hardware to handle
936 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
937 if (*new_rate > target_rate) {
942 /* Guard against m underflow */
943 if (*m < DPLL_MIN_MULTIPLIER) {
944 *m = DPLL_MIN_MULTIPLIER;
946 r = DPLL_MULT_UNDERFLOW;
950 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
956 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
957 * @clk: struct clk * for a DPLL
958 * @target_rate: desired DPLL clock rate
960 * Given a DPLL, a desired target rate, and a rate tolerance, round
961 * the target rate to a possible, programmable rate for this DPLL.
962 * Rate tolerance is assumed to be set by the caller before this
963 * function is called. Attempts to select the minimum possible n
964 * within the tolerance to reduce power consumption. Stores the
965 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
966 * will not need to call this (expensive) function again. Returns ~0
967 * if the target rate cannot be rounded, either because the rate is
968 * too low or because the rate tolerance is set too tightly; or the
969 * rounded rate upon success.
971 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
973 int m, n, r, e, scaled_max_m;
974 unsigned long scaled_rt_rp, new_rate;
975 int min_e = -1, min_e_m = -1, min_e_n = -1;
976 struct dpll_data *dd;
978 if (!clk || !clk->dpll_data)
983 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
984 "%ld\n", clk->name, target_rate);
986 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
987 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
989 dd->last_rounded_rate = 0;
991 for (n = dd->min_divider; n <= dd->max_divider; n++) {
993 /* Is the (input clk, divider) pair valid for the DPLL? */
994 r = _dpll_test_fint(clk, n);
995 if (r == DPLL_FINT_UNDERFLOW)
997 else if (r == DPLL_FINT_INVALID)
1000 /* Compute the scaled DPLL multiplier, based on the divider */
1001 m = scaled_rt_rp * n;
1004 * Since we're counting n up, a m overflow means we
1005 * can bail out completely (since as n increases in
1006 * the next iteration, there's no way that m can
1007 * increase beyond the current m)
1009 if (m > scaled_max_m)
1012 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1015 /* m can't be set low enough for this n - try with a larger n */
1016 if (r == DPLL_MULT_UNDERFLOW)
1019 e = target_rate - new_rate;
1020 pr_debug("clock: n = %d: m = %d: rate error is %d "
1021 "(new_rate = %ld)\n", n, m, e, new_rate);
1024 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
1029 pr_debug("clock: found new least error %d\n", min_e);
1031 /* We found good settings -- bail out now */
1032 if (min_e <= dd->rate_tolerance)
1038 pr_debug("clock: error: target rate or tolerance too low\n");
1042 dd->last_rounded_m = min_e_m;
1043 dd->last_rounded_n = min_e_n;
1044 dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate,
1047 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1048 min_e, min_e_m, min_e_n);
1049 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1050 dd->last_rounded_rate, target_rate);
1052 return dd->last_rounded_rate;
1055 /*-------------------------------------------------------------------------
1056 * Omap2 clock reset and init functions
1057 *-------------------------------------------------------------------------*/
1059 #ifdef CONFIG_OMAP_RESET_CLOCKS
1060 void omap2_clk_disable_unused(struct clk *clk)
1064 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1066 regval32 = _omap2_clk_read_reg(clk->enable_reg, clk);
1067 if ((regval32 & (1 << clk->enable_bit)) == v)
1070 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1071 _omap2_clk_disable(clk);