arch/arm/mach-omap1/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static int omap1_clk_enable_generic(struct clk * clk);
  17 static void omap1_clk_disable_generic(struct clk * clk);
  18 static void omap1_ckctl_recalc(struct clk *clk, unsigned long parent_rate,
  19                                u8 rate_storage);
  20 static void omap1_watchdog_recalc(struct clk *clk, unsigned long parent_rate,
  21                                   u8 rate_storage);
  22 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
  23 static void omap1_sossi_recalc(struct clk *clk, unsigned long parent_rate,
  24                                u8 rate_storage);
  25 static void omap1_ckctl_recalc_dsp_domain(struct clk *clk,
  26                                           unsigned long parent_rate,
  27                                           u8 rate_storage);
  28 static int omap1_clk_enable_dsp_domain(struct clk * clk);
  29 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  30 static void omap1_clk_disable_dsp_domain(struct clk * clk);
  31 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  32 static void omap1_uart_recalc(struct clk *clk, unsigned long parent_rate,
  33                               u8 rate_storage);
  34 static int omap1_clk_enable_uart_functional(struct clk * clk);
  35 static void omap1_clk_disable_uart_functional(struct clk * clk);
  36 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  37 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  38 static void omap1_init_ext_clk(struct clk * clk);
  39 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  40 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  41 static int omap1_clk_enable(struct clk *clk);
  42 static void omap1_clk_disable(struct clk *clk);
  43
  44 struct mpu_rate {
  45         unsigned long           rate;
  46         unsigned long           xtal;
  47         unsigned long           pll_rate;
  48         __u16                   ckctl_val;
  49         __u16                   dpllctl_val;
  50 };
  51
  52 struct uart_clk {
  53         struct clk      clk;
  54         unsigned long   sysc_addr;
  55 };
  56
  57 /* Provide a method for preventing idling some ARM IDLECT clocks */
  58 struct arm_idlect1_clk {
  59         struct clk      clk;
  60         unsigned long   no_idle_count;
  61         __u8            idlect_shift;
  62 };
  63
  64 /* ARM_CKCTL bit shifts */
  65 #define CKCTL_PERDIV_OFFSET     0
  66 #define CKCTL_LCDDIV_OFFSET     2
  67 #define CKCTL_ARMDIV_OFFSET     4
  68 #define CKCTL_DSPDIV_OFFSET     6
  69 #define CKCTL_TCDIV_OFFSET      8
  70 #define CKCTL_DSPMMUDIV_OFFSET  10
  71 /*#define ARM_TIMXO             12*/
  72 #define EN_DSPCK                13
  73 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  74 /* DSP_CKCTL bit shifts */
  75 #define CKCTL_DSPPERDIV_OFFSET  0
  76
  77 /* ARM_IDLECT2 bit shifts */
  78 #define EN_WDTCK        0
  79 #define EN_XORPCK       1
  80 #define EN_PERCK        2
  81 #define EN_LCDCK        3
  82 #define EN_LBCK         4 /* Not on 1610/1710 */
  83 /*#define EN_HSABCK     5*/
  84 #define EN_APICK        6
  85 #define EN_TIMCK        7
  86 #define DMACK_REQ       8
  87 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  88 /*#define EN_LBFREECK   10*/
  89 #define EN_CKOUT_ARM    11
  90
  91 /* ARM_IDLECT3 bit shifts */
  92 #define EN_OCPI_CK      0
  93 #define EN_TC1_CK       2
  94 #define EN_TC2_CK       4
  95
  96 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  97 #define EN_DSPTIMCK     5
  98
  99 /* Various register defines for clock controls scattered around OMAP chip */
 100 #define SDW_MCLK_INV_BIT        2       /* In ULPD_CLKC_CTRL */
 101 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
 102 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
 103 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
 104 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
 105 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
 106 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
 107 #define SOFT_REQ_REG            0xfffe0834
 108 #define SOFT_REQ_REG2           0xfffe0880
 109
 110 /*-------------------------------------------------------------------------
 111  * Omap1 MPU rate table
 112  *-------------------------------------------------------------------------*/
 113 static struct mpu_rate rate_table[] = {
 114         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 115          * NOTE: Comment order here is different from bits in CKCTL value:
 116          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 117          */
 118 #if defined(CONFIG_OMAP_ARM_216MHZ)
 119         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 120 #endif
 121 #if defined(CONFIG_OMAP_ARM_195MHZ)
 122         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 123 #endif
 124 #if defined(CONFIG_OMAP_ARM_192MHZ)
 125         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 126         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 127         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 128         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 129         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 130 #endif
 131 #if defined(CONFIG_OMAP_ARM_182MHZ)
 132         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 133 #endif
 134 #if defined(CONFIG_OMAP_ARM_168MHZ)
 135         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 136 #endif
 137 #if defined(CONFIG_OMAP_ARM_150MHZ)
 138         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 139 #endif
 140 #if defined(CONFIG_OMAP_ARM_120MHZ)
 141         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 142 #endif
 143 #if defined(CONFIG_OMAP_ARM_96MHZ)
 144         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 145 #endif
 146 #if defined(CONFIG_OMAP_ARM_60MHZ)
 147         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 148 #endif
 149 #if defined(CONFIG_OMAP_ARM_30MHZ)
 150         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 151 #endif
 152         { 0, 0, 0, 0, 0 },
 153 };
 154
 155 /*-------------------------------------------------------------------------
 156  * Omap1 clocks
 157  *-------------------------------------------------------------------------*/
 158
 159 static struct clk ck_ref = {
 160         .name           = "ck_ref",
 161         .rate           = 12000000,
 162         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 163                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 164         .enable         = &omap1_clk_enable_generic,
 165         .disable        = &omap1_clk_disable_generic,
 166 };
 167
 168 static struct clk ck_dpll1 = {
 169         .name           = "ck_dpll1",
 170         .parent         = &ck_ref,
 171         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 172                           CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
 173         .enable         = &omap1_clk_enable_generic,
 174         .disable        = &omap1_clk_disable_generic,
 175 };
 176
 177 static struct arm_idlect1_clk ck_dpll1out = {
 178         .clk = {
 179                 .name           = "ck_dpll1out",
 180                 .parent         = &ck_dpll1,
 181                 .flags          = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
 182                                   ENABLE_REG_32BIT | RATE_PROPAGATES,
 183                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 184                 .enable_bit     = EN_CKOUT_ARM,
 185                 .recalc         = &followparent_recalc,
 186                 .enable         = &omap1_clk_enable_generic,
 187                 .disable        = &omap1_clk_disable_generic,
 188         },
 189         .idlect_shift   = 12,
 190 };
 191
 192 static struct clk sossi_ck = {
 193         .name           = "ck_sossi",
 194         .parent         = &ck_dpll1out.clk,
 195         .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
 196                           ENABLE_REG_32BIT,
 197         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
 198         .enable_bit     = 16,
 199         .recalc         = &omap1_sossi_recalc,
 200         .set_rate       = &omap1_set_sossi_rate,
 201         .enable         = &omap1_clk_enable_generic,
 202         .disable        = &omap1_clk_disable_generic,
 203 };
 204
 205 static struct clk arm_ck = {
 206         .name           = "arm_ck",
 207         .parent         = &ck_dpll1,
 208         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 209                           CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
 210                           ALWAYS_ENABLED,
 211         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 212         .recalc         = &omap1_ckctl_recalc,
 213         .enable         = &omap1_clk_enable_generic,
 214         .disable        = &omap1_clk_disable_generic,
 215 };
 216
 217 static struct arm_idlect1_clk armper_ck = {
 218         .clk = {
 219                 .name           = "armper_ck",
 220                 .parent         = &ck_dpll1,
 221                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 222                                   CLOCK_IN_OMAP310 | RATE_CKCTL |
 223                                   CLOCK_IDLE_CONTROL,
 224                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 225                 .enable_bit     = EN_PERCK,
 226                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 227                 .recalc         = &omap1_ckctl_recalc,
 228                 .enable         = &omap1_clk_enable_generic,
 229                 .disable        = &omap1_clk_disable_generic,
 230         },
 231         .idlect_shift   = 2,
 232 };
 233
 234 static struct clk arm_gpio_ck = {
 235         .name           = "arm_gpio_ck",
 236         .parent         = &ck_dpll1,
 237         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 238         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 239         .enable_bit     = EN_GPIOCK,
 240         .recalc         = &followparent_recalc,
 241         .enable         = &omap1_clk_enable_generic,
 242         .disable        = &omap1_clk_disable_generic,
 243 };
 244
 245 static struct arm_idlect1_clk armxor_ck = {
 246         .clk = {
 247                 .name           = "armxor_ck",
 248                 .parent         = &ck_ref,
 249                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 250                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 251                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 252                 .enable_bit     = EN_XORPCK,
 253                 .recalc         = &followparent_recalc,
 254                 .enable         = &omap1_clk_enable_generic,
 255                 .disable        = &omap1_clk_disable_generic,
 256         },
 257         .idlect_shift   = 1,
 258 };
 259
 260 static struct arm_idlect1_clk armtim_ck = {
 261         .clk = {
 262                 .name           = "armtim_ck",
 263                 .parent         = &ck_ref,
 264                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 265                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 266                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 267                 .enable_bit     = EN_TIMCK,
 268                 .recalc         = &followparent_recalc,
 269                 .enable         = &omap1_clk_enable_generic,
 270                 .disable        = &omap1_clk_disable_generic,
 271         },
 272         .idlect_shift   = 9,
 273 };
 274
 275 static struct arm_idlect1_clk armwdt_ck = {
 276         .clk = {
 277                 .name           = "armwdt_ck",
 278                 .parent         = &ck_ref,
 279                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 280                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 281                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 282                 .enable_bit     = EN_WDTCK,
 283                 .recalc         = &omap1_watchdog_recalc,
 284                 .enable         = &omap1_clk_enable_generic,
 285                 .disable        = &omap1_clk_disable_generic,
 286         },
 287         .idlect_shift   = 0,
 288 };
 289
 290 static struct clk arminth_ck16xx = {
 291         .name           = "arminth_ck",
 292         .parent         = &arm_ck,
 293         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 294         .recalc         = &followparent_recalc,
 295         /* Note: On 16xx the frequency can be divided by 2 by programming
 296          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 297          *
 298          * 1510 version is in TC clocks.
 299          */
 300         .enable         = &omap1_clk_enable_generic,
 301         .disable        = &omap1_clk_disable_generic,
 302 };
 303
 304 static struct clk dsp_ck = {
 305         .name           = "dsp_ck",
 306         .parent         = &ck_dpll1,
 307         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 308                           RATE_CKCTL,
 309         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 310         .enable_bit     = EN_DSPCK,
 311         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 312         .recalc         = &omap1_ckctl_recalc,
 313         .enable         = &omap1_clk_enable_generic,
 314         .disable        = &omap1_clk_disable_generic,
 315 };
 316
 317 static struct clk dspmmu_ck = {
 318         .name           = "dspmmu_ck",
 319         .parent         = &ck_dpll1,
 320         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 321                           RATE_CKCTL | ALWAYS_ENABLED,
 322         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 323         .recalc         = &omap1_ckctl_recalc,
 324         .enable         = &omap1_clk_enable_generic,
 325         .disable        = &omap1_clk_disable_generic,
 326 };
 327
 328 static struct clk dspper_ck = {
 329         .name           = "dspper_ck",
 330         .parent         = &ck_dpll1,
 331         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 332                           RATE_CKCTL,
 333         .enable_reg     = IOMEM(DSP_IDLECT2),
 334         .enable_bit     = EN_PERCK,
 335         .rate_offset    = CKCTL_PERDIV_OFFSET,
 336         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 337         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 338         .enable         = &omap1_clk_enable_dsp_domain,
 339         .disable        = &omap1_clk_disable_dsp_domain,
 340 };
 341
 342 static struct clk dspxor_ck = {
 343         .name           = "dspxor_ck",
 344         .parent         = &ck_ref,
 345         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 346         .enable_reg     = IOMEM(DSP_IDLECT2),
 347         .enable_bit     = EN_XORPCK,
 348         .recalc         = &followparent_recalc,
 349         .enable         = &omap1_clk_enable_dsp_domain,
 350         .disable        = &omap1_clk_disable_dsp_domain,
 351 };
 352
 353 static struct clk dsptim_ck = {
 354         .name           = "dsptim_ck",
 355         .parent         = &ck_ref,
 356         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 357         .enable_reg     = IOMEM(DSP_IDLECT2),
 358         .enable_bit     = EN_DSPTIMCK,
 359         .recalc         = &followparent_recalc,
 360         .enable         = &omap1_clk_enable_dsp_domain,
 361         .disable        = &omap1_clk_disable_dsp_domain,
 362 };
 363
 364 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 365 static struct arm_idlect1_clk tc_ck = {
 366         .clk = {
 367                 .name           = "tc_ck",
 368                 .parent         = &ck_dpll1,
 369                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 370                                   CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
 371                                   RATE_CKCTL | RATE_PROPAGATES |
 372                                   ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
 373                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 374                 .recalc         = &omap1_ckctl_recalc,
 375                 .enable         = &omap1_clk_enable_generic,
 376                 .disable        = &omap1_clk_disable_generic,
 377         },
 378         .idlect_shift   = 6,
 379 };
 380
 381 static struct clk arminth_ck1510 = {
 382         .name           = "arminth_ck",
 383         .parent         = &tc_ck.clk,
 384         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 385                           ALWAYS_ENABLED,
 386         .recalc         = &followparent_recalc,
 387         /* Note: On 1510 the frequency follows TC_CK
 388          *
 389          * 16xx version is in MPU clocks.
 390          */
 391         .enable         = &omap1_clk_enable_generic,
 392         .disable        = &omap1_clk_disable_generic,
 393 };
 394
 395 static struct clk tipb_ck = {
 396         /* No-idle controlled by "tc_ck" */
 397         .name           = "tipb_ck",
 398         .parent         = &tc_ck.clk,
 399         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 400                           ALWAYS_ENABLED,
 401         .recalc         = &followparent_recalc,
 402         .enable         = &omap1_clk_enable_generic,
 403         .disable        = &omap1_clk_disable_generic,
 404 };
 405
 406 static struct clk l3_ocpi_ck = {
 407         /* No-idle controlled by "tc_ck" */
 408         .name           = "l3_ocpi_ck",
 409         .parent         = &tc_ck.clk,
 410         .flags          = CLOCK_IN_OMAP16XX,
 411         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 412         .enable_bit     = EN_OCPI_CK,
 413         .recalc         = &followparent_recalc,
 414         .enable         = &omap1_clk_enable_generic,
 415         .disable        = &omap1_clk_disable_generic,
 416 };
 417
 418 static struct clk tc1_ck = {
 419         .name           = "tc1_ck",
 420         .parent         = &tc_ck.clk,
 421         .flags          = CLOCK_IN_OMAP16XX,
 422         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 423         .enable_bit     = EN_TC1_CK,
 424         .recalc         = &followparent_recalc,
 425         .enable         = &omap1_clk_enable_generic,
 426         .disable        = &omap1_clk_disable_generic,
 427 };
 428
 429 static struct clk tc2_ck = {
 430         .name           = "tc2_ck",
 431         .parent         = &tc_ck.clk,
 432         .flags          = CLOCK_IN_OMAP16XX,
 433         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 434         .enable_bit     = EN_TC2_CK,
 435         .recalc         = &followparent_recalc,
 436         .enable         = &omap1_clk_enable_generic,
 437         .disable        = &omap1_clk_disable_generic,
 438 };
 439
 440 static struct clk dma_ck = {
 441         /* No-idle controlled by "tc_ck" */
 442         .name           = "dma_ck",
 443         .parent         = &tc_ck.clk,
 444         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 445                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 446         .recalc         = &followparent_recalc,
 447         .enable         = &omap1_clk_enable_generic,
 448         .disable        = &omap1_clk_disable_generic,
 449 };
 450
 451 static struct clk dma_lcdfree_ck = {
 452         .name           = "dma_lcdfree_ck",
 453         .parent         = &tc_ck.clk,
 454         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 455         .recalc         = &followparent_recalc,
 456         .enable         = &omap1_clk_enable_generic,
 457         .disable        = &omap1_clk_disable_generic,
 458 };
 459
 460 static struct arm_idlect1_clk api_ck = {
 461         .clk = {
 462                 .name           = "api_ck",
 463                 .parent         = &tc_ck.clk,
 464                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 465                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 466                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 467                 .enable_bit     = EN_APICK,
 468                 .recalc         = &followparent_recalc,
 469                 .enable         = &omap1_clk_enable_generic,
 470                 .disable        = &omap1_clk_disable_generic,
 471         },
 472         .idlect_shift   = 8,
 473 };
 474
 475 static struct arm_idlect1_clk lb_ck = {
 476         .clk = {
 477                 .name           = "lb_ck",
 478                 .parent         = &tc_ck.clk,
 479                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 480                                   CLOCK_IDLE_CONTROL,
 481                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 482                 .enable_bit     = EN_LBCK,
 483                 .recalc         = &followparent_recalc,
 484                 .enable         = &omap1_clk_enable_generic,
 485                 .disable        = &omap1_clk_disable_generic,
 486         },
 487         .idlect_shift   = 4,
 488 };
 489
 490 static struct clk rhea1_ck = {
 491         .name           = "rhea1_ck",
 492         .parent         = &tc_ck.clk,
 493         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 494         .recalc         = &followparent_recalc,
 495         .enable         = &omap1_clk_enable_generic,
 496         .disable        = &omap1_clk_disable_generic,
 497 };
 498
 499 static struct clk rhea2_ck = {
 500         .name           = "rhea2_ck",
 501         .parent         = &tc_ck.clk,
 502         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 503         .recalc         = &followparent_recalc,
 504         .enable         = &omap1_clk_enable_generic,
 505         .disable        = &omap1_clk_disable_generic,
 506 };
 507
 508 static struct clk lcd_ck_16xx = {
 509         .name           = "lcd_ck",
 510         .parent         = &ck_dpll1,
 511         .flags          = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
 512         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 513         .enable_bit     = EN_LCDCK,
 514         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 515         .recalc         = &omap1_ckctl_recalc,
 516         .enable         = &omap1_clk_enable_generic,
 517         .disable        = &omap1_clk_disable_generic,
 518 };
 519
 520 static struct arm_idlect1_clk lcd_ck_1510 = {
 521         .clk = {
 522                 .name           = "lcd_ck",
 523                 .parent         = &ck_dpll1,
 524                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 525                                   RATE_CKCTL | CLOCK_IDLE_CONTROL,
 526                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 527                 .enable_bit     = EN_LCDCK,
 528                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 529                 .recalc         = &omap1_ckctl_recalc,
 530                 .enable         = &omap1_clk_enable_generic,
 531                 .disable        = &omap1_clk_disable_generic,
 532         },
 533         .idlect_shift   = 3,
 534 };
 535
 536 static struct clk uart1_1510 = {
 537         .name           = "uart1_ck",
 538         /* Direct from ULPD, no real parent */
 539         .parent         = &armper_ck.clk,
 540         .rate           = 12000000,
 541         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 542                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 543                           CLOCK_NO_IDLE_PARENT,
 544         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 545         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 546         .set_rate       = &omap1_set_uart_rate,
 547         .recalc         = &omap1_uart_recalc,
 548         .enable         = &omap1_clk_enable_generic,
 549         .disable        = &omap1_clk_disable_generic,
 550 };
 551
 552 static struct uart_clk uart1_16xx = {
 553         .clk    = {
 554                 .name           = "uart1_ck",
 555                 /* Direct from ULPD, no real parent */
 556                 .parent         = &armper_ck.clk,
 557                 .rate           = 48000000,
 558                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 559                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 560                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 561                 .enable_bit     = 29,
 562                 .enable         = &omap1_clk_enable_uart_functional,
 563                 .disable        = &omap1_clk_disable_uart_functional,
 564         },
 565         .sysc_addr      = 0xfffb0054,
 566 };
 567
 568 static struct clk uart2_ck = {
 569         .name           = "uart2_ck",
 570         /* Direct from ULPD, no real parent */
 571         .parent         = &armper_ck.clk,
 572         .rate           = 12000000,
 573         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 574                           CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
 575                           ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
 576         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 577         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 578         .set_rate       = &omap1_set_uart_rate,
 579         .recalc         = &omap1_uart_recalc,
 580         .enable         = &omap1_clk_enable_generic,
 581         .disable        = &omap1_clk_disable_generic,
 582 };
 583
 584 static struct clk uart3_1510 = {
 585         .name           = "uart3_ck",
 586         /* Direct from ULPD, no real parent */
 587         .parent         = &armper_ck.clk,
 588         .rate           = 12000000,
 589         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 590                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 591                           CLOCK_NO_IDLE_PARENT,
 592         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 593         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 594         .set_rate       = &omap1_set_uart_rate,
 595         .recalc         = &omap1_uart_recalc,
 596         .enable         = &omap1_clk_enable_generic,
 597         .disable        = &omap1_clk_disable_generic,
 598 };
 599
 600 static struct uart_clk uart3_16xx = {
 601         .clk    = {
 602                 .name           = "uart3_ck",
 603                 /* Direct from ULPD, no real parent */
 604                 .parent         = &armper_ck.clk,
 605                 .rate           = 48000000,
 606                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 607                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 608                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 609                 .enable_bit     = 31,
 610                 .enable         = &omap1_clk_enable_uart_functional,
 611                 .disable        = &omap1_clk_disable_uart_functional,
 612         },
 613         .sysc_addr      = 0xfffb9854,
 614 };
 615
 616 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 617         .name           = "usb_clko",
 618         /* Direct from ULPD, no parent */
 619         .rate           = 6000000,
 620         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 621                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
 622         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 623         .enable_bit     = USB_MCLK_EN_BIT,
 624         .enable         = &omap1_clk_enable_generic,
 625         .disable        = &omap1_clk_disable_generic,
 626 };
 627
 628 static struct clk usb_hhc_ck1510 = {
 629         .name           = "usb_hhc_ck",
 630         /* Direct from ULPD, no parent */
 631         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 632         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 633                           RATE_FIXED | ENABLE_REG_32BIT,
 634         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 635         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 636         .enable         = &omap1_clk_enable_generic,
 637         .disable        = &omap1_clk_disable_generic,
 638 };
 639
 640 static struct clk usb_hhc_ck16xx = {
 641         .name           = "usb_hhc_ck",
 642         /* Direct from ULPD, no parent */
 643         .rate           = 48000000,
 644         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 645         .flags          = CLOCK_IN_OMAP16XX |
 646                           RATE_FIXED | ENABLE_REG_32BIT,
 647         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 648         .enable_bit     = 8 /* UHOST_EN */,
 649         .enable         = &omap1_clk_enable_generic,
 650         .disable        = &omap1_clk_disable_generic,
 651 };
 652
 653 static struct clk usb_dc_ck = {
 654         .name           = "usb_dc_ck",
 655         /* Direct from ULPD, no parent */
 656         .rate           = 48000000,
 657         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED,
 658         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 659         .enable_bit     = 4,
 660         .enable         = &omap1_clk_enable_generic,
 661         .disable        = &omap1_clk_disable_generic,
 662 };
 663
 664 static struct clk mclk_1510 = {
 665         .name           = "mclk",
 666         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 667         .rate           = 12000000,
 668         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 669         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 670         .enable_bit     = 6,
 671         .enable         = &omap1_clk_enable_generic,
 672         .disable        = &omap1_clk_disable_generic,
 673 };
 674
 675 static struct clk mclk_16xx = {
 676         .name           = "mclk",
 677         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 678         .flags          = CLOCK_IN_OMAP16XX,
 679         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 680         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 681         .set_rate       = &omap1_set_ext_clk_rate,
 682         .round_rate     = &omap1_round_ext_clk_rate,
 683         .init           = &omap1_init_ext_clk,
 684         .enable         = &omap1_clk_enable_generic,
 685         .disable        = &omap1_clk_disable_generic,
 686 };
 687
 688 static struct clk bclk_1510 = {
 689         .name           = "bclk",
 690         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 691         .rate           = 12000000,
 692         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 693         .enable         = &omap1_clk_enable_generic,
 694         .disable        = &omap1_clk_disable_generic,
 695 };
 696
 697 static struct clk bclk_16xx = {
 698         .name           = "bclk",
 699         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 700         .flags          = CLOCK_IN_OMAP16XX,
 701         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 702         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 703         .set_rate       = &omap1_set_ext_clk_rate,
 704         .round_rate     = &omap1_round_ext_clk_rate,
 705         .init           = &omap1_init_ext_clk,
 706         .enable         = &omap1_clk_enable_generic,
 707         .disable        = &omap1_clk_disable_generic,
 708 };
 709
 710 static struct clk mmc1_ck = {
 711         .name           = "mmc_ck",
 712         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 713         .parent         = &armper_ck.clk,
 714         .rate           = 48000000,
 715         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 716                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
 717                           CLOCK_NO_IDLE_PARENT,
 718         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 719         .enable_bit     = 23,
 720         .enable         = &omap1_clk_enable_generic,
 721         .disable        = &omap1_clk_disable_generic,
 722 };
 723
 724 static struct clk mmc2_ck = {
 725         .name           = "mmc_ck",
 726         .id             = 1,
 727         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 728         .parent         = &armper_ck.clk,
 729         .rate           = 48000000,
 730         .flags          = CLOCK_IN_OMAP16XX |
 731                           RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 732         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 733         .enable_bit     = 20,
 734         .enable         = &omap1_clk_enable_generic,
 735         .disable        = &omap1_clk_disable_generic,
 736 };
 737
 738 static struct clk virtual_ck_mpu = {
 739         .name           = "mpu",
 740         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 741                           CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,
 742         .parent         = &arm_ck, /* Is smarter alias for */
 743         .recalc         = &followparent_recalc,
 744         .set_rate       = &omap1_select_table_rate,
 745         .round_rate     = &omap1_round_to_table_rate,
 746         .enable         = &omap1_clk_enable_generic,
 747         .disable        = &omap1_clk_disable_generic,
 748 };
 749
 750 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 751 remains active during MPU idle whenever this is enabled */
 752 static struct clk i2c_fck = {
 753         .name           = "i2c_fck",
 754         .id             = 1,
 755         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 756                           VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
 757                           ALWAYS_ENABLED,
 758         .parent         = &armxor_ck.clk,
 759         .recalc         = &followparent_recalc,
 760         .enable         = &omap1_clk_enable_generic,
 761         .disable        = &omap1_clk_disable_generic,
 762 };
 763
 764 static struct clk i2c_ick = {
 765         .name           = "i2c_ick",
 766         .id             = 1,
 767         .flags          = CLOCK_IN_OMAP16XX |
 768                           VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
 769                           ALWAYS_ENABLED,
 770         .parent         = &armper_ck.clk,
 771         .recalc         = &followparent_recalc,
 772         .enable         = &omap1_clk_enable_generic,
 773         .disable        = &omap1_clk_disable_generic,
 774 };
 775
 776 static struct clk * onchip_clks[] = {
 777         /* non-ULPD clocks */
 778         &ck_ref,
 779         &ck_dpll1,
 780         /* CK_GEN1 clocks */
 781         &ck_dpll1out.clk,
 782         &sossi_ck,
 783         &arm_ck,
 784         &armper_ck.clk,
 785         &arm_gpio_ck,
 786         &armxor_ck.clk,
 787         &armtim_ck.clk,
 788         &armwdt_ck.clk,
 789         &arminth_ck1510,  &arminth_ck16xx,
 790         /* CK_GEN2 clocks */
 791         &dsp_ck,
 792         &dspmmu_ck,
 793         &dspper_ck,
 794         &dspxor_ck,
 795         &dsptim_ck,
 796         /* CK_GEN3 clocks */
 797         &tc_ck.clk,
 798         &tipb_ck,
 799         &l3_ocpi_ck,
 800         &tc1_ck,
 801         &tc2_ck,
 802         &dma_ck,
 803         &dma_lcdfree_ck,
 804         &api_ck.clk,
 805         &lb_ck.clk,
 806         &rhea1_ck,
 807         &rhea2_ck,
 808         &lcd_ck_16xx,
 809         &lcd_ck_1510.clk,
 810         /* ULPD clocks */
 811         &uart1_1510,
 812         &uart1_16xx.clk,
 813         &uart2_ck,
 814         &uart3_1510,
 815         &uart3_16xx.clk,
 816         &usb_clko,
 817         &usb_hhc_ck1510, &usb_hhc_ck16xx,
 818         &usb_dc_ck,
 819         &mclk_1510,  &mclk_16xx,
 820         &bclk_1510,  &bclk_16xx,
 821         &mmc1_ck,
 822         &mmc2_ck,
 823         /* Virtual clocks */
 824         &virtual_ck_mpu,
 825         &i2c_fck,
 826         &i2c_ick,
 827 };
 828
 829 #endif