2 * linux/arch/arm/mach-omap1/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
16 static int omap1_clk_enable_generic(struct clk * clk);
17 static void omap1_clk_disable_generic(struct clk * clk);
18 static void omap1_ckctl_recalc(struct clk *clk, unsigned long parent_rate,
20 static void omap1_watchdog_recalc(struct clk *clk, unsigned long parent_rate,
22 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
23 static void omap1_sossi_recalc(struct clk *clk, unsigned long parent_rate,
25 static void omap1_ckctl_recalc_dsp_domain(struct clk *clk,
26 unsigned long parent_rate,
28 static int omap1_clk_enable_dsp_domain(struct clk * clk);
29 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
30 static void omap1_clk_disable_dsp_domain(struct clk * clk);
31 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
32 static void omap1_uart_recalc(struct clk *clk, unsigned long parent_rate,
34 static int omap1_clk_enable_uart_functional(struct clk * clk);
35 static void omap1_clk_disable_uart_functional(struct clk * clk);
36 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
37 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
38 static void omap1_init_ext_clk(struct clk * clk);
39 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
40 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
41 static int omap1_clk_enable(struct clk *clk);
42 static void omap1_clk_disable(struct clk *clk);
47 unsigned long pll_rate;
54 unsigned long sysc_addr;
57 /* Provide a method for preventing idling some ARM IDLECT clocks */
58 struct arm_idlect1_clk {
60 unsigned long no_idle_count;
64 /* ARM_CKCTL bit shifts */
65 #define CKCTL_PERDIV_OFFSET 0
66 #define CKCTL_LCDDIV_OFFSET 2
67 #define CKCTL_ARMDIV_OFFSET 4
68 #define CKCTL_DSPDIV_OFFSET 6
69 #define CKCTL_TCDIV_OFFSET 8
70 #define CKCTL_DSPMMUDIV_OFFSET 10
71 /*#define ARM_TIMXO 12*/
73 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
74 /* DSP_CKCTL bit shifts */
75 #define CKCTL_DSPPERDIV_OFFSET 0
77 /* ARM_IDLECT2 bit shifts */
82 #define EN_LBCK 4 /* Not on 1610/1710 */
83 /*#define EN_HSABCK 5*/
87 #define EN_GPIOCK 9 /* Not on 1610/1710 */
88 /*#define EN_LBFREECK 10*/
89 #define EN_CKOUT_ARM 11
91 /* ARM_IDLECT3 bit shifts */
96 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
99 /* Various register defines for clock controls scattered around OMAP chip */
100 #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
101 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
102 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
103 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
104 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
105 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
106 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878
107 #define SOFT_REQ_REG 0xfffe0834
108 #define SOFT_REQ_REG2 0xfffe0880
110 /*-------------------------------------------------------------------------
111 * Omap1 MPU rate table
112 *-------------------------------------------------------------------------*/
113 static struct mpu_rate rate_table[] = {
114 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
115 * NOTE: Comment order here is different from bits in CKCTL value:
116 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
118 #if defined(CONFIG_OMAP_ARM_216MHZ)
119 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
121 #if defined(CONFIG_OMAP_ARM_195MHZ)
122 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
124 #if defined(CONFIG_OMAP_ARM_192MHZ)
125 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
126 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
127 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
128 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
129 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
131 #if defined(CONFIG_OMAP_ARM_182MHZ)
132 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
134 #if defined(CONFIG_OMAP_ARM_168MHZ)
135 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
137 #if defined(CONFIG_OMAP_ARM_150MHZ)
138 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
140 #if defined(CONFIG_OMAP_ARM_120MHZ)
141 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
143 #if defined(CONFIG_OMAP_ARM_96MHZ)
144 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
146 #if defined(CONFIG_OMAP_ARM_60MHZ)
147 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
149 #if defined(CONFIG_OMAP_ARM_30MHZ)
150 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
155 /*-------------------------------------------------------------------------
157 *-------------------------------------------------------------------------*/
159 static struct clk ck_ref = {
162 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
163 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
164 .enable = &omap1_clk_enable_generic,
165 .disable = &omap1_clk_disable_generic,
168 static struct clk ck_dpll1 = {
171 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
172 CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
173 .enable = &omap1_clk_enable_generic,
174 .disable = &omap1_clk_disable_generic,
177 static struct arm_idlect1_clk ck_dpll1out = {
179 .name = "ck_dpll1out",
181 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
182 ENABLE_REG_32BIT | RATE_PROPAGATES,
183 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
184 .enable_bit = EN_CKOUT_ARM,
185 .recalc = &followparent_recalc,
186 .enable = &omap1_clk_enable_generic,
187 .disable = &omap1_clk_disable_generic,
192 static struct clk sossi_ck = {
194 .parent = &ck_dpll1out.clk,
195 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
197 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
199 .recalc = &omap1_sossi_recalc,
200 .set_rate = &omap1_set_sossi_rate,
201 .enable = &omap1_clk_enable_generic,
202 .disable = &omap1_clk_disable_generic,
205 static struct clk arm_ck = {
208 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
209 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
211 .rate_offset = CKCTL_ARMDIV_OFFSET,
212 .recalc = &omap1_ckctl_recalc,
213 .enable = &omap1_clk_enable_generic,
214 .disable = &omap1_clk_disable_generic,
217 static struct arm_idlect1_clk armper_ck = {
221 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
222 CLOCK_IN_OMAP310 | RATE_CKCTL |
224 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
225 .enable_bit = EN_PERCK,
226 .rate_offset = CKCTL_PERDIV_OFFSET,
227 .recalc = &omap1_ckctl_recalc,
228 .enable = &omap1_clk_enable_generic,
229 .disable = &omap1_clk_disable_generic,
234 static struct clk arm_gpio_ck = {
235 .name = "arm_gpio_ck",
237 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
238 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
239 .enable_bit = EN_GPIOCK,
240 .recalc = &followparent_recalc,
241 .enable = &omap1_clk_enable_generic,
242 .disable = &omap1_clk_disable_generic,
245 static struct arm_idlect1_clk armxor_ck = {
249 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
250 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
251 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
252 .enable_bit = EN_XORPCK,
253 .recalc = &followparent_recalc,
254 .enable = &omap1_clk_enable_generic,
255 .disable = &omap1_clk_disable_generic,
260 static struct arm_idlect1_clk armtim_ck = {
264 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
265 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
266 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
267 .enable_bit = EN_TIMCK,
268 .recalc = &followparent_recalc,
269 .enable = &omap1_clk_enable_generic,
270 .disable = &omap1_clk_disable_generic,
275 static struct arm_idlect1_clk armwdt_ck = {
279 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
280 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
281 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
282 .enable_bit = EN_WDTCK,
283 .recalc = &omap1_watchdog_recalc,
284 .enable = &omap1_clk_enable_generic,
285 .disable = &omap1_clk_disable_generic,
290 static struct clk arminth_ck16xx = {
291 .name = "arminth_ck",
293 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
294 .recalc = &followparent_recalc,
295 /* Note: On 16xx the frequency can be divided by 2 by programming
296 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
298 * 1510 version is in TC clocks.
300 .enable = &omap1_clk_enable_generic,
301 .disable = &omap1_clk_disable_generic,
304 static struct clk dsp_ck = {
307 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
309 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
310 .enable_bit = EN_DSPCK,
311 .rate_offset = CKCTL_DSPDIV_OFFSET,
312 .recalc = &omap1_ckctl_recalc,
313 .enable = &omap1_clk_enable_generic,
314 .disable = &omap1_clk_disable_generic,
317 static struct clk dspmmu_ck = {
320 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
321 RATE_CKCTL | ALWAYS_ENABLED,
322 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
323 .recalc = &omap1_ckctl_recalc,
324 .enable = &omap1_clk_enable_generic,
325 .disable = &omap1_clk_disable_generic,
328 static struct clk dspper_ck = {
331 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
333 .enable_reg = IOMEM(DSP_IDLECT2),
334 .enable_bit = EN_PERCK,
335 .rate_offset = CKCTL_PERDIV_OFFSET,
336 .recalc = &omap1_ckctl_recalc_dsp_domain,
337 .set_rate = &omap1_clk_set_rate_dsp_domain,
338 .enable = &omap1_clk_enable_dsp_domain,
339 .disable = &omap1_clk_disable_dsp_domain,
342 static struct clk dspxor_ck = {
345 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
346 .enable_reg = IOMEM(DSP_IDLECT2),
347 .enable_bit = EN_XORPCK,
348 .recalc = &followparent_recalc,
349 .enable = &omap1_clk_enable_dsp_domain,
350 .disable = &omap1_clk_disable_dsp_domain,
353 static struct clk dsptim_ck = {
356 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
357 .enable_reg = IOMEM(DSP_IDLECT2),
358 .enable_bit = EN_DSPTIMCK,
359 .recalc = &followparent_recalc,
360 .enable = &omap1_clk_enable_dsp_domain,
361 .disable = &omap1_clk_disable_dsp_domain,
364 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
365 static struct arm_idlect1_clk tc_ck = {
369 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
370 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
371 RATE_CKCTL | RATE_PROPAGATES |
372 ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
373 .rate_offset = CKCTL_TCDIV_OFFSET,
374 .recalc = &omap1_ckctl_recalc,
375 .enable = &omap1_clk_enable_generic,
376 .disable = &omap1_clk_disable_generic,
381 static struct clk arminth_ck1510 = {
382 .name = "arminth_ck",
383 .parent = &tc_ck.clk,
384 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
386 .recalc = &followparent_recalc,
387 /* Note: On 1510 the frequency follows TC_CK
389 * 16xx version is in MPU clocks.
391 .enable = &omap1_clk_enable_generic,
392 .disable = &omap1_clk_disable_generic,
395 static struct clk tipb_ck = {
396 /* No-idle controlled by "tc_ck" */
398 .parent = &tc_ck.clk,
399 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
401 .recalc = &followparent_recalc,
402 .enable = &omap1_clk_enable_generic,
403 .disable = &omap1_clk_disable_generic,
406 static struct clk l3_ocpi_ck = {
407 /* No-idle controlled by "tc_ck" */
408 .name = "l3_ocpi_ck",
409 .parent = &tc_ck.clk,
410 .flags = CLOCK_IN_OMAP16XX,
411 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
412 .enable_bit = EN_OCPI_CK,
413 .recalc = &followparent_recalc,
414 .enable = &omap1_clk_enable_generic,
415 .disable = &omap1_clk_disable_generic,
418 static struct clk tc1_ck = {
420 .parent = &tc_ck.clk,
421 .flags = CLOCK_IN_OMAP16XX,
422 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
423 .enable_bit = EN_TC1_CK,
424 .recalc = &followparent_recalc,
425 .enable = &omap1_clk_enable_generic,
426 .disable = &omap1_clk_disable_generic,
429 static struct clk tc2_ck = {
431 .parent = &tc_ck.clk,
432 .flags = CLOCK_IN_OMAP16XX,
433 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
434 .enable_bit = EN_TC2_CK,
435 .recalc = &followparent_recalc,
436 .enable = &omap1_clk_enable_generic,
437 .disable = &omap1_clk_disable_generic,
440 static struct clk dma_ck = {
441 /* No-idle controlled by "tc_ck" */
443 .parent = &tc_ck.clk,
444 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
445 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
446 .recalc = &followparent_recalc,
447 .enable = &omap1_clk_enable_generic,
448 .disable = &omap1_clk_disable_generic,
451 static struct clk dma_lcdfree_ck = {
452 .name = "dma_lcdfree_ck",
453 .parent = &tc_ck.clk,
454 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
455 .recalc = &followparent_recalc,
456 .enable = &omap1_clk_enable_generic,
457 .disable = &omap1_clk_disable_generic,
460 static struct arm_idlect1_clk api_ck = {
463 .parent = &tc_ck.clk,
464 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
465 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
466 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
467 .enable_bit = EN_APICK,
468 .recalc = &followparent_recalc,
469 .enable = &omap1_clk_enable_generic,
470 .disable = &omap1_clk_disable_generic,
475 static struct arm_idlect1_clk lb_ck = {
478 .parent = &tc_ck.clk,
479 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
481 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
482 .enable_bit = EN_LBCK,
483 .recalc = &followparent_recalc,
484 .enable = &omap1_clk_enable_generic,
485 .disable = &omap1_clk_disable_generic,
490 static struct clk rhea1_ck = {
492 .parent = &tc_ck.clk,
493 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
494 .recalc = &followparent_recalc,
495 .enable = &omap1_clk_enable_generic,
496 .disable = &omap1_clk_disable_generic,
499 static struct clk rhea2_ck = {
501 .parent = &tc_ck.clk,
502 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
503 .recalc = &followparent_recalc,
504 .enable = &omap1_clk_enable_generic,
505 .disable = &omap1_clk_disable_generic,
508 static struct clk lcd_ck_16xx = {
511 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
512 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
513 .enable_bit = EN_LCDCK,
514 .rate_offset = CKCTL_LCDDIV_OFFSET,
515 .recalc = &omap1_ckctl_recalc,
516 .enable = &omap1_clk_enable_generic,
517 .disable = &omap1_clk_disable_generic,
520 static struct arm_idlect1_clk lcd_ck_1510 = {
524 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
525 RATE_CKCTL | CLOCK_IDLE_CONTROL,
526 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
527 .enable_bit = EN_LCDCK,
528 .rate_offset = CKCTL_LCDDIV_OFFSET,
529 .recalc = &omap1_ckctl_recalc,
530 .enable = &omap1_clk_enable_generic,
531 .disable = &omap1_clk_disable_generic,
536 static struct clk uart1_1510 = {
538 /* Direct from ULPD, no real parent */
539 .parent = &armper_ck.clk,
541 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
542 ENABLE_REG_32BIT | ALWAYS_ENABLED |
543 CLOCK_NO_IDLE_PARENT,
544 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
545 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
546 .set_rate = &omap1_set_uart_rate,
547 .recalc = &omap1_uart_recalc,
548 .enable = &omap1_clk_enable_generic,
549 .disable = &omap1_clk_disable_generic,
552 static struct uart_clk uart1_16xx = {
555 /* Direct from ULPD, no real parent */
556 .parent = &armper_ck.clk,
558 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
559 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
560 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
562 .enable = &omap1_clk_enable_uart_functional,
563 .disable = &omap1_clk_disable_uart_functional,
565 .sysc_addr = 0xfffb0054,
568 static struct clk uart2_ck = {
570 /* Direct from ULPD, no real parent */
571 .parent = &armper_ck.clk,
573 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
574 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
575 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
576 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
577 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
578 .set_rate = &omap1_set_uart_rate,
579 .recalc = &omap1_uart_recalc,
580 .enable = &omap1_clk_enable_generic,
581 .disable = &omap1_clk_disable_generic,
584 static struct clk uart3_1510 = {
586 /* Direct from ULPD, no real parent */
587 .parent = &armper_ck.clk,
589 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
590 ENABLE_REG_32BIT | ALWAYS_ENABLED |
591 CLOCK_NO_IDLE_PARENT,
592 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
593 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
594 .set_rate = &omap1_set_uart_rate,
595 .recalc = &omap1_uart_recalc,
596 .enable = &omap1_clk_enable_generic,
597 .disable = &omap1_clk_disable_generic,
600 static struct uart_clk uart3_16xx = {
603 /* Direct from ULPD, no real parent */
604 .parent = &armper_ck.clk,
606 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
607 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
608 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
610 .enable = &omap1_clk_enable_uart_functional,
611 .disable = &omap1_clk_disable_uart_functional,
613 .sysc_addr = 0xfffb9854,
616 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
618 /* Direct from ULPD, no parent */
620 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
621 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
622 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
623 .enable_bit = USB_MCLK_EN_BIT,
624 .enable = &omap1_clk_enable_generic,
625 .disable = &omap1_clk_disable_generic,
628 static struct clk usb_hhc_ck1510 = {
629 .name = "usb_hhc_ck",
630 /* Direct from ULPD, no parent */
631 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
632 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
633 RATE_FIXED | ENABLE_REG_32BIT,
634 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
635 .enable_bit = USB_HOST_HHC_UHOST_EN,
636 .enable = &omap1_clk_enable_generic,
637 .disable = &omap1_clk_disable_generic,
640 static struct clk usb_hhc_ck16xx = {
641 .name = "usb_hhc_ck",
642 /* Direct from ULPD, no parent */
644 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
645 .flags = CLOCK_IN_OMAP16XX |
646 RATE_FIXED | ENABLE_REG_32BIT,
647 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
648 .enable_bit = 8 /* UHOST_EN */,
649 .enable = &omap1_clk_enable_generic,
650 .disable = &omap1_clk_disable_generic,
653 static struct clk usb_dc_ck = {
655 /* Direct from ULPD, no parent */
657 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
658 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
660 .enable = &omap1_clk_enable_generic,
661 .disable = &omap1_clk_disable_generic,
664 static struct clk mclk_1510 = {
666 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
668 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
669 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
671 .enable = &omap1_clk_enable_generic,
672 .disable = &omap1_clk_disable_generic,
675 static struct clk mclk_16xx = {
677 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
678 .flags = CLOCK_IN_OMAP16XX,
679 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
680 .enable_bit = COM_ULPD_PLL_CLK_REQ,
681 .set_rate = &omap1_set_ext_clk_rate,
682 .round_rate = &omap1_round_ext_clk_rate,
683 .init = &omap1_init_ext_clk,
684 .enable = &omap1_clk_enable_generic,
685 .disable = &omap1_clk_disable_generic,
688 static struct clk bclk_1510 = {
690 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
692 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
693 .enable = &omap1_clk_enable_generic,
694 .disable = &omap1_clk_disable_generic,
697 static struct clk bclk_16xx = {
699 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
700 .flags = CLOCK_IN_OMAP16XX,
701 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
702 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
703 .set_rate = &omap1_set_ext_clk_rate,
704 .round_rate = &omap1_round_ext_clk_rate,
705 .init = &omap1_init_ext_clk,
706 .enable = &omap1_clk_enable_generic,
707 .disable = &omap1_clk_disable_generic,
710 static struct clk mmc1_ck = {
712 /* Functional clock is direct from ULPD, interface clock is ARMPER */
713 .parent = &armper_ck.clk,
715 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
716 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
717 CLOCK_NO_IDLE_PARENT,
718 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
720 .enable = &omap1_clk_enable_generic,
721 .disable = &omap1_clk_disable_generic,
724 static struct clk mmc2_ck = {
727 /* Functional clock is direct from ULPD, interface clock is ARMPER */
728 .parent = &armper_ck.clk,
730 .flags = CLOCK_IN_OMAP16XX |
731 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
732 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
734 .enable = &omap1_clk_enable_generic,
735 .disable = &omap1_clk_disable_generic,
738 static struct clk virtual_ck_mpu = {
740 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
741 CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,
742 .parent = &arm_ck, /* Is smarter alias for */
743 .recalc = &followparent_recalc,
744 .set_rate = &omap1_select_table_rate,
745 .round_rate = &omap1_round_to_table_rate,
746 .enable = &omap1_clk_enable_generic,
747 .disable = &omap1_clk_disable_generic,
750 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
751 remains active during MPU idle whenever this is enabled */
752 static struct clk i2c_fck = {
755 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
756 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
758 .parent = &armxor_ck.clk,
759 .recalc = &followparent_recalc,
760 .enable = &omap1_clk_enable_generic,
761 .disable = &omap1_clk_disable_generic,
764 static struct clk i2c_ick = {
767 .flags = CLOCK_IN_OMAP16XX |
768 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
770 .parent = &armper_ck.clk,
771 .recalc = &followparent_recalc,
772 .enable = &omap1_clk_enable_generic,
773 .disable = &omap1_clk_disable_generic,
776 static struct clk * onchip_clks[] = {
777 /* non-ULPD clocks */
789 &arminth_ck1510, &arminth_ck16xx,
817 &usb_hhc_ck1510, &usb_hhc_ck16xx,
819 &mclk_1510, &mclk_16xx,
820 &bclk_1510, &bclk_16xx,