arch/arm/mach-omap1/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static int omap1_clk_enable_generic(struct clk * clk);
  17 static void omap1_clk_disable_generic(struct clk * clk);
  18 static void omap1_ckctl_recalc(struct clk *clk, unsigned long parent_rate,
  19                                u8 rate_storage);
  20 static void omap1_watchdog_recalc(struct clk *clk, unsigned long parent_rate,
  21                                   u8 rate_storage);
  22 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
  23 static void omap1_sossi_recalc(struct clk *clk, unsigned long parent_rate,
  24                                u8 rate_storage);
  25 static void omap1_ckctl_recalc_dsp_domain(struct clk *clk,
  26                                           unsigned long parent_rate,
  27                                           u8 rate_storage);
  28 static int omap1_clk_enable_dsp_domain(struct clk * clk);
  29 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  30 static void omap1_clk_disable_dsp_domain(struct clk * clk);
  31 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  32 static void omap1_uart_recalc(struct clk *clk, unsigned long parent_rate,
  33                               u8 rate_storage);
  34 static int omap1_clk_enable_uart_functional(struct clk * clk);
  35 static void omap1_clk_disable_uart_functional(struct clk * clk);
  36 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  37 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  38 static void omap1_init_ext_clk(struct clk * clk);
  39 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  40 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  41 static int omap1_clk_enable(struct clk *clk);
  42 static void omap1_clk_disable(struct clk *clk);
  43
  44 struct mpu_rate {
  45         unsigned long           rate;
  46         unsigned long           xtal;
  47         unsigned long           pll_rate;
  48         __u16                   ckctl_val;
  49         __u16                   dpllctl_val;
  50 };
  51
  52 struct uart_clk {
  53         struct clk      clk;
  54         unsigned long   sysc_addr;
  55 };
  56
  57 /* Provide a method for preventing idling some ARM IDLECT clocks */
  58 struct arm_idlect1_clk {
  59         struct clk      clk;
  60         unsigned long   no_idle_count;
  61         __u8            idlect_shift;
  62 };
  63
  64 /* ARM_CKCTL bit shifts */
  65 #define CKCTL_PERDIV_OFFSET     0
  66 #define CKCTL_LCDDIV_OFFSET     2
  67 #define CKCTL_ARMDIV_OFFSET     4
  68 #define CKCTL_DSPDIV_OFFSET     6
  69 #define CKCTL_TCDIV_OFFSET      8
  70 #define CKCTL_DSPMMUDIV_OFFSET  10
  71 /*#define ARM_TIMXO             12*/
  72 #define EN_DSPCK                13
  73 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  74 /* DSP_CKCTL bit shifts */
  75 #define CKCTL_DSPPERDIV_OFFSET  0
  76
  77 /* ARM_IDLECT2 bit shifts */
  78 #define EN_WDTCK        0
  79 #define EN_XORPCK       1
  80 #define EN_PERCK        2
  81 #define EN_LCDCK        3
  82 #define EN_LBCK         4 /* Not on 1610/1710 */
  83 /*#define EN_HSABCK     5*/
  84 #define EN_APICK        6
  85 #define EN_TIMCK        7
  86 #define DMACK_REQ       8
  87 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  88 /*#define EN_LBFREECK   10*/
  89 #define EN_CKOUT_ARM    11
  90
  91 /* ARM_IDLECT3 bit shifts */
  92 #define EN_OCPI_CK      0
  93 #define EN_TC1_CK       2
  94 #define EN_TC2_CK       4
  95
  96 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  97 #define EN_DSPTIMCK     5
  98
  99 /* Various register defines for clock controls scattered around OMAP chip */
 100 #define SDW_MCLK_INV_BIT        2       /* In ULPD_CLKC_CTRL */
 101 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
 102 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
 103 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
 104 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
 105 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
 106 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
 107 #define SOFT_REQ_REG            0xfffe0834
 108 #define SOFT_REQ_REG2           0xfffe0880
 109
 110 /*-------------------------------------------------------------------------
 111  * Omap1 MPU rate table
 112  *-------------------------------------------------------------------------*/
 113 static struct mpu_rate rate_table[] = {
 114         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 115          * NOTE: Comment order here is different from bits in CKCTL value:
 116          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 117          */
 118 #if defined(CONFIG_OMAP_ARM_216MHZ)
 119         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 120 #endif
 121 #if defined(CONFIG_OMAP_ARM_195MHZ)
 122         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 123 #endif
 124 #if defined(CONFIG_OMAP_ARM_192MHZ)
 125         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 126         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 127         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 128         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 129         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 130 #endif
 131 #if defined(CONFIG_OMAP_ARM_182MHZ)
 132         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 133 #endif
 134 #if defined(CONFIG_OMAP_ARM_168MHZ)
 135         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 136 #endif
 137 #if defined(CONFIG_OMAP_ARM_150MHZ)
 138         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 139 #endif
 140 #if defined(CONFIG_OMAP_ARM_120MHZ)
 141         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 142 #endif
 143 #if defined(CONFIG_OMAP_ARM_96MHZ)
 144         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 145 #endif
 146 #if defined(CONFIG_OMAP_ARM_60MHZ)
 147         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 148 #endif
 149 #if defined(CONFIG_OMAP_ARM_30MHZ)
 150         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 151 #endif
 152         { 0, 0, 0, 0, 0 },
 153 };
 154
 155 /*-------------------------------------------------------------------------
 156  * Omap1 clocks
 157  *-------------------------------------------------------------------------*/
 158
 159 static struct clk ck_ref = {
 160         .name           = "ck_ref",
 161         .rate           = 12000000,
 162         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 163                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 164         .enable         = &omap1_clk_enable_generic,
 165         .disable        = &omap1_clk_disable_generic,
 166 };
 167
 168 static struct clk ck_dpll1 = {
 169         .name           = "ck_dpll1",
 170         .parent         = &ck_ref,
 171         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 172                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 173         .enable         = &omap1_clk_enable_generic,
 174         .disable        = &omap1_clk_disable_generic,
 175 };
 176
 177 static struct arm_idlect1_clk ck_dpll1out = {
 178         .clk = {
 179                 .name           = "ck_dpll1out",
 180                 .parent         = &ck_dpll1,
 181                 .flags          = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
 182                                   ENABLE_REG_32BIT,
 183                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 184                 .enable_bit     = EN_CKOUT_ARM,
 185                 .recalc         = &followparent_recalc,
 186                 .enable         = &omap1_clk_enable_generic,
 187                 .disable        = &omap1_clk_disable_generic,
 188         },
 189         .idlect_shift   = 12,
 190 };
 191
 192 static struct clk sossi_ck = {
 193         .name           = "ck_sossi",
 194         .parent         = &ck_dpll1out.clk,
 195         .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
 196                           ENABLE_REG_32BIT,
 197         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
 198         .enable_bit     = 16,
 199         .recalc         = &omap1_sossi_recalc,
 200         .set_rate       = &omap1_set_sossi_rate,
 201         .enable         = &omap1_clk_enable_generic,
 202         .disable        = &omap1_clk_disable_generic,
 203 };
 204
 205 static struct clk arm_ck = {
 206         .name           = "arm_ck",
 207         .parent         = &ck_dpll1,
 208         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 209                           CLOCK_IN_OMAP310 | RATE_CKCTL | ALWAYS_ENABLED,
 210         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 211         .recalc         = &omap1_ckctl_recalc,
 212         .enable         = &omap1_clk_enable_generic,
 213         .disable        = &omap1_clk_disable_generic,
 214 };
 215
 216 static struct arm_idlect1_clk armper_ck = {
 217         .clk = {
 218                 .name           = "armper_ck",
 219                 .parent         = &ck_dpll1,
 220                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 221                                   CLOCK_IN_OMAP310 | RATE_CKCTL |
 222                                   CLOCK_IDLE_CONTROL,
 223                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 224                 .enable_bit     = EN_PERCK,
 225                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 226                 .recalc         = &omap1_ckctl_recalc,
 227                 .enable         = &omap1_clk_enable_generic,
 228                 .disable        = &omap1_clk_disable_generic,
 229         },
 230         .idlect_shift   = 2,
 231 };
 232
 233 static struct clk arm_gpio_ck = {
 234         .name           = "arm_gpio_ck",
 235         .parent         = &ck_dpll1,
 236         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 237         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 238         .enable_bit     = EN_GPIOCK,
 239         .recalc         = &followparent_recalc,
 240         .enable         = &omap1_clk_enable_generic,
 241         .disable        = &omap1_clk_disable_generic,
 242 };
 243
 244 static struct arm_idlect1_clk armxor_ck = {
 245         .clk = {
 246                 .name           = "armxor_ck",
 247                 .parent         = &ck_ref,
 248                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 249                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 250                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 251                 .enable_bit     = EN_XORPCK,
 252                 .recalc         = &followparent_recalc,
 253                 .enable         = &omap1_clk_enable_generic,
 254                 .disable        = &omap1_clk_disable_generic,
 255         },
 256         .idlect_shift   = 1,
 257 };
 258
 259 static struct arm_idlect1_clk armtim_ck = {
 260         .clk = {
 261                 .name           = "armtim_ck",
 262                 .parent         = &ck_ref,
 263                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 264                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 265                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 266                 .enable_bit     = EN_TIMCK,
 267                 .recalc         = &followparent_recalc,
 268                 .enable         = &omap1_clk_enable_generic,
 269                 .disable        = &omap1_clk_disable_generic,
 270         },
 271         .idlect_shift   = 9,
 272 };
 273
 274 static struct arm_idlect1_clk armwdt_ck = {
 275         .clk = {
 276                 .name           = "armwdt_ck",
 277                 .parent         = &ck_ref,
 278                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 279                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 280                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 281                 .enable_bit     = EN_WDTCK,
 282                 .recalc         = &omap1_watchdog_recalc,
 283                 .enable         = &omap1_clk_enable_generic,
 284                 .disable        = &omap1_clk_disable_generic,
 285         },
 286         .idlect_shift   = 0,
 287 };
 288
 289 static struct clk arminth_ck16xx = {
 290         .name           = "arminth_ck",
 291         .parent         = &arm_ck,
 292         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 293         .recalc         = &followparent_recalc,
 294         /* Note: On 16xx the frequency can be divided by 2 by programming
 295          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 296          *
 297          * 1510 version is in TC clocks.
 298          */
 299         .enable         = &omap1_clk_enable_generic,
 300         .disable        = &omap1_clk_disable_generic,
 301 };
 302
 303 static struct clk dsp_ck = {
 304         .name           = "dsp_ck",
 305         .parent         = &ck_dpll1,
 306         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 307                           RATE_CKCTL,
 308         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 309         .enable_bit     = EN_DSPCK,
 310         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 311         .recalc         = &omap1_ckctl_recalc,
 312         .enable         = &omap1_clk_enable_generic,
 313         .disable        = &omap1_clk_disable_generic,
 314 };
 315
 316 static struct clk dspmmu_ck = {
 317         .name           = "dspmmu_ck",
 318         .parent         = &ck_dpll1,
 319         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 320                           RATE_CKCTL | ALWAYS_ENABLED,
 321         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 322         .recalc         = &omap1_ckctl_recalc,
 323         .enable         = &omap1_clk_enable_generic,
 324         .disable        = &omap1_clk_disable_generic,
 325 };
 326
 327 static struct clk dspper_ck = {
 328         .name           = "dspper_ck",
 329         .parent         = &ck_dpll1,
 330         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 331                           RATE_CKCTL,
 332         .enable_reg     = IOMEM(DSP_IDLECT2),
 333         .enable_bit     = EN_PERCK,
 334         .rate_offset    = CKCTL_PERDIV_OFFSET,
 335         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 336         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 337         .enable         = &omap1_clk_enable_dsp_domain,
 338         .disable        = &omap1_clk_disable_dsp_domain,
 339 };
 340
 341 static struct clk dspxor_ck = {
 342         .name           = "dspxor_ck",
 343         .parent         = &ck_ref,
 344         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 345         .enable_reg     = IOMEM(DSP_IDLECT2),
 346         .enable_bit     = EN_XORPCK,
 347         .recalc         = &followparent_recalc,
 348         .enable         = &omap1_clk_enable_dsp_domain,
 349         .disable        = &omap1_clk_disable_dsp_domain,
 350 };
 351
 352 static struct clk dsptim_ck = {
 353         .name           = "dsptim_ck",
 354         .parent         = &ck_ref,
 355         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 356         .enable_reg     = IOMEM(DSP_IDLECT2),
 357         .enable_bit     = EN_DSPTIMCK,
 358         .recalc         = &followparent_recalc,
 359         .enable         = &omap1_clk_enable_dsp_domain,
 360         .disable        = &omap1_clk_disable_dsp_domain,
 361 };
 362
 363 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 364 static struct arm_idlect1_clk tc_ck = {
 365         .clk = {
 366                 .name           = "tc_ck",
 367                 .parent         = &ck_dpll1,
 368                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 369                                   CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
 370                                   RATE_CKCTL |
 371                                   ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
 372                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 373                 .recalc         = &omap1_ckctl_recalc,
 374                 .enable         = &omap1_clk_enable_generic,
 375                 .disable        = &omap1_clk_disable_generic,
 376         },
 377         .idlect_shift   = 6,
 378 };
 379
 380 static struct clk arminth_ck1510 = {
 381         .name           = "arminth_ck",
 382         .parent         = &tc_ck.clk,
 383         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 384                           ALWAYS_ENABLED,
 385         .recalc         = &followparent_recalc,
 386         /* Note: On 1510 the frequency follows TC_CK
 387          *
 388          * 16xx version is in MPU clocks.
 389          */
 390         .enable         = &omap1_clk_enable_generic,
 391         .disable        = &omap1_clk_disable_generic,
 392 };
 393
 394 static struct clk tipb_ck = {
 395         /* No-idle controlled by "tc_ck" */
 396         .name           = "tipb_ck",
 397         .parent         = &tc_ck.clk,
 398         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 399                           ALWAYS_ENABLED,
 400         .recalc         = &followparent_recalc,
 401         .enable         = &omap1_clk_enable_generic,
 402         .disable        = &omap1_clk_disable_generic,
 403 };
 404
 405 static struct clk l3_ocpi_ck = {
 406         /* No-idle controlled by "tc_ck" */
 407         .name           = "l3_ocpi_ck",
 408         .parent         = &tc_ck.clk,
 409         .flags          = CLOCK_IN_OMAP16XX,
 410         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 411         .enable_bit     = EN_OCPI_CK,
 412         .recalc         = &followparent_recalc,
 413         .enable         = &omap1_clk_enable_generic,
 414         .disable        = &omap1_clk_disable_generic,
 415 };
 416
 417 static struct clk tc1_ck = {
 418         .name           = "tc1_ck",
 419         .parent         = &tc_ck.clk,
 420         .flags          = CLOCK_IN_OMAP16XX,
 421         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 422         .enable_bit     = EN_TC1_CK,
 423         .recalc         = &followparent_recalc,
 424         .enable         = &omap1_clk_enable_generic,
 425         .disable        = &omap1_clk_disable_generic,
 426 };
 427
 428 static struct clk tc2_ck = {
 429         .name           = "tc2_ck",
 430         .parent         = &tc_ck.clk,
 431         .flags          = CLOCK_IN_OMAP16XX,
 432         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 433         .enable_bit     = EN_TC2_CK,
 434         .recalc         = &followparent_recalc,
 435         .enable         = &omap1_clk_enable_generic,
 436         .disable        = &omap1_clk_disable_generic,
 437 };
 438
 439 static struct clk dma_ck = {
 440         /* No-idle controlled by "tc_ck" */
 441         .name           = "dma_ck",
 442         .parent         = &tc_ck.clk,
 443         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 444                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 445         .recalc         = &followparent_recalc,
 446         .enable         = &omap1_clk_enable_generic,
 447         .disable        = &omap1_clk_disable_generic,
 448 };
 449
 450 static struct clk dma_lcdfree_ck = {
 451         .name           = "dma_lcdfree_ck",
 452         .parent         = &tc_ck.clk,
 453         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 454         .recalc         = &followparent_recalc,
 455         .enable         = &omap1_clk_enable_generic,
 456         .disable        = &omap1_clk_disable_generic,
 457 };
 458
 459 static struct arm_idlect1_clk api_ck = {
 460         .clk = {
 461                 .name           = "api_ck",
 462                 .parent         = &tc_ck.clk,
 463                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 464                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 465                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 466                 .enable_bit     = EN_APICK,
 467                 .recalc         = &followparent_recalc,
 468                 .enable         = &omap1_clk_enable_generic,
 469                 .disable        = &omap1_clk_disable_generic,
 470         },
 471         .idlect_shift   = 8,
 472 };
 473
 474 static struct arm_idlect1_clk lb_ck = {
 475         .clk = {
 476                 .name           = "lb_ck",
 477                 .parent         = &tc_ck.clk,
 478                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 479                                   CLOCK_IDLE_CONTROL,
 480                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 481                 .enable_bit     = EN_LBCK,
 482                 .recalc         = &followparent_recalc,
 483                 .enable         = &omap1_clk_enable_generic,
 484                 .disable        = &omap1_clk_disable_generic,
 485         },
 486         .idlect_shift   = 4,
 487 };
 488
 489 static struct clk rhea1_ck = {
 490         .name           = "rhea1_ck",
 491         .parent         = &tc_ck.clk,
 492         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 493         .recalc         = &followparent_recalc,
 494         .enable         = &omap1_clk_enable_generic,
 495         .disable        = &omap1_clk_disable_generic,
 496 };
 497
 498 static struct clk rhea2_ck = {
 499         .name           = "rhea2_ck",
 500         .parent         = &tc_ck.clk,
 501         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 502         .recalc         = &followparent_recalc,
 503         .enable         = &omap1_clk_enable_generic,
 504         .disable        = &omap1_clk_disable_generic,
 505 };
 506
 507 static struct clk lcd_ck_16xx = {
 508         .name           = "lcd_ck",
 509         .parent         = &ck_dpll1,
 510         .flags          = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
 511         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 512         .enable_bit     = EN_LCDCK,
 513         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 514         .recalc         = &omap1_ckctl_recalc,
 515         .enable         = &omap1_clk_enable_generic,
 516         .disable        = &omap1_clk_disable_generic,
 517 };
 518
 519 static struct arm_idlect1_clk lcd_ck_1510 = {
 520         .clk = {
 521                 .name           = "lcd_ck",
 522                 .parent         = &ck_dpll1,
 523                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 524                                   RATE_CKCTL | CLOCK_IDLE_CONTROL,
 525                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 526                 .enable_bit     = EN_LCDCK,
 527                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 528                 .recalc         = &omap1_ckctl_recalc,
 529                 .enable         = &omap1_clk_enable_generic,
 530                 .disable        = &omap1_clk_disable_generic,
 531         },
 532         .idlect_shift   = 3,
 533 };
 534
 535 static struct clk uart1_1510 = {
 536         .name           = "uart1_ck",
 537         /* Direct from ULPD, no real parent */
 538         .parent         = &armper_ck.clk,
 539         .rate           = 12000000,
 540         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 541                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 542                           CLOCK_NO_IDLE_PARENT,
 543         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 544         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 545         .set_rate       = &omap1_set_uart_rate,
 546         .recalc         = &omap1_uart_recalc,
 547         .enable         = &omap1_clk_enable_generic,
 548         .disable        = &omap1_clk_disable_generic,
 549 };
 550
 551 static struct uart_clk uart1_16xx = {
 552         .clk    = {
 553                 .name           = "uart1_ck",
 554                 /* Direct from ULPD, no real parent */
 555                 .parent         = &armper_ck.clk,
 556                 .rate           = 48000000,
 557                 .flags          = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
 558                                   CLOCK_NO_IDLE_PARENT,
 559                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 560                 .enable_bit     = 29,
 561                 .enable         = &omap1_clk_enable_uart_functional,
 562                 .disable        = &omap1_clk_disable_uart_functional,
 563         },
 564         .sysc_addr      = 0xfffb0054,
 565 };
 566
 567 static struct clk uart2_ck = {
 568         .name           = "uart2_ck",
 569         /* Direct from ULPD, no real parent */
 570         .parent         = &armper_ck.clk,
 571         .rate           = 12000000,
 572         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 573                           CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
 574                           ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
 575         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 576         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 577         .set_rate       = &omap1_set_uart_rate,
 578         .recalc         = &omap1_uart_recalc,
 579         .enable         = &omap1_clk_enable_generic,
 580         .disable        = &omap1_clk_disable_generic,
 581 };
 582
 583 static struct clk uart3_1510 = {
 584         .name           = "uart3_ck",
 585         /* Direct from ULPD, no real parent */
 586         .parent         = &armper_ck.clk,
 587         .rate           = 12000000,
 588         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 589                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 590                           CLOCK_NO_IDLE_PARENT,
 591         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 592         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 593         .set_rate       = &omap1_set_uart_rate,
 594         .recalc         = &omap1_uart_recalc,
 595         .enable         = &omap1_clk_enable_generic,
 596         .disable        = &omap1_clk_disable_generic,
 597 };
 598
 599 static struct uart_clk uart3_16xx = {
 600         .clk    = {
 601                 .name           = "uart3_ck",
 602                 /* Direct from ULPD, no real parent */
 603                 .parent         = &armper_ck.clk,
 604                 .rate           = 48000000,
 605                 .flags          = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
 606                                   CLOCK_NO_IDLE_PARENT,
 607                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 608                 .enable_bit     = 31,
 609                 .enable         = &omap1_clk_enable_uart_functional,
 610                 .disable        = &omap1_clk_disable_uart_functional,
 611         },
 612         .sysc_addr      = 0xfffb9854,
 613 };
 614
 615 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 616         .name           = "usb_clko",
 617         /* Direct from ULPD, no parent */
 618         .rate           = 6000000,
 619         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 620                           CLOCK_IN_OMAP310 | ENABLE_REG_32BIT,
 621         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 622         .enable_bit     = USB_MCLK_EN_BIT,
 623         .enable         = &omap1_clk_enable_generic,
 624         .disable        = &omap1_clk_disable_generic,
 625 };
 626
 627 static struct clk usb_hhc_ck1510 = {
 628         .name           = "usb_hhc_ck",
 629         /* Direct from ULPD, no parent */
 630         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 631         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 632                           ENABLE_REG_32BIT,
 633         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 634         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 635         .enable         = &omap1_clk_enable_generic,
 636         .disable        = &omap1_clk_disable_generic,
 637 };
 638
 639 static struct clk usb_hhc_ck16xx = {
 640         .name           = "usb_hhc_ck",
 641         /* Direct from ULPD, no parent */
 642         .rate           = 48000000,
 643         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 644         .flags          = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT,
 645         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 646         .enable_bit     = 8 /* UHOST_EN */,
 647         .enable         = &omap1_clk_enable_generic,
 648         .disable        = &omap1_clk_disable_generic,
 649 };
 650
 651 static struct clk usb_dc_ck = {
 652         .name           = "usb_dc_ck",
 653         /* Direct from ULPD, no parent */
 654         .rate           = 48000000,
 655         .flags          = CLOCK_IN_OMAP16XX,
 656         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 657         .enable_bit     = 4,
 658         .enable         = &omap1_clk_enable_generic,
 659         .disable        = &omap1_clk_disable_generic,
 660 };
 661
 662 static struct clk mclk_1510 = {
 663         .name           = "mclk",
 664         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 665         .rate           = 12000000,
 666         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 667         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 668         .enable_bit     = 6,
 669         .enable         = &omap1_clk_enable_generic,
 670         .disable        = &omap1_clk_disable_generic,
 671 };
 672
 673 static struct clk mclk_16xx = {
 674         .name           = "mclk",
 675         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 676         .flags          = CLOCK_IN_OMAP16XX,
 677         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 678         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 679         .set_rate       = &omap1_set_ext_clk_rate,
 680         .round_rate     = &omap1_round_ext_clk_rate,
 681         .init           = &omap1_init_ext_clk,
 682         .enable         = &omap1_clk_enable_generic,
 683         .disable        = &omap1_clk_disable_generic,
 684 };
 685
 686 static struct clk bclk_1510 = {
 687         .name           = "bclk",
 688         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 689         .rate           = 12000000,
 690         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 691         .enable         = &omap1_clk_enable_generic,
 692         .disable        = &omap1_clk_disable_generic,
 693 };
 694
 695 static struct clk bclk_16xx = {
 696         .name           = "bclk",
 697         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 698         .flags          = CLOCK_IN_OMAP16XX,
 699         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 700         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 701         .set_rate       = &omap1_set_ext_clk_rate,
 702         .round_rate     = &omap1_round_ext_clk_rate,
 703         .init           = &omap1_init_ext_clk,
 704         .enable         = &omap1_clk_enable_generic,
 705         .disable        = &omap1_clk_disable_generic,
 706 };
 707
 708 static struct clk mmc1_ck = {
 709         .name           = "mmc_ck",
 710         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 711         .parent         = &armper_ck.clk,
 712         .rate           = 48000000,
 713         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 714                           CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
 715                           CLOCK_NO_IDLE_PARENT,
 716         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 717         .enable_bit     = 23,
 718         .enable         = &omap1_clk_enable_generic,
 719         .disable        = &omap1_clk_disable_generic,
 720 };
 721
 722 static struct clk mmc2_ck = {
 723         .name           = "mmc_ck",
 724         .id             = 1,
 725         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 726         .parent         = &armper_ck.clk,
 727         .rate           = 48000000,
 728         .flags          = CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
 729                           CLOCK_NO_IDLE_PARENT,
 730         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 731         .enable_bit     = 20,
 732         .enable         = &omap1_clk_enable_generic,
 733         .disable        = &omap1_clk_disable_generic,
 734 };
 735
 736 static struct clk virtual_ck_mpu = {
 737         .name           = "mpu",
 738         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 739                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 740         .parent         = &arm_ck, /* Is smarter alias for */
 741         .recalc         = &followparent_recalc,
 742         .set_rate       = &omap1_select_table_rate,
 743         .round_rate     = &omap1_round_to_table_rate,
 744         .enable         = &omap1_clk_enable_generic,
 745         .disable        = &omap1_clk_disable_generic,
 746 };
 747
 748 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 749 remains active during MPU idle whenever this is enabled */
 750 static struct clk i2c_fck = {
 751         .name           = "i2c_fck",
 752         .id             = 1,
 753         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 754                           CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED,
 755         .parent         = &armxor_ck.clk,
 756         .recalc         = &followparent_recalc,
 757         .enable         = &omap1_clk_enable_generic,
 758         .disable        = &omap1_clk_disable_generic,
 759 };
 760
 761 static struct clk i2c_ick = {
 762         .name           = "i2c_ick",
 763         .id             = 1,
 764         .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
 765                           ALWAYS_ENABLED,
 766         .parent         = &armper_ck.clk,
 767         .recalc         = &followparent_recalc,
 768         .enable         = &omap1_clk_enable_generic,
 769         .disable        = &omap1_clk_disable_generic,
 770 };
 771
 772 static struct clk * onchip_clks[] = {
 773         /* non-ULPD clocks */
 774         &ck_ref,
 775         &ck_dpll1,
 776         /* CK_GEN1 clocks */
 777         &ck_dpll1out.clk,
 778         &sossi_ck,
 779         &arm_ck,
 780         &armper_ck.clk,
 781         &arm_gpio_ck,
 782         &armxor_ck.clk,
 783         &armtim_ck.clk,
 784         &armwdt_ck.clk,
 785         &arminth_ck1510,  &arminth_ck16xx,
 786         /* CK_GEN2 clocks */
 787         &dsp_ck,
 788         &dspmmu_ck,
 789         &dspper_ck,
 790         &dspxor_ck,
 791         &dsptim_ck,
 792         /* CK_GEN3 clocks */
 793         &tc_ck.clk,
 794         &tipb_ck,
 795         &l3_ocpi_ck,
 796         &tc1_ck,
 797         &tc2_ck,
 798         &dma_ck,
 799         &dma_lcdfree_ck,
 800         &api_ck.clk,
 801         &lb_ck.clk,
 802         &rhea1_ck,
 803         &rhea2_ck,
 804         &lcd_ck_16xx,
 805         &lcd_ck_1510.clk,
 806         /* ULPD clocks */
 807         &uart1_1510,
 808         &uart1_16xx.clk,
 809         &uart2_ck,
 810         &uart3_1510,
 811         &uart3_16xx.clk,
 812         &usb_clko,
 813         &usb_hhc_ck1510, &usb_hhc_ck16xx,
 814         &usb_dc_ck,
 815         &mclk_1510,  &mclk_16xx,
 816         &bclk_1510,  &bclk_16xx,
 817         &mmc1_ck,
 818         &mmc2_ck,
 819         /* Virtual clocks */
 820         &virtual_ck_mpu,
 821         &i2c_fck,
 822         &i2c_ick,
 823 };
 824
 825 #endif