arch/arm/mach-omap1/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static int omap1_clk_enable_generic(struct clk * clk);
  17 static void omap1_clk_disable_generic(struct clk * clk);
  18 static void omap1_ckctl_recalc(struct clk * clk);
  19 static void omap1_watchdog_recalc(struct clk * clk);
  20 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
  21 static void omap1_sossi_recalc(struct clk *clk);
  22 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
  23 static int omap1_clk_enable_dsp_domain(struct clk * clk);
  24 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  25 static void omap1_clk_disable_dsp_domain(struct clk * clk);
  26 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  27 static void omap1_uart_recalc(struct clk * clk);
  28 static int omap1_clk_enable_uart_functional(struct clk * clk);
  29 static void omap1_clk_disable_uart_functional(struct clk * clk);
  30 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  31 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  32 static void omap1_init_ext_clk(struct clk * clk);
  33 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  34 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  35 static int omap1_clk_enable(struct clk *clk);
  36 static void omap1_clk_disable(struct clk *clk);
  37
  38 struct mpu_rate {
  39         unsigned long           rate;
  40         unsigned long           xtal;
  41         unsigned long           pll_rate;
  42         __u16                   ckctl_val;
  43         __u16                   dpllctl_val;
  44 };
  45
  46 struct uart_clk {
  47         struct clk      clk;
  48         unsigned long   sysc_addr;
  49 };
  50
  51 /* Provide a method for preventing idling some ARM IDLECT clocks */
  52 struct arm_idlect1_clk {
  53         struct clk      clk;
  54         unsigned long   no_idle_count;
  55         __u8            idlect_shift;
  56 };
  57
  58 /* ARM_CKCTL bit shifts */
  59 #define CKCTL_PERDIV_OFFSET     0
  60 #define CKCTL_LCDDIV_OFFSET     2
  61 #define CKCTL_ARMDIV_OFFSET     4
  62 #define CKCTL_DSPDIV_OFFSET     6
  63 #define CKCTL_TCDIV_OFFSET      8
  64 #define CKCTL_DSPMMUDIV_OFFSET  10
  65 /*#define ARM_TIMXO             12*/
  66 #define EN_DSPCK                13
  67 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  68 /* DSP_CKCTL bit shifts */
  69 #define CKCTL_DSPPERDIV_OFFSET  0
  70
  71 /* ARM_IDLECT2 bit shifts */
  72 #define EN_WDTCK        0
  73 #define EN_XORPCK       1
  74 #define EN_PERCK        2
  75 #define EN_LCDCK        3
  76 #define EN_LBCK         4 /* Not on 1610/1710 */
  77 /*#define EN_HSABCK     5*/
  78 #define EN_APICK        6
  79 #define EN_TIMCK        7
  80 #define DMACK_REQ       8
  81 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  82 /*#define EN_LBFREECK   10*/
  83 #define EN_CKOUT_ARM    11
  84
  85 /* ARM_IDLECT3 bit shifts */
  86 #define EN_OCPI_CK      0
  87 #define EN_TC1_CK       2
  88 #define EN_TC2_CK       4
  89
  90 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  91 #define EN_DSPTIMCK     5
  92
  93 /* Various register defines for clock controls scattered around OMAP chip */
  94 #define SDW_MCLK_INV_BIT        2       /* In ULPD_CLKC_CTRL */
  95 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
  96 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
  97 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
  98 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
  99 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
 100 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
 101 #define SOFT_REQ_REG            0xfffe0834
 102 #define SOFT_REQ_REG2           0xfffe0880
 103
 104 /*-------------------------------------------------------------------------
 105  * Omap1 MPU rate table
 106  *-------------------------------------------------------------------------*/
 107 static struct mpu_rate rate_table[] = {
 108         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 109          * NOTE: Comment order here is different from bits in CKCTL value:
 110          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 111          */
 112 #if defined(CONFIG_OMAP_ARM_216MHZ)
 113         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 114 #endif
 115 #if defined(CONFIG_OMAP_ARM_195MHZ)
 116         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 117 #endif
 118 #if defined(CONFIG_OMAP_ARM_192MHZ)
 119         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 120         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 121         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 122         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 123         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 124 #endif
 125 #if defined(CONFIG_OMAP_ARM_182MHZ)
 126         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 127 #endif
 128 #if defined(CONFIG_OMAP_ARM_168MHZ)
 129         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 130 #endif
 131 #if defined(CONFIG_OMAP_ARM_150MHZ)
 132         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 133 #endif
 134 #if defined(CONFIG_OMAP_ARM_120MHZ)
 135         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 136 #endif
 137 #if defined(CONFIG_OMAP_ARM_96MHZ)
 138         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 139 #endif
 140 #if defined(CONFIG_OMAP_ARM_60MHZ)
 141         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 142 #endif
 143 #if defined(CONFIG_OMAP_ARM_30MHZ)
 144         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 145 #endif
 146         { 0, 0, 0, 0, 0 },
 147 };
 148
 149 /*-------------------------------------------------------------------------
 150  * Omap1 clocks
 151  *-------------------------------------------------------------------------*/
 152
 153 static struct clk ck_ref = {
 154         .name           = "ck_ref",
 155         .rate           = 12000000,
 156         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 157                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 158         .enable         = &omap1_clk_enable_generic,
 159         .disable        = &omap1_clk_disable_generic,
 160 };
 161
 162 static struct clk ck_dpll1 = {
 163         .name           = "ck_dpll1",
 164         .parent         = &ck_ref,
 165         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 166                           CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
 167         .enable         = &omap1_clk_enable_generic,
 168         .disable        = &omap1_clk_disable_generic,
 169 };
 170
 171 static struct arm_idlect1_clk ck_dpll1out = {
 172         .clk = {
 173                 .name           = "ck_dpll1out",
 174                 .parent         = &ck_dpll1,
 175                 .flags          = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
 176                                   ENABLE_REG_32BIT | RATE_PROPAGATES,
 177                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 178                 .enable_bit     = EN_CKOUT_ARM,
 179                 .recalc         = &followparent_recalc,
 180                 .enable         = &omap1_clk_enable_generic,
 181                 .disable        = &omap1_clk_disable_generic,
 182         },
 183         .idlect_shift   = 12,
 184 };
 185
 186 static struct clk sossi_ck = {
 187         .name           = "ck_sossi",
 188         .parent         = &ck_dpll1out.clk,
 189         .flags          = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
 190                           ENABLE_REG_32BIT,
 191         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
 192         .enable_bit     = 16,
 193         .recalc         = &omap1_sossi_recalc,
 194         .set_rate       = &omap1_set_sossi_rate,
 195         .enable         = &omap1_clk_enable_generic,
 196         .disable        = &omap1_clk_disable_generic,
 197 };
 198
 199 static struct clk arm_ck = {
 200         .name           = "arm_ck",
 201         .parent         = &ck_dpll1,
 202         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 203                           CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
 204                           ALWAYS_ENABLED,
 205         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 206         .recalc         = &omap1_ckctl_recalc,
 207         .enable         = &omap1_clk_enable_generic,
 208         .disable        = &omap1_clk_disable_generic,
 209 };
 210
 211 static struct arm_idlect1_clk armper_ck = {
 212         .clk = {
 213                 .name           = "armper_ck",
 214                 .parent         = &ck_dpll1,
 215                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 216                                   CLOCK_IN_OMAP310 | RATE_CKCTL |
 217                                   CLOCK_IDLE_CONTROL,
 218                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 219                 .enable_bit     = EN_PERCK,
 220                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 221                 .recalc         = &omap1_ckctl_recalc,
 222                 .enable         = &omap1_clk_enable_generic,
 223                 .disable        = &omap1_clk_disable_generic,
 224         },
 225         .idlect_shift   = 2,
 226 };
 227
 228 static struct clk arm_gpio_ck = {
 229         .name           = "arm_gpio_ck",
 230         .parent         = &ck_dpll1,
 231         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 232         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 233         .enable_bit     = EN_GPIOCK,
 234         .recalc         = &followparent_recalc,
 235         .enable         = &omap1_clk_enable_generic,
 236         .disable        = &omap1_clk_disable_generic,
 237 };
 238
 239 static struct arm_idlect1_clk armxor_ck = {
 240         .clk = {
 241                 .name           = "armxor_ck",
 242                 .parent         = &ck_ref,
 243                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 244                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 245                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 246                 .enable_bit     = EN_XORPCK,
 247                 .recalc         = &followparent_recalc,
 248                 .enable         = &omap1_clk_enable_generic,
 249                 .disable        = &omap1_clk_disable_generic,
 250         },
 251         .idlect_shift   = 1,
 252 };
 253
 254 static struct arm_idlect1_clk armtim_ck = {
 255         .clk = {
 256                 .name           = "armtim_ck",
 257                 .parent         = &ck_ref,
 258                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 259                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 260                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 261                 .enable_bit     = EN_TIMCK,
 262                 .recalc         = &followparent_recalc,
 263                 .enable         = &omap1_clk_enable_generic,
 264                 .disable        = &omap1_clk_disable_generic,
 265         },
 266         .idlect_shift   = 9,
 267 };
 268
 269 static struct arm_idlect1_clk armwdt_ck = {
 270         .clk = {
 271                 .name           = "armwdt_ck",
 272                 .parent         = &ck_ref,
 273                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 274                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 275                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 276                 .enable_bit     = EN_WDTCK,
 277                 .recalc         = &omap1_watchdog_recalc,
 278                 .enable         = &omap1_clk_enable_generic,
 279                 .disable        = &omap1_clk_disable_generic,
 280         },
 281         .idlect_shift   = 0,
 282 };
 283
 284 static struct clk arminth_ck16xx = {
 285         .name           = "arminth_ck",
 286         .parent         = &arm_ck,
 287         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 288         .recalc         = &followparent_recalc,
 289         /* Note: On 16xx the frequency can be divided by 2 by programming
 290          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 291          *
 292          * 1510 version is in TC clocks.
 293          */
 294         .enable         = &omap1_clk_enable_generic,
 295         .disable        = &omap1_clk_disable_generic,
 296 };
 297
 298 static struct clk dsp_ck = {
 299         .name           = "dsp_ck",
 300         .parent         = &ck_dpll1,
 301         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 302                           RATE_CKCTL,
 303         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 304         .enable_bit     = EN_DSPCK,
 305         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 306         .recalc         = &omap1_ckctl_recalc,
 307         .enable         = &omap1_clk_enable_generic,
 308         .disable        = &omap1_clk_disable_generic,
 309 };
 310
 311 static struct clk dspmmu_ck = {
 312         .name           = "dspmmu_ck",
 313         .parent         = &ck_dpll1,
 314         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 315                           RATE_CKCTL | ALWAYS_ENABLED,
 316         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 317         .recalc         = &omap1_ckctl_recalc,
 318         .enable         = &omap1_clk_enable_generic,
 319         .disable        = &omap1_clk_disable_generic,
 320 };
 321
 322 static struct clk dspper_ck = {
 323         .name           = "dspper_ck",
 324         .parent         = &ck_dpll1,
 325         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 326                           RATE_CKCTL,
 327         .enable_reg     = IOMEM(DSP_IDLECT2),
 328         .enable_bit     = EN_PERCK,
 329         .rate_offset    = CKCTL_PERDIV_OFFSET,
 330         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 331         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 332         .enable         = &omap1_clk_enable_dsp_domain,
 333         .disable        = &omap1_clk_disable_dsp_domain,
 334 };
 335
 336 static struct clk dspxor_ck = {
 337         .name           = "dspxor_ck",
 338         .parent         = &ck_ref,
 339         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 340         .enable_reg     = IOMEM(DSP_IDLECT2),
 341         .enable_bit     = EN_XORPCK,
 342         .recalc         = &followparent_recalc,
 343         .enable         = &omap1_clk_enable_dsp_domain,
 344         .disable        = &omap1_clk_disable_dsp_domain,
 345 };
 346
 347 static struct clk dsptim_ck = {
 348         .name           = "dsptim_ck",
 349         .parent         = &ck_ref,
 350         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
 351         .enable_reg     = IOMEM(DSP_IDLECT2),
 352         .enable_bit     = EN_DSPTIMCK,
 353         .recalc         = &followparent_recalc,
 354         .enable         = &omap1_clk_enable_dsp_domain,
 355         .disable        = &omap1_clk_disable_dsp_domain,
 356 };
 357
 358 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 359 static struct arm_idlect1_clk tc_ck = {
 360         .clk = {
 361                 .name           = "tc_ck",
 362                 .parent         = &ck_dpll1,
 363                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 364                                   CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
 365                                   RATE_CKCTL | RATE_PROPAGATES |
 366                                   ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
 367                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 368                 .recalc         = &omap1_ckctl_recalc,
 369                 .enable         = &omap1_clk_enable_generic,
 370                 .disable        = &omap1_clk_disable_generic,
 371         },
 372         .idlect_shift   = 6,
 373 };
 374
 375 static struct clk arminth_ck1510 = {
 376         .name           = "arminth_ck",
 377         .parent         = &tc_ck.clk,
 378         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 379                           ALWAYS_ENABLED,
 380         .recalc         = &followparent_recalc,
 381         /* Note: On 1510 the frequency follows TC_CK
 382          *
 383          * 16xx version is in MPU clocks.
 384          */
 385         .enable         = &omap1_clk_enable_generic,
 386         .disable        = &omap1_clk_disable_generic,
 387 };
 388
 389 static struct clk tipb_ck = {
 390         /* No-idle controlled by "tc_ck" */
 391         .name           = "tipb_ck",
 392         .parent         = &tc_ck.clk,
 393         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 394                           ALWAYS_ENABLED,
 395         .recalc         = &followparent_recalc,
 396         .enable         = &omap1_clk_enable_generic,
 397         .disable        = &omap1_clk_disable_generic,
 398 };
 399
 400 static struct clk l3_ocpi_ck = {
 401         /* No-idle controlled by "tc_ck" */
 402         .name           = "l3_ocpi_ck",
 403         .parent         = &tc_ck.clk,
 404         .flags          = CLOCK_IN_OMAP16XX,
 405         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 406         .enable_bit     = EN_OCPI_CK,
 407         .recalc         = &followparent_recalc,
 408         .enable         = &omap1_clk_enable_generic,
 409         .disable        = &omap1_clk_disable_generic,
 410 };
 411
 412 static struct clk tc1_ck = {
 413         .name           = "tc1_ck",
 414         .parent         = &tc_ck.clk,
 415         .flags          = CLOCK_IN_OMAP16XX,
 416         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 417         .enable_bit     = EN_TC1_CK,
 418         .recalc         = &followparent_recalc,
 419         .enable         = &omap1_clk_enable_generic,
 420         .disable        = &omap1_clk_disable_generic,
 421 };
 422
 423 static struct clk tc2_ck = {
 424         .name           = "tc2_ck",
 425         .parent         = &tc_ck.clk,
 426         .flags          = CLOCK_IN_OMAP16XX,
 427         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 428         .enable_bit     = EN_TC2_CK,
 429         .recalc         = &followparent_recalc,
 430         .enable         = &omap1_clk_enable_generic,
 431         .disable        = &omap1_clk_disable_generic,
 432 };
 433
 434 static struct clk dma_ck = {
 435         /* No-idle controlled by "tc_ck" */
 436         .name           = "dma_ck",
 437         .parent         = &tc_ck.clk,
 438         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 439                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 440         .recalc         = &followparent_recalc,
 441         .enable         = &omap1_clk_enable_generic,
 442         .disable        = &omap1_clk_disable_generic,
 443 };
 444
 445 static struct clk dma_lcdfree_ck = {
 446         .name           = "dma_lcdfree_ck",
 447         .parent         = &tc_ck.clk,
 448         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 449         .recalc         = &followparent_recalc,
 450         .enable         = &omap1_clk_enable_generic,
 451         .disable        = &omap1_clk_disable_generic,
 452 };
 453
 454 static struct arm_idlect1_clk api_ck = {
 455         .clk = {
 456                 .name           = "api_ck",
 457                 .parent         = &tc_ck.clk,
 458                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 459                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 460                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 461                 .enable_bit     = EN_APICK,
 462                 .recalc         = &followparent_recalc,
 463                 .enable         = &omap1_clk_enable_generic,
 464                 .disable        = &omap1_clk_disable_generic,
 465         },
 466         .idlect_shift   = 8,
 467 };
 468
 469 static struct arm_idlect1_clk lb_ck = {
 470         .clk = {
 471                 .name           = "lb_ck",
 472                 .parent         = &tc_ck.clk,
 473                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 474                                   CLOCK_IDLE_CONTROL,
 475                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 476                 .enable_bit     = EN_LBCK,
 477                 .recalc         = &followparent_recalc,
 478                 .enable         = &omap1_clk_enable_generic,
 479                 .disable        = &omap1_clk_disable_generic,
 480         },
 481         .idlect_shift   = 4,
 482 };
 483
 484 static struct clk rhea1_ck = {
 485         .name           = "rhea1_ck",
 486         .parent         = &tc_ck.clk,
 487         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 488         .recalc         = &followparent_recalc,
 489         .enable         = &omap1_clk_enable_generic,
 490         .disable        = &omap1_clk_disable_generic,
 491 };
 492
 493 static struct clk rhea2_ck = {
 494         .name           = "rhea2_ck",
 495         .parent         = &tc_ck.clk,
 496         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 497         .recalc         = &followparent_recalc,
 498         .enable         = &omap1_clk_enable_generic,
 499         .disable        = &omap1_clk_disable_generic,
 500 };
 501
 502 static struct clk lcd_ck_16xx = {
 503         .name           = "lcd_ck",
 504         .parent         = &ck_dpll1,
 505         .flags          = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
 506         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 507         .enable_bit     = EN_LCDCK,
 508         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 509         .recalc         = &omap1_ckctl_recalc,
 510         .enable         = &omap1_clk_enable_generic,
 511         .disable        = &omap1_clk_disable_generic,
 512 };
 513
 514 static struct arm_idlect1_clk lcd_ck_1510 = {
 515         .clk = {
 516                 .name           = "lcd_ck",
 517                 .parent         = &ck_dpll1,
 518                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 519                                   RATE_CKCTL | CLOCK_IDLE_CONTROL,
 520                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 521                 .enable_bit     = EN_LCDCK,
 522                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 523                 .recalc         = &omap1_ckctl_recalc,
 524                 .enable         = &omap1_clk_enable_generic,
 525                 .disable        = &omap1_clk_disable_generic,
 526         },
 527         .idlect_shift   = 3,
 528 };
 529
 530 static struct clk uart1_1510 = {
 531         .name           = "uart1_ck",
 532         /* Direct from ULPD, no real parent */
 533         .parent         = &armper_ck.clk,
 534         .rate           = 12000000,
 535         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 536                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 537                           CLOCK_NO_IDLE_PARENT,
 538         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 539         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 540         .set_rate       = &omap1_set_uart_rate,
 541         .recalc         = &omap1_uart_recalc,
 542         .enable         = &omap1_clk_enable_generic,
 543         .disable        = &omap1_clk_disable_generic,
 544 };
 545
 546 static struct uart_clk uart1_16xx = {
 547         .clk    = {
 548                 .name           = "uart1_ck",
 549                 /* Direct from ULPD, no real parent */
 550                 .parent         = &armper_ck.clk,
 551                 .rate           = 48000000,
 552                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 553                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 554                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 555                 .enable_bit     = 29,
 556                 .enable         = &omap1_clk_enable_uart_functional,
 557                 .disable        = &omap1_clk_disable_uart_functional,
 558         },
 559         .sysc_addr      = 0xfffb0054,
 560 };
 561
 562 static struct clk uart2_ck = {
 563         .name           = "uart2_ck",
 564         /* Direct from ULPD, no real parent */
 565         .parent         = &armper_ck.clk,
 566         .rate           = 12000000,
 567         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 568                           CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
 569                           ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
 570         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 571         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 572         .set_rate       = &omap1_set_uart_rate,
 573         .recalc         = &omap1_uart_recalc,
 574         .enable         = &omap1_clk_enable_generic,
 575         .disable        = &omap1_clk_disable_generic,
 576 };
 577
 578 static struct clk uart3_1510 = {
 579         .name           = "uart3_ck",
 580         /* Direct from ULPD, no real parent */
 581         .parent         = &armper_ck.clk,
 582         .rate           = 12000000,
 583         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 584                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 585                           CLOCK_NO_IDLE_PARENT,
 586         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 587         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 588         .set_rate       = &omap1_set_uart_rate,
 589         .recalc         = &omap1_uart_recalc,
 590         .enable         = &omap1_clk_enable_generic,
 591         .disable        = &omap1_clk_disable_generic,
 592 };
 593
 594 static struct uart_clk uart3_16xx = {
 595         .clk    = {
 596                 .name           = "uart3_ck",
 597                 /* Direct from ULPD, no real parent */
 598                 .parent         = &armper_ck.clk,
 599                 .rate           = 48000000,
 600                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 601                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 602                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 603                 .enable_bit     = 31,
 604                 .enable         = &omap1_clk_enable_uart_functional,
 605                 .disable        = &omap1_clk_disable_uart_functional,
 606         },
 607         .sysc_addr      = 0xfffb9854,
 608 };
 609
 610 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 611         .name           = "usb_clko",
 612         /* Direct from ULPD, no parent */
 613         .rate           = 6000000,
 614         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 615                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
 616         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 617         .enable_bit     = USB_MCLK_EN_BIT,
 618         .enable         = &omap1_clk_enable_generic,
 619         .disable        = &omap1_clk_disable_generic,
 620 };
 621
 622 static struct clk usb_hhc_ck1510 = {
 623         .name           = "usb_hhc_ck",
 624         /* Direct from ULPD, no parent */
 625         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 626         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 627                           RATE_FIXED | ENABLE_REG_32BIT,
 628         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 629         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 630         .enable         = &omap1_clk_enable_generic,
 631         .disable        = &omap1_clk_disable_generic,
 632 };
 633
 634 static struct clk usb_hhc_ck16xx = {
 635         .name           = "usb_hhc_ck",
 636         /* Direct from ULPD, no parent */
 637         .rate           = 48000000,
 638         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 639         .flags          = CLOCK_IN_OMAP16XX |
 640                           RATE_FIXED | ENABLE_REG_32BIT,
 641         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 642         .enable_bit     = 8 /* UHOST_EN */,
 643         .enable         = &omap1_clk_enable_generic,
 644         .disable        = &omap1_clk_disable_generic,
 645 };
 646
 647 static struct clk usb_dc_ck = {
 648         .name           = "usb_dc_ck",
 649         /* Direct from ULPD, no parent */
 650         .rate           = 48000000,
 651         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED,
 652         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 653         .enable_bit     = 4,
 654         .enable         = &omap1_clk_enable_generic,
 655         .disable        = &omap1_clk_disable_generic,
 656 };
 657
 658 static struct clk mclk_1510 = {
 659         .name           = "mclk",
 660         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 661         .rate           = 12000000,
 662         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 663         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 664         .enable_bit     = 6,
 665         .enable         = &omap1_clk_enable_generic,
 666         .disable        = &omap1_clk_disable_generic,
 667 };
 668
 669 static struct clk mclk_16xx = {
 670         .name           = "mclk",
 671         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 672         .flags          = CLOCK_IN_OMAP16XX,
 673         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 674         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 675         .set_rate       = &omap1_set_ext_clk_rate,
 676         .round_rate     = &omap1_round_ext_clk_rate,
 677         .init           = &omap1_init_ext_clk,
 678         .enable         = &omap1_clk_enable_generic,
 679         .disable        = &omap1_clk_disable_generic,
 680 };
 681
 682 static struct clk bclk_1510 = {
 683         .name           = "bclk",
 684         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 685         .rate           = 12000000,
 686         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 687         .enable         = &omap1_clk_enable_generic,
 688         .disable        = &omap1_clk_disable_generic,
 689 };
 690
 691 static struct clk bclk_16xx = {
 692         .name           = "bclk",
 693         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 694         .flags          = CLOCK_IN_OMAP16XX,
 695         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 696         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 697         .set_rate       = &omap1_set_ext_clk_rate,
 698         .round_rate     = &omap1_round_ext_clk_rate,
 699         .init           = &omap1_init_ext_clk,
 700         .enable         = &omap1_clk_enable_generic,
 701         .disable        = &omap1_clk_disable_generic,
 702 };
 703
 704 static struct clk mmc1_ck = {
 705         .name           = "mmc_ck",
 706         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 707         .parent         = &armper_ck.clk,
 708         .rate           = 48000000,
 709         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 710                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
 711                           CLOCK_NO_IDLE_PARENT,
 712         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 713         .enable_bit     = 23,
 714         .enable         = &omap1_clk_enable_generic,
 715         .disable        = &omap1_clk_disable_generic,
 716 };
 717
 718 static struct clk mmc2_ck = {
 719         .name           = "mmc_ck",
 720         .id             = 1,
 721         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 722         .parent         = &armper_ck.clk,
 723         .rate           = 48000000,
 724         .flags          = CLOCK_IN_OMAP16XX |
 725                           RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 726         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 727         .enable_bit     = 20,
 728         .enable         = &omap1_clk_enable_generic,
 729         .disable        = &omap1_clk_disable_generic,
 730 };
 731
 732 static struct clk virtual_ck_mpu = {
 733         .name           = "mpu",
 734         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 735                           CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,
 736         .parent         = &arm_ck, /* Is smarter alias for */
 737         .recalc         = &followparent_recalc,
 738         .set_rate       = &omap1_select_table_rate,
 739         .round_rate     = &omap1_round_to_table_rate,
 740         .enable         = &omap1_clk_enable_generic,
 741         .disable        = &omap1_clk_disable_generic,
 742 };
 743
 744 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 745 remains active during MPU idle whenever this is enabled */
 746 static struct clk i2c_fck = {
 747         .name           = "i2c_fck",
 748         .id             = 1,
 749         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 750                           VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
 751                           ALWAYS_ENABLED,
 752         .parent         = &armxor_ck.clk,
 753         .recalc         = &followparent_recalc,
 754         .enable         = &omap1_clk_enable_generic,
 755         .disable        = &omap1_clk_disable_generic,
 756 };
 757
 758 static struct clk i2c_ick = {
 759         .name           = "i2c_ick",
 760         .id             = 1,
 761         .flags          = CLOCK_IN_OMAP16XX |
 762                           VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
 763                           ALWAYS_ENABLED,
 764         .parent         = &armper_ck.clk,
 765         .recalc         = &followparent_recalc,
 766         .enable         = &omap1_clk_enable_generic,
 767         .disable        = &omap1_clk_disable_generic,
 768 };
 769
 770 static struct clk * onchip_clks[] = {
 771         /* non-ULPD clocks */
 772         &ck_ref,
 773         &ck_dpll1,
 774         /* CK_GEN1 clocks */
 775         &ck_dpll1out.clk,
 776         &sossi_ck,
 777         &arm_ck,
 778         &armper_ck.clk,
 779         &arm_gpio_ck,
 780         &armxor_ck.clk,
 781         &armtim_ck.clk,
 782         &armwdt_ck.clk,
 783         &arminth_ck1510,  &arminth_ck16xx,
 784         /* CK_GEN2 clocks */
 785         &dsp_ck,
 786         &dspmmu_ck,
 787         &dspper_ck,
 788         &dspxor_ck,
 789         &dsptim_ck,
 790         /* CK_GEN3 clocks */
 791         &tc_ck.clk,
 792         &tipb_ck,
 793         &l3_ocpi_ck,
 794         &tc1_ck,
 795         &tc2_ck,
 796         &dma_ck,
 797         &dma_lcdfree_ck,
 798         &api_ck.clk,
 799         &lb_ck.clk,
 800         &rhea1_ck,
 801         &rhea2_ck,
 802         &lcd_ck_16xx,
 803         &lcd_ck_1510.clk,
 804         /* ULPD clocks */
 805         &uart1_1510,
 806         &uart1_16xx.clk,
 807         &uart2_ck,
 808         &uart3_1510,
 809         &uart3_16xx.clk,
 810         &usb_clko,
 811         &usb_hhc_ck1510, &usb_hhc_ck16xx,
 812         &usb_dc_ck,
 813         &mclk_1510,  &mclk_16xx,
 814         &bclk_1510,  &bclk_16xx,
 815         &mmc1_ck,
 816         &mmc2_ck,
 817         /* Virtual clocks */
 818         &virtual_ck_mpu,
 819         &i2c_fck,
 820         &i2c_ick,
 821 };
 822
 823 #endif