arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <mach/cpu.h>
  26 #include <mach/usb.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 static int clk_omap1_dummy_enable(struct clk *clk)
  37 {
  38         return 0;
  39 }
  40
  41 static void clk_omap1_dummy_disable(struct clk *clk)
  42 {
  43 }
  44
  45 static const struct clkops clkops_dummy = {
  46         .enable = clk_omap1_dummy_enable,
  47         .disable = clk_omap1_dummy_disable,
  48 };
  49
  50 static struct clk dummy_ck = {
  51         .name   = "dummy",
  52         .ops    = &clkops_dummy,
  53         .flags  = RATE_FIXED,
  54 };
  55
  56 struct omap_clk {
  57         u32             cpu;
  58         struct clk_lookup lk;
  59 };
  60
  61 #define CLK(dev, con, ck, cp)           \
  62         {                               \
  63                  .cpu = cp,             \
  64                 .lk = {                 \
  65                         .dev_id = dev,  \
  66                         .con_id = con,  \
  67                         .clk = ck,      \
  68                 },                      \
  69         }
  70
  71 #define CK_310  (1 << 0)
  72 #define CK_730  (1 << 1)
  73 #define CK_1510 (1 << 2)
  74 #define CK_16XX (1 << 3)
  75
  76 static struct omap_clk omap_clks[] = {
  77         /* non-ULPD clocks */
  78         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
  79         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  80         /* CK_GEN1 clocks */
  81         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  82         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  83         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  85         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  86         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
  87         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  88         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  89         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
  90         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
  91         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  92         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  93         /* CK_GEN2 clocks */
  94         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  96         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  97         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  98         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  99         /* CK_GEN3 clocks */
 100         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
 101         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 102         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
 103         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 104         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 105         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 106         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 107         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
 108         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 109         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 110         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 111         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
 112         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 113         /* ULPD clocks */
 114         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 115         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 116         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 117         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 118         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 119         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 120         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 121         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 122         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 123         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 124         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 125         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 126         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 127         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 128         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 129         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 130         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 131         /* Virtual clocks */
 132         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 133         CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 134         CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
 135         CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310),
 136         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 137         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 138         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 139         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 140         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 141         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 142         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 143         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 144         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 145         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 146 };
 147
 148 static int omap1_clk_enable_generic(struct clk * clk);
 149 static int omap1_clk_enable(struct clk *clk);
 150 static void omap1_clk_disable_generic(struct clk * clk);
 151 static void omap1_clk_disable(struct clk *clk);
 152
 153 __u32 arm_idlect1_mask;
 154
 155 /*-------------------------------------------------------------------------
 156  * Omap1 specific clock functions
 157  *-------------------------------------------------------------------------*/
 158
 159 static void omap1_watchdog_recalc(struct clk * clk)
 160 {
 161         clk->rate = clk->parent->rate / 14;
 162 }
 163
 164 static void omap1_uart_recalc(struct clk * clk)
 165 {
 166         unsigned int val = omap_readl(clk->enable_reg);
 167         if (val & clk->enable_bit)
 168                 clk->rate = 48000000;
 169         else
 170                 clk->rate = 12000000;
 171 }
 172
 173 static void omap1_sossi_recalc(struct clk *clk)
 174 {
 175         u32 div = omap_readl(MOD_CONF_CTRL_1);
 176
 177         div = (div >> 17) & 0x7;
 178         div++;
 179         clk->rate = clk->parent->rate / div;
 180 }
 181
 182 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 183 {
 184         int retval;
 185
 186         retval = omap1_clk_enable(&api_ck.clk);
 187         if (!retval) {
 188                 retval = omap1_clk_enable_generic(clk);
 189                 omap1_clk_disable(&api_ck.clk);
 190         }
 191
 192         return retval;
 193 }
 194
 195 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 196 {
 197         if (omap1_clk_enable(&api_ck.clk) == 0) {
 198                 omap1_clk_disable_generic(clk);
 199                 omap1_clk_disable(&api_ck.clk);
 200         }
 201 }
 202
 203 static const struct clkops clkops_dspck = {
 204         .enable         = &omap1_clk_enable_dsp_domain,
 205         .disable        = &omap1_clk_disable_dsp_domain,
 206 };
 207
 208 static int omap1_clk_enable_uart_functional(struct clk *clk)
 209 {
 210         int ret;
 211         struct uart_clk *uclk;
 212
 213         ret = omap1_clk_enable_generic(clk);
 214         if (ret == 0) {
 215                 /* Set smart idle acknowledgement mode */
 216                 uclk = (struct uart_clk *)clk;
 217                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 218                             uclk->sysc_addr);
 219         }
 220
 221         return ret;
 222 }
 223
 224 static void omap1_clk_disable_uart_functional(struct clk *clk)
 225 {
 226         struct uart_clk *uclk;
 227
 228         /* Set force idle acknowledgement mode */
 229         uclk = (struct uart_clk *)clk;
 230         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 231
 232         omap1_clk_disable_generic(clk);
 233 }
 234
 235 static const struct clkops clkops_uart = {
 236         .enable         = &omap1_clk_enable_uart_functional,
 237         .disable        = &omap1_clk_disable_uart_functional,
 238 };
 239
 240 static void omap1_clk_allow_idle(struct clk *clk)
 241 {
 242         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 243
 244         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 245                 return;
 246
 247         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 248                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 249 }
 250
 251 static void omap1_clk_deny_idle(struct clk *clk)
 252 {
 253         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 254
 255         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 256                 return;
 257
 258         if (iclk->no_idle_count++ == 0)
 259                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 260 }
 261
 262 static __u16 verify_ckctl_value(__u16 newval)
 263 {
 264         /* This function checks for following limitations set
 265          * by the hardware (all conditions must be true):
 266          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 267          * ARM_CK >= TC_CK
 268          * DSP_CK >= TC_CK
 269          * DSPMMU_CK >= TC_CK
 270          *
 271          * In addition following rules are enforced:
 272          * LCD_CK <= TC_CK
 273          * ARMPER_CK <= TC_CK
 274          *
 275          * However, maximum frequencies are not checked for!
 276          */
 277         __u8 per_exp;
 278         __u8 lcd_exp;
 279         __u8 arm_exp;
 280         __u8 dsp_exp;
 281         __u8 tc_exp;
 282         __u8 dspmmu_exp;
 283
 284         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 285         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 286         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 287         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 288         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 289         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 290
 291         if (dspmmu_exp < dsp_exp)
 292                 dspmmu_exp = dsp_exp;
 293         if (dspmmu_exp > dsp_exp+1)
 294                 dspmmu_exp = dsp_exp+1;
 295         if (tc_exp < arm_exp)
 296                 tc_exp = arm_exp;
 297         if (tc_exp < dspmmu_exp)
 298                 tc_exp = dspmmu_exp;
 299         if (tc_exp > lcd_exp)
 300                 lcd_exp = tc_exp;
 301         if (tc_exp > per_exp)
 302                 per_exp = tc_exp;
 303
 304         newval &= 0xf000;
 305         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 306         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 307         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 308         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 309         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 310         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 311
 312         return newval;
 313 }
 314
 315 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 316 {
 317         /* Note: If target frequency is too low, this function will return 4,
 318          * which is invalid value. Caller must check for this value and act
 319          * accordingly.
 320          *
 321          * Note: This function does not check for following limitations set
 322          * by the hardware (all conditions must be true):
 323          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 324          * ARM_CK >= TC_CK
 325          * DSP_CK >= TC_CK
 326          * DSPMMU_CK >= TC_CK
 327          */
 328         unsigned long realrate;
 329         struct clk * parent;
 330         unsigned  dsor_exp;
 331
 332         parent = clk->parent;
 333         if (unlikely(parent == NULL))
 334                 return -EIO;
 335
 336         realrate = parent->rate;
 337         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 338                 if (realrate <= rate)
 339                         break;
 340
 341                 realrate /= 2;
 342         }
 343
 344         return dsor_exp;
 345 }
 346
 347 static void omap1_ckctl_recalc(struct clk * clk)
 348 {
 349         int dsor;
 350
 351         /* Calculate divisor encoded as 2-bit exponent */
 352         dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 353
 354         if (unlikely(clk->rate == clk->parent->rate / dsor))
 355                 return; /* No change, quick exit */
 356         clk->rate = clk->parent->rate / dsor;
 357 }
 358
 359 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
 360 {
 361         int dsor;
 362
 363         /* Calculate divisor encoded as 2-bit exponent
 364          *
 365          * The clock control bits are in DSP domain,
 366          * so api_ck is needed for access.
 367          * Note that DSP_CKCTL virt addr = phys addr, so
 368          * we must use __raw_readw() instead of omap_readw().
 369          */
 370         omap1_clk_enable(&api_ck.clk);
 371         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 372         omap1_clk_disable(&api_ck.clk);
 373
 374         if (unlikely(clk->rate == clk->parent->rate / dsor))
 375                 return; /* No change, quick exit */
 376         clk->rate = clk->parent->rate / dsor;
 377 }
 378
 379 /* MPU virtual clock functions */
 380 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 381 {
 382         /* Find the highest supported frequency <= rate and switch to it */
 383         struct mpu_rate * ptr;
 384
 385         if (clk != &virtual_ck_mpu)
 386                 return -EINVAL;
 387
 388         for (ptr = rate_table; ptr->rate; ptr++) {
 389                 if (ptr->xtal != ck_ref.rate)
 390                         continue;
 391
 392                 /* DPLL1 cannot be reprogrammed without risking system crash */
 393                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 394                         continue;
 395
 396                 /* Can check only after xtal frequency check */
 397                 if (ptr->rate <= rate)
 398                         break;
 399         }
 400
 401         if (!ptr->rate)
 402                 return -EINVAL;
 403
 404         /*
 405          * In most cases we should not need to reprogram DPLL.
 406          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 407          * (on 730, bit 13 must always be 1)
 408          */
 409         if (cpu_is_omap730())
 410                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 411         else
 412                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 413
 414         ck_dpll1.rate = ptr->pll_rate;
 415         return 0;
 416 }
 417
 418 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 419 {
 420         int dsor_exp;
 421         u16 regval;
 422
 423         dsor_exp = calc_dsor_exp(clk, rate);
 424         if (dsor_exp > 3)
 425                 dsor_exp = -EINVAL;
 426         if (dsor_exp < 0)
 427                 return dsor_exp;
 428
 429         regval = __raw_readw(DSP_CKCTL);
 430         regval &= ~(3 << clk->rate_offset);
 431         regval |= dsor_exp << clk->rate_offset;
 432         __raw_writew(regval, DSP_CKCTL);
 433         clk->rate = clk->parent->rate / (1 << dsor_exp);
 434
 435         return 0;
 436 }
 437
 438 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 439 {
 440         int dsor_exp = calc_dsor_exp(clk, rate);
 441         if (dsor_exp < 0)
 442                 return dsor_exp;
 443         if (dsor_exp > 3)
 444                 dsor_exp = 3;
 445         return clk->parent->rate / (1 << dsor_exp);
 446 }
 447
 448 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 449 {
 450         int dsor_exp;
 451         u16 regval;
 452
 453         dsor_exp = calc_dsor_exp(clk, rate);
 454         if (dsor_exp > 3)
 455                 dsor_exp = -EINVAL;
 456         if (dsor_exp < 0)
 457                 return dsor_exp;
 458
 459         regval = omap_readw(ARM_CKCTL);
 460         regval &= ~(3 << clk->rate_offset);
 461         regval |= dsor_exp << clk->rate_offset;
 462         regval = verify_ckctl_value(regval);
 463         omap_writew(regval, ARM_CKCTL);
 464         clk->rate = clk->parent->rate / (1 << dsor_exp);
 465         return 0;
 466 }
 467
 468 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 469 {
 470         /* Find the highest supported frequency <= rate */
 471         struct mpu_rate * ptr;
 472         long  highest_rate;
 473
 474         if (clk != &virtual_ck_mpu)
 475                 return -EINVAL;
 476
 477         highest_rate = -EINVAL;
 478
 479         for (ptr = rate_table; ptr->rate; ptr++) {
 480                 if (ptr->xtal != ck_ref.rate)
 481                         continue;
 482
 483                 highest_rate = ptr->rate;
 484
 485                 /* Can check only after xtal frequency check */
 486                 if (ptr->rate <= rate)
 487                         break;
 488         }
 489
 490         return highest_rate;
 491 }
 492
 493 static unsigned calc_ext_dsor(unsigned long rate)
 494 {
 495         unsigned dsor;
 496
 497         /* MCLK and BCLK divisor selection is not linear:
 498          * freq = 96MHz / dsor
 499          *
 500          * RATIO_SEL range: dsor <-> RATIO_SEL
 501          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 502          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 503          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 504          * can not be used.
 505          */
 506         for (dsor = 2; dsor < 96; ++dsor) {
 507                 if ((dsor & 1) && dsor > 8)
 508                         continue;
 509                 if (rate >= 96000000 / dsor)
 510                         break;
 511         }
 512         return dsor;
 513 }
 514
 515 /* Only needed on 1510 */
 516 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 517 {
 518         unsigned int val;
 519
 520         val = omap_readl(clk->enable_reg);
 521         if (rate == 12000000)
 522                 val &= ~(1 << clk->enable_bit);
 523         else if (rate == 48000000)
 524                 val |= (1 << clk->enable_bit);
 525         else
 526                 return -EINVAL;
 527         omap_writel(val, clk->enable_reg);
 528         clk->rate = rate;
 529
 530         return 0;
 531 }
 532
 533 /* External clock (MCLK & BCLK) functions */
 534 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 535 {
 536         unsigned dsor;
 537         __u16 ratio_bits;
 538
 539         dsor = calc_ext_dsor(rate);
 540         clk->rate = 96000000 / dsor;
 541         if (dsor > 8)
 542                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 543         else
 544                 ratio_bits = (dsor - 2) << 2;
 545
 546         ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
 547         omap_writew(ratio_bits, clk->enable_reg);
 548
 549         return 0;
 550 }
 551
 552 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 553 {
 554         u32 l;
 555         int div;
 556         unsigned long p_rate;
 557
 558         p_rate = clk->parent->rate;
 559         /* Round towards slower frequency */
 560         div = (p_rate + rate - 1) / rate;
 561         div--;
 562         if (div < 0 || div > 7)
 563                 return -EINVAL;
 564
 565         l = omap_readl(MOD_CONF_CTRL_1);
 566         l &= ~(7 << 17);
 567         l |= div << 17;
 568         omap_writel(l, MOD_CONF_CTRL_1);
 569
 570         clk->rate = p_rate / (div + 1);
 571
 572         return 0;
 573 }
 574
 575 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 576 {
 577         return 96000000 / calc_ext_dsor(rate);
 578 }
 579
 580 static void omap1_init_ext_clk(struct clk * clk)
 581 {
 582         unsigned dsor;
 583         __u16 ratio_bits;
 584
 585         /* Determine current rate and ensure clock is based on 96MHz APLL */
 586         ratio_bits = omap_readw(clk->enable_reg) & ~1;
 587         omap_writew(ratio_bits, clk->enable_reg);
 588
 589         ratio_bits = (ratio_bits & 0xfc) >> 2;
 590         if (ratio_bits > 6)
 591                 dsor = (ratio_bits - 6) * 2 + 8;
 592         else
 593                 dsor = ratio_bits + 2;
 594
 595         clk-> rate = 96000000 / dsor;
 596 }
 597
 598 static int omap1_clk_enable(struct clk *clk)
 599 {
 600         int ret = 0;
 601         if (clk->usecount++ == 0) {
 602                 if (likely(clk->parent)) {
 603                         ret = omap1_clk_enable(clk->parent);
 604
 605                         if (unlikely(ret != 0)) {
 606                                 clk->usecount--;
 607                                 return ret;
 608                         }
 609
 610                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 611                                 omap1_clk_deny_idle(clk->parent);
 612                 }
 613
 614                 ret = clk->ops->enable(clk);
 615
 616                 if (unlikely(ret != 0) && clk->parent) {
 617                         omap1_clk_disable(clk->parent);
 618                         clk->usecount--;
 619                 }
 620         }
 621
 622         return ret;
 623 }
 624
 625 static void omap1_clk_disable(struct clk *clk)
 626 {
 627         if (clk->usecount > 0 && !(--clk->usecount)) {
 628                 clk->ops->disable(clk);
 629                 if (likely(clk->parent)) {
 630                         omap1_clk_disable(clk->parent);
 631                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 632                                 omap1_clk_allow_idle(clk->parent);
 633                 }
 634         }
 635 }
 636
 637 static int omap1_clk_enable_generic(struct clk *clk)
 638 {
 639         __u16 regval16;
 640         __u32 regval32;
 641
 642         if (unlikely(clk->enable_reg == NULL)) {
 643                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 644                        clk->name);
 645                 return -EINVAL;
 646         }
 647
 648         if (clk->flags & ENABLE_REG_32BIT) {
 649                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 650                         regval32 = __raw_readl(clk->enable_reg);
 651                         regval32 |= (1 << clk->enable_bit);
 652                         __raw_writel(regval32, clk->enable_reg);
 653                 } else {
 654                         regval32 = omap_readl(clk->enable_reg);
 655                         regval32 |= (1 << clk->enable_bit);
 656                         omap_writel(regval32, clk->enable_reg);
 657                 }
 658         } else {
 659                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 660                         regval16 = __raw_readw(clk->enable_reg);
 661                         regval16 |= (1 << clk->enable_bit);
 662                         __raw_writew(regval16, clk->enable_reg);
 663                 } else {
 664                         regval16 = omap_readw(clk->enable_reg);
 665                         regval16 |= (1 << clk->enable_bit);
 666                         omap_writew(regval16, clk->enable_reg);
 667                 }
 668         }
 669
 670         return 0;
 671 }
 672
 673 static void omap1_clk_disable_generic(struct clk *clk)
 674 {
 675         __u16 regval16;
 676         __u32 regval32;
 677
 678         if (clk->enable_reg == NULL)
 679                 return;
 680
 681         if (clk->flags & ENABLE_REG_32BIT) {
 682                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 683                         regval32 = __raw_readl(clk->enable_reg);
 684                         regval32 &= ~(1 << clk->enable_bit);
 685                         __raw_writel(regval32, clk->enable_reg);
 686                 } else {
 687                         regval32 = omap_readl(clk->enable_reg);
 688                         regval32 &= ~(1 << clk->enable_bit);
 689                         omap_writel(regval32, clk->enable_reg);
 690                 }
 691         } else {
 692                 if (clk->flags & VIRTUAL_IO_ADDRESS) {
 693                         regval16 = __raw_readw(clk->enable_reg);
 694                         regval16 &= ~(1 << clk->enable_bit);
 695                         __raw_writew(regval16, clk->enable_reg);
 696                 } else {
 697                         regval16 = omap_readw(clk->enable_reg);
 698                         regval16 &= ~(1 << clk->enable_bit);
 699                         omap_writew(regval16, clk->enable_reg);
 700                 }
 701         }
 702 }
 703
 704 static const struct clkops clkops_generic = {
 705         .enable         = &omap1_clk_enable_generic,
 706         .disable        = &omap1_clk_disable_generic,
 707 };
 708
 709 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 710 {
 711         if (clk->flags & RATE_FIXED)
 712                 return clk->rate;
 713
 714         if (clk->round_rate != NULL)
 715                 return clk->round_rate(clk, rate);
 716
 717         return clk->rate;
 718 }
 719
 720 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 721 {
 722         int  ret = -EINVAL;
 723
 724         if (clk->set_rate)
 725                 ret = clk->set_rate(clk, rate);
 726         return ret;
 727 }
 728
 729 /*-------------------------------------------------------------------------
 730  * Omap1 clock reset and init functions
 731  *-------------------------------------------------------------------------*/
 732
 733 #ifdef CONFIG_OMAP_RESET_CLOCKS
 734
 735 static void __init omap1_clk_disable_unused(struct clk *clk)
 736 {
 737         __u32 regval32;
 738
 739         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 740          * has not enabled any DSP clocks */
 741         if (clk->enable_reg == DSP_IDLECT2) {
 742                 printk(KERN_INFO "Skipping reset check for DSP domain "
 743                        "clock \"%s\"\n", clk->name);
 744                 return;
 745         }
 746
 747         /* Is the clock already disabled? */
 748         if (clk->flags & ENABLE_REG_32BIT) {
 749                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 750                         regval32 = __raw_readl(clk->enable_reg);
 751                         else
 752                                 regval32 = omap_readl(clk->enable_reg);
 753         } else {
 754                 if (clk->flags & VIRTUAL_IO_ADDRESS)
 755                         regval32 = __raw_readw(clk->enable_reg);
 756                 else
 757                         regval32 = omap_readw(clk->enable_reg);
 758         }
 759
 760         if ((regval32 & (1 << clk->enable_bit)) == 0)
 761                 return;
 762
 763         /* FIXME: This clock seems to be necessary but no-one
 764          * has asked for its activation. */
 765         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 766             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 767             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 768                 ) {
 769                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 770                        clk->name);
 771                 return;
 772         }
 773
 774         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 775         clk->ops->disable(clk);
 776         printk(" done\n");
 777 }
 778
 779 #else
 780 #define omap1_clk_disable_unused        NULL
 781 #endif
 782
 783 static struct clk_functions omap1_clk_functions = {
 784         .clk_enable             = omap1_clk_enable,
 785         .clk_disable            = omap1_clk_disable,
 786         .clk_round_rate         = omap1_clk_round_rate,
 787         .clk_set_rate           = omap1_clk_set_rate,
 788         .clk_disable_unused     = omap1_clk_disable_unused,
 789 };
 790
 791 int __init omap1_clk_init(void)
 792 {
 793         struct omap_clk *c;
 794         const struct omap_clock_config *info;
 795         int crystal_type = 0; /* Default 12 MHz */
 796         u32 reg, cpu_mask;
 797
 798 #ifdef CONFIG_DEBUG_LL
 799         /* Resets some clocks that may be left on from bootloader,
 800          * but leaves serial clocks on.
 801          */
 802         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 803 #endif
 804
 805         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 806         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 807         omap_writew(reg, SOFT_REQ_REG);
 808         if (!cpu_is_omap15xx())
 809                 omap_writew(0, SOFT_REQ_REG2);
 810
 811         clk_init(&omap1_clk_functions);
 812
 813         /* By default all idlect1 clocks are allowed to idle */
 814         arm_idlect1_mask = ~0;
 815
 816         cpu_mask = 0;
 817         if (cpu_is_omap16xx())
 818                 cpu_mask |= CK_16XX;
 819         if (cpu_is_omap1510())
 820                 cpu_mask |= CK_1510;
 821         if (cpu_is_omap730())
 822                 cpu_mask |= CK_730;
 823         if (cpu_is_omap310())
 824                 cpu_mask |= CK_310;
 825
 826         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 827                 if (c->cpu & cpu_mask) {
 828                         clkdev_add(&c->lk);
 829                         clk_register(c->lk.clk);
 830                 }
 831
 832         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 833         if (info != NULL) {
 834                 if (!cpu_is_omap15xx())
 835                         crystal_type = info->system_clock_type;
 836         }
 837
 838 #if defined(CONFIG_ARCH_OMAP730)
 839         ck_ref.rate = 13000000;
 840 #elif defined(CONFIG_ARCH_OMAP16XX)
 841         if (crystal_type == 2)
 842                 ck_ref.rate = 19200000;
 843 #endif
 844
 845         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 846                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 847                omap_readw(ARM_CKCTL));
 848
 849         /* We want to be in syncronous scalable mode */
 850         omap_writew(0x1000, ARM_SYSST);
 851
 852 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 853         /* Use values set by bootloader. Determine PLL rate and recalculate
 854          * dependent clocks as if kernel had changed PLL or divisors.
 855          */
 856         {
 857                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 858
 859                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 860                 if (pll_ctl_val & 0x10) {
 861                         /* PLL enabled, apply multiplier and divisor */
 862                         if (pll_ctl_val & 0xf80)
 863                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 864                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 865                 } else {
 866                         /* PLL disabled, apply bypass divisor */
 867                         switch (pll_ctl_val & 0xc) {
 868                         case 0:
 869                                 break;
 870                         case 0x4:
 871                                 ck_dpll1.rate /= 2;
 872                                 break;
 873                         default:
 874                                 ck_dpll1.rate /= 4;
 875                                 break;
 876                         }
 877                 }
 878         }
 879 #else
 880         /* Find the highest supported frequency and enable it */
 881         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 882                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 883                 /* Guess sane values (60MHz) */
 884                 omap_writew(0x2290, DPLL_CTL);
 885                 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 886                 ck_dpll1.rate = 60000000;
 887         }
 888 #endif
 889         propagate_rate(&ck_dpll1);
 890         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 891         propagate_rate(&ck_ref);
 892         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 893                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 894                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 895                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 896                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 897
 898 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 899         /* Select slicer output as OMAP input clock */
 900         omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 901 #endif
 902
 903         /* Amstrad Delta wants BCLK high when inactive */
 904         if (machine_is_ams_delta())
 905                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 906                                 (1 << SDW_MCLK_INV_BIT),
 907                                 ULPD_CLOCK_CTRL);
 908
 909         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 910         /* (on 730, bit 13 must not be cleared) */
 911         if (cpu_is_omap730())
 912                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 913         else
 914                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 915
 916         /* Put DSP/MPUI into reset until needed */
 917         omap_writew(0, ARM_RSTCT1);
 918         omap_writew(1, ARM_RSTCT2);
 919         omap_writew(0x400, ARM_IDLECT1);
 920
 921         /*
 922          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 923          * of the ARM_IDLECT2 register must be set to zero. The power-on
 924          * default value of this bit is one.
 925          */
 926         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 927
 928         /*
 929          * Only enable those clocks we will need, let the drivers
 930          * enable other clocks as necessary
 931          */
 932         clk_enable(&armper_ck.clk);
 933         clk_enable(&armxor_ck.clk);
 934         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 935
 936         if (cpu_is_omap15xx())
 937                 clk_enable(&arm_gpio_ck);
 938
 939         return 0;
 940 }