*
*/
+/* Common registers for 24xx and 34xx in OCP_MOD */
+#define OMAP2_PRM_IRQSTATUS_MPU_OFFSET 0x0018
+#define OMAP2_PRM_IRQENABLE_MPU_OFFSET 0x001c
+
/* 24xx register offsets in OCP_MOD */
-#define OMAP24XX_PRCM_REVISION_OFFSET 0x0000
-#define OMAP24XX_PRCM_SYSCONFIG_OFFSET 0x0010
-#define OMAP24XX_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP24XX_PRCM_IRQENABLE_MPU_OFFSET 0x001c
+#define OMAP24XX_PRM_REVISION_OFFSET 0x0000
+#define OMAP24XX_PRM_SYSCONFIG_OFFSET 0x0010
+
+/* 34xx register offsets in OCP_MOD */
+#define OMAP3430_PRM_REVISION_OFFSET 0x0004
+#define OMAP3430_PRM_SYSCONFIG_OFFSET 0x0014
/* 24xx register offsets in OMAP24XX_GR_MOD (Same as OCP_MOD for 24xx) */
#define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050
#define OMAP24XX_PRCM_CLKSSETUP_OFFSET 0x0094
#define OMAP24XX_PRCM_POLCTRL_OFFSET 0x0098
-/* 34xx register offsets in OCP_MOD */
-#define OMAP3430_PRM_REVISION_OFFSET 0x0004
-#define OMAP3430_PRM_SYSCONFIG_OFFSET 0x0014
-#define OMAP3430_PRM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP3430_PRM_IRQENABLE_MPU_OFFSET 0x001c
-
/* 34xx register offsets in GR_MOD */
#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024