OMAP clock: drop RATE_FIXED

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 08789c8997fcf2f7eb1681599e960d41934fe989..179ea1774d705b996a706ce487f5bc1f032189a4 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -27,8 +27,10 @@
 #include "prm.h"
 #include "prm-regbits-34xx.h"
 
-static void omap3_dpll_recalc(struct clk *clk);
-static void omap3_clkoutx2_recalc(struct clk *clk);
+static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
+                             u8 rate_storage);
+static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
+                             u8 rate_storage);
 static void omap3_dpll_allow_idle(struct clk *clk);
 static void omap3_dpll_deny_idle(struct clk *clk);
 static u32 omap3_dpll_autoidle_read(struct clk *clk);
@@ -64,74 +66,58 @@ static struct clk dpll2_fck;
 static struct clk omap_32k_fck = {
        .name           = "omap_32k_fck",
        .rate           = 32768,
-       .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 static struct clk secure_32k_fck = {
        .name           = "secure_32k_fck",
        .rate           = 32768,
-       .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 /* Virtual source clocks for osc_sys_ck */
 static struct clk virt_12m_ck = {
        .name           = "virt_12m_ck",
        .rate           = 12000000,
-       .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 static struct clk virt_13m_ck = {
        .name           = "virt_13m_ck",
        .rate           = 13000000,
-       .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 static struct clk virt_16_8m_ck = {
        .name           = "virt_16_8m_ck",
        .rate           = 16800000,
-       .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP3430ES2 | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 static struct clk virt_19_2m_ck = {
        .name           = "virt_19_2m_ck",
        .rate           = 19200000,
-       .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 static struct clk virt_26m_ck = {
        .name           = "virt_26m_ck",
        .rate           = 26000000,
-       .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 static struct clk virt_38_4m_ck = {
        .name           = "virt_38_4m_ck",
        .rate           = 38400000,
-       .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 static const struct clksel_rate osc_sys_12m_rates[] = {
@@ -184,8 +170,7 @@ static struct clk osc_sys_ck = {
        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
        .clksel         = osc_sys_clksel,
        /* REVISIT: deal with autoextclkmode? */
-       .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
-                               ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -211,16 +196,15 @@ static struct clk sys_ck = {
        .clksel_reg     = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
        .clksel         = sys_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk sys_altclk = {
        .name           = "sys_altclk",
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "cm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 /*
@@ -230,9 +214,8 @@ static struct clk sys_altclk = {
  */
 static struct clk mcbsp_clks = {
        .name           = "mcbsp_clks",
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
-       .recalc         = &propagate_rate,
 };
 
 /* PRM EXTERNAL CLOCK OUTPUT */
@@ -292,6 +275,7 @@ static struct dpll_data dpll1_dd = {
        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .bypass_clk     = &dpll1_fck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -301,7 +285,7 @@ static struct clk dpll1_ck = {
        .parent         = &sys_ck,
        .prcm_mod       = MPU_MOD,
        .dpll_data      = &dpll1_dd,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
        .clkdm          = { .name = "dpll1_clkdm" },
@@ -315,8 +299,7 @@ static struct clk dpll1_ck = {
 static struct clk dpll1_x2_ck = {
        .name           = "dpll1_x2_ck",
        .parent         = &dpll1_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll1_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -339,8 +322,7 @@ static struct clk dpll1_x2m2_ck = {
        .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll1_x2m2_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll1_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -367,6 +349,7 @@ static struct dpll_data dpll2_dd = {
        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
        .bypass_clk     = &dpll2_fck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -376,7 +359,7 @@ static struct clk dpll2_ck = {
        .parent         = &sys_ck,
        .prcm_mod       = OMAP3430_IVA2_MOD,
        .dpll_data      = &dpll2_dd,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+       .flags          = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
        .enable         = &omap3_noncore_dpll_enable,
        .disable        = &omap3_noncore_dpll_disable,
        .round_rate     = &omap2_dpll_round_rate,
@@ -402,8 +385,7 @@ static struct clk dpll2_m2_ck = {
        .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll2_m2x2_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll2_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -429,6 +411,7 @@ static struct dpll_data dpll3_dd = {
        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -438,7 +421,7 @@ static struct clk dpll3_ck = {
        .parent         = &sys_ck,
        .prcm_mod       = PLL_MOD,
        .dpll_data      = &dpll3_dd,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
        .round_rate     = &omap2_dpll_round_rate,
        .clkdm          = { .name = "dpll3_clkdm" },
        .recalc         = &omap3_dpll_recalc,
@@ -451,8 +434,7 @@ static struct clk dpll3_ck = {
 static struct clk dpll3_x2_ck = {
        .name           = "dpll3_x2_ck",
        .parent         = &dpll3_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll3_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -506,8 +488,7 @@ static struct clk dpll3_m2_ck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div31_dpll3m2_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll3_clkdm" },
        .round_rate     = &omap2_clksel_round_rate,
        .set_rate       = &omap3_core_dpll_m2_set_rate,
@@ -517,8 +498,7 @@ static struct clk dpll3_m2_ck = {
 static struct clk core_ck = {
        .name           = "core_ck",
        .parent         = &dpll3_m2_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -526,8 +506,7 @@ static struct clk core_ck = {
 static struct clk dpll3_m2x2_ck = {
        .name           = "dpll3_m2x2_ck",
        .parent         = &dpll3_x2_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll3_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -547,8 +526,7 @@ static struct clk dpll3_m3_ck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
        .clksel         = div16_dpll3_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll3_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -560,7 +538,7 @@ static struct clk dpll3_m3x2_ck = {
        .prcm_mod       = PLL_MOD,
        .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+       .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
        .clkdm          = { .name = "dpll3_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -568,8 +546,7 @@ static struct clk dpll3_m3x2_ck = {
 static struct clk emu_core_alwon_ck = {
        .name           = "emu_core_alwon_ck",
        .parent         = &dpll3_m3x2_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll3_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -594,6 +571,7 @@ static struct dpll_data dpll4_dd = {
        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -603,7 +581,7 @@ static struct clk dpll4_ck = {
        .parent         = &sys_ck,
        .prcm_mod       = PLL_MOD,
        .dpll_data      = &dpll4_dd,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+       .flags          = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
        .enable         = &omap3_noncore_dpll_enable,
        .disable        = &omap3_noncore_dpll_disable,
        .round_rate     = &omap2_dpll_round_rate,
@@ -620,8 +598,7 @@ static struct clk dpll4_ck = {
 static struct clk dpll4_x2_ck = {
        .name           = "dpll4_x2_ck",
        .parent         = &dpll4_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -640,8 +617,7 @@ static struct clk dpll4_m2_ck = {
        .clksel_reg     = OMAP3430_CM_CLKSEL3,
        .clksel_mask    = OMAP3430_DIV_96M_MASK,
        .clksel         = div16_dpll4_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -653,7 +629,7 @@ static struct clk dpll4_m2x2_ck = {
        .prcm_mod       = PLL_MOD,
        .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+       .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -667,8 +643,7 @@ static struct clk dpll4_m2x2_ck = {
 static struct clk omap_96m_alwon_fck = {
        .name           = "omap_96m_alwon_fck",
        .parent         = &dpll4_m2x2_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -676,8 +651,7 @@ static struct clk omap_96m_alwon_fck = {
 static struct clk cm_96m_fck = {
        .name           = "cm_96m_fck",
        .parent         = &omap_96m_alwon_fck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -706,8 +680,7 @@ static struct clk omap_96m_fck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
        .clksel         = omap_96m_fck_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -721,8 +694,7 @@ static struct clk dpll4_m3_ck = {
        .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
        .clksel         = div16_dpll4_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -735,7 +707,7 @@ static struct clk dpll4_m3x2_ck = {
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+       .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -763,8 +735,7 @@ static struct clk omap_54m_fck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
        .clksel         = omap_54m_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -792,8 +763,7 @@ static struct clk omap_48m_fck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
        .clksel         = omap_48m_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -802,8 +772,7 @@ static struct clk omap_12m_fck = {
        .name           = "omap_12m_fck",
        .parent         = &omap_48m_fck,
        .fixed_div      = 4,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &omap2_fixed_divisor_recalc,
 };
@@ -817,10 +786,11 @@ static struct clk dpll4_m4_ck = {
        .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
        .clksel         = div16_dpll4_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
 };
 
 /* The PWRDN bit is apparently only available on 3430ES2 and above */
@@ -830,7 +800,7 @@ static struct clk dpll4_m4x2_ck = {
        .prcm_mod       = PLL_MOD,
        .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+       .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -844,8 +814,7 @@ static struct clk dpll4_m5_ck = {
        .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
        .clksel         = div16_dpll4_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -857,7 +826,7 @@ static struct clk dpll4_m5x2_ck = {
        .prcm_mod       = PLL_MOD,
        .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+       .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -871,8 +840,7 @@ static struct clk dpll4_m6_ck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
        .clksel         = div16_dpll4_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -885,7 +853,7 @@ static struct clk dpll4_m6x2_ck = {
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+       .flags          = CLOCK_IN_OMAP343X | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -893,8 +861,7 @@ static struct clk dpll4_m6x2_ck = {
 static struct clk emu_per_alwon_ck = {
        .name           = "emu_per_alwon_ck",
        .parent         = &dpll4_m6x2_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll4_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -920,6 +887,7 @@ static struct dpll_data dpll5_dd = {
        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+       .min_divider    = 1,
        .max_divider    = OMAP3_MAX_DPLL_DIV,
        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -929,7 +897,7 @@ static struct clk dpll5_ck = {
        .parent         = &sys_ck,
        .prcm_mod       = PLL_MOD,
        .dpll_data      = &dpll5_dd,
-       .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+       .flags          = CLOCK_IN_OMAP3430ES2 | RECALC_ON_ENABLE,
        .enable         = &omap3_noncore_dpll_enable,
        .disable        = &omap3_noncore_dpll_disable,
        .round_rate     = &omap2_dpll_round_rate,
@@ -951,8 +919,7 @@ static struct clk dpll5_m2_ck = {
        .clksel_reg     = OMAP3430ES2_CM_CLKSEL5,
        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
        .clksel         = div16_dpll5_clksel,
-       .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "dpll5_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -996,7 +963,7 @@ static struct clk clkout2_src_ck = {
        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
        .clksel         = clkout2_src_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+       .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1032,8 +999,7 @@ static struct clk sys_clkout2 = {
 static struct clk corex2_fck = {
        .name           = "corex2_fck",
        .parent         = &dpll3_m2x2_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1060,8 +1026,7 @@ static struct clk dpll1_fck = {
        .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
        .clksel         = div4_core_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1069,8 +1034,7 @@ static struct clk dpll1_fck = {
 static struct clk mpu_ck = {
        .name           = "mpu_ck",
        .parent         = &dpll1_x2m2_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "mpu_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1095,8 +1059,7 @@ static struct clk arm_fck = {
        .clksel_reg     = OMAP3430_CM_IDLEST_PLL,
        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .clksel         = arm_fck_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "mpu_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1110,8 +1073,7 @@ static struct clk arm_fck = {
 static struct clk emu_mpu_alwon_ck = {
        .name           = "emu_mpu_alwon_ck",
        .parent         = &mpu_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "mpu_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1124,8 +1086,7 @@ static struct clk dpll2_fck = {
        .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
        .clksel         = div4_core_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "cm_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1137,7 +1098,7 @@ static struct clk iva2_ck = {
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+       .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "iva2_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1157,8 +1118,7 @@ static struct clk l3_ick = {
        .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
        .clksel         = div2_core_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l3_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1176,8 +1136,7 @@ static struct clk l4_ick = {
        .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
        .clksel         = div2_l3_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 
@@ -1231,8 +1190,7 @@ static struct clk gfx_l3_fck = {
        .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
        .clksel         = gfx_l3_clksel,
-       .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "gfx_3430es1_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1403,8 +1361,7 @@ static struct clk usbtll_fck = {
 static struct clk core_96m_fck = {
        .name           = "core_96m_fck",
        .parent         = &omap_96m_fck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1575,8 +1532,7 @@ static struct clk mcbsp1_fck = {
 static struct clk core_48m_fck = {
        .name           = "core_48m_fck",
        .parent         = &omap_48m_fck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1675,8 +1631,7 @@ static struct clk fshostusb_fck = {
 static struct clk core_12m_fck = {
        .name           = "core_12m_fck",
        .parent         = &omap_12m_fck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1719,7 +1674,7 @@ static struct clk ssi_ssr_fck_3430es1 = {
        .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
        .clksel         = ssi_ssr_clksel,
-       .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
+       .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1734,7 +1689,7 @@ static struct clk ssi_ssr_fck_3430es2 = {
        .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
        .clksel         = ssi_ssr_clksel,
-       .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | WAIT_READY,
+       .flags          = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -1769,8 +1724,7 @@ static struct clk ssi_sst_fck_3430es2 = {
 static struct clk core_l3_ick = {
        .name           = "core_l3_ick",
        .parent         = &l3_ick,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l3_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1824,8 +1778,7 @@ static struct clk gpmc_fck = {
 static struct clk security_l3_ick = {
        .name           = "security_l3_ick",
        .parent         = &l3_ick,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l3_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -1847,8 +1800,7 @@ static struct clk pka_ick = {
 static struct clk core_l4_ick = {
        .name           = "core_l4_ick",
        .parent         = &l4_ick,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2182,8 +2134,7 @@ static struct clk omapctrl_ick = {
 static struct clk ssi_l4_ick = {
        .name           = "ssi_l4_ick",
        .parent         = &l4_ick,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2243,8 +2194,7 @@ static struct clk usb_l4_ick = {
 static struct clk security_l4_ick2 = {
        .name           = "security_l4_ick2",
        .parent         = &l4_ick,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "core_l4_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2514,7 +2464,7 @@ static struct clk gpt1_fck = {
 static struct clk wkup_32k_fck = {
        .name           = "wkup_32k_fck",
        .parent         = &omap_32k_fck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2546,7 +2496,7 @@ static struct clk wdt2_fck = {
 static struct clk wkup_l4_ick = {
        .name           = "wkup_l4_ick",
        .parent         = &sys_ck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2642,8 +2592,7 @@ static struct clk gpt1_ick = {
 static struct clk per_96m_fck = {
        .name           = "per_96m_fck",
        .parent         = &omap_96m_alwon_fck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "per_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2651,8 +2600,7 @@ static struct clk per_96m_fck = {
 static struct clk per_48m_fck = {
        .name           = "per_48m_fck",
        .parent         = &omap_48m_fck,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "per_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -2793,7 +2741,7 @@ static struct clk per_32k_alwon_fck = {
        .name           = "per_32k_alwon_fck",
        .parent         = &omap_32k_fck,
        .clkdm          = { .name = "per_clkdm" },
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .recalc         = &followparent_recalc,
 };
 
@@ -2872,8 +2820,7 @@ static struct clk wdt3_fck = {
 static struct clk per_l4_ick = {
        .name           = "per_l4_ick",
        .parent         = &l4_ick,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
-                               PARENT_CONTROLS_CLOCK,
+       .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
        .clkdm          = { .name = "per_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -3225,7 +3172,7 @@ static struct clk emu_src_ck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
        .clksel         = emu_src_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "emu_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -3250,7 +3197,7 @@ static struct clk pclk_fck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
        .clksel         = pclk_emu_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "emu_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -3274,7 +3221,7 @@ static struct clk pclkx2_fck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
        .clksel         = pclkx2_emu_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "emu_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -3291,7 +3238,7 @@ static struct clk atclk_fck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
        .clksel         = atclk_emu_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "emu_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -3303,7 +3250,7 @@ static struct clk traceclk_src_fck = {
        .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
        .clksel         = emu_src_clksel,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+       .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
        .clkdm          = { .name = "emu_clkdm" },
        .recalc         = &omap2_clksel_recalc,
 };
@@ -3342,7 +3289,7 @@ static struct clk sr1_fck = {
        .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
        .idlest_bit     = OMAP3430_ST_SR1_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
+       .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
        .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };
@@ -3355,7 +3302,7 @@ static struct clk sr2_fck = {
        .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
        .idlest_bit     = OMAP3430_ST_SR2_SHIFT,
-       .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | WAIT_READY,
+       .flags          = CLOCK_IN_OMAP343X | WAIT_READY,
        .clkdm          = { .name = "prm_clkdm" },
        .recalc         = &followparent_recalc,
 };