OMAP clock: drop RATE_FIXED

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock.c

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 8a064b3d1d93211afa9f13e91029800c05c18543..31b5c9dc06631f6969e710ef490ed5d4e3c72458 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -224,7 +224,11 @@ void omap2_init_clksel_parent(struct clk *clk)
                                                 clk->name, clks->parent->name,
                                                 ((clk->parent) ?
                                                  clk->parent->name : "NULL"));
+                                       if (clk->parent)
+                                               omap_clk_del_child(clk->parent,
+                                                                  clk);
                                        clk->parent = clks->parent;
+                                       omap_clk_add_child(clk->parent, clk);
                                };
                                found = 1;
                        }
@@ -241,6 +245,7 @@ void omap2_init_clksel_parent(struct clk *clk)
 /**
  * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
  * @clk: struct clk * of a DPLL
+ * @parent_rate: rate of the parent of the DPLL clock
  *
  * DPLLs can be locked or bypassed - basically, enabled or disabled.
  * When locked, the DPLL output depends on the M and N values.  When
@@ -252,7 +257,7 @@ void omap2_init_clksel_parent(struct clk *clk)
  * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
  * if the clock @clk is not a DPLL.
  */
-u32 omap2_get_dpll_rate(struct clk *clk)
+u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate)
 {
        long long dpll_clk;
        u32 dpll_mult, dpll_div, v;
@@ -271,7 +276,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 
                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                       return clk->parent->rate;
+                       return parent_rate;
 
        } else if (cpu_is_omap34xx()) {
 
@@ -287,7 +292,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
        dpll_div = v & dd->div1_mask;
        dpll_div >>= __ffs(dd->div1_mask);
 
-       dpll_clk = (long long)clk->parent->rate * dpll_mult;
+       dpll_clk = (long long)parent_rate * dpll_mult;
        do_div(dpll_clk, dpll_div + 1);
 
        return dpll_clk;
@@ -297,14 +302,19 @@ u32 omap2_get_dpll_rate(struct clk *clk)
  * Used for clocks that have the same value as the parent clock,
  * divided by some factor
  */
-void omap2_fixed_divisor_recalc(struct clk *clk)
+void omap2_fixed_divisor_recalc(struct clk *clk, unsigned long parent_rate,
+                               u8 rate_storage)
 {
-       WARN_ON(!clk->fixed_div);
+       unsigned long rate;
 
-       clk->rate = clk->parent->rate / clk->fixed_div;
+       WARN_ON(!clk->fixed_div); /* XXX move this to init */
 
-       if (clk->flags & RATE_PROPAGATES)
-               propagate_rate(clk);
+       rate = parent_rate / clk->fixed_div;
+
+       if (rate_storage == CURRENT_RATE)
+               clk->rate = rate;
+       else if (rate_storage == TEMP_RATE)
+               clk->temp_rate = rate;
 }
 
 /**
@@ -491,9 +501,11 @@ int omap2_clk_enable(struct clk *clk)
  * Used for clocks that are part of CLKSEL_xyz governed clocks.
  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
  */
-void omap2_clksel_recalc(struct clk *clk)
+void omap2_clksel_recalc(struct clk *clk, unsigned long parent_rate,
+                        u8 rate_storage)
 {
        u32 div = 0;
+       unsigned long rate;
 
        pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
 
@@ -501,14 +513,14 @@ void omap2_clksel_recalc(struct clk *clk)
        if (div == 0)
                return;
 
-       if (clk->rate == (clk->parent->rate / div))
-               return;
-       clk->rate = clk->parent->rate / div;
+       rate = parent_rate / div;
 
-       pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
+       if (rate_storage == CURRENT_RATE)
+               clk->rate = rate;
+       else if (rate_storage == TEMP_RATE)
+               clk->temp_rate = rate;
 
-       if (clk->flags & RATE_PROPAGATES)
-               propagate_rate(clk);
+       pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
 }
 
 /**
@@ -632,10 +644,6 @@ long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
        if (clk->round_rate != NULL)
                return clk->round_rate(clk, rate);
 
-       if (clk->flags & RATE_FIXED)
-               printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
-                      "on fixed-rate clock %s\n", clk->name);
-
        return clk->rate;
 }
 
@@ -779,9 +787,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
        if (clk->set_rate != NULL)
                ret = clk->set_rate(clk, rate);
 
-       if (ret == 0 && (clk->flags & RATE_PROPAGATES))
-               propagate_rate(clk);
-
        return ret;
 }
 
@@ -863,9 +868,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
                 clk->name, clk->parent->name, clk->rate);
 
-       if (clk->flags & RATE_PROPAGATES)
-               propagate_rate(clk);
-
        return 0;
 }