drivers/video/omap/lcdc.c

   1 /*
   2  * File: drivers/video/omap/omap1/lcdc.c
   3  *
   4  * OMAP1 internal LCD controller
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Author: Imre Deak <imre.deak@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, write to the Free Software Foundation, Inc.,
  21  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  22  */
  23
  24 #include <linux/config.h>
  25 #include <linux/module.h>
  26 #include <linux/device.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/err.h>
  30 #include <linux/mm.h>
  31 #include <linux/fb.h>
  32 #include <linux/dma-mapping.h>
  33
  34 #include <asm/arch/dma.h>
  35 #include <asm/arch/omapfb.h>
  36
  37 #include <asm/mach-types.h>
  38 #include <asm/hardware/clock.h>
  39
  40 /* #define OMAPFB_DBG 2 */
  41
  42 #include "debug.h"
  43
  44 #define MODULE_NAME                     "omapfb-lcdc"
  45
  46 #define OMAP_LCDC_BASE                  0xfffec000
  47 #define OMAP_LCDC_SIZE                  256
  48 #define OMAP_LCDC_IRQ                   INT_LCD_CTRL
  49
  50 #define OMAP_LCDC_CONTROL               (OMAP_LCDC_BASE + 0x00)
  51 #define OMAP_LCDC_TIMING0               (OMAP_LCDC_BASE + 0x04)
  52 #define OMAP_LCDC_TIMING1               (OMAP_LCDC_BASE + 0x08)
  53 #define OMAP_LCDC_TIMING2               (OMAP_LCDC_BASE + 0x0c)
  54 #define OMAP_LCDC_STATUS                (OMAP_LCDC_BASE + 0x10)
  55 #define OMAP_LCDC_SUBPANEL              (OMAP_LCDC_BASE + 0x14)
  56 #define OMAP_LCDC_LINE_INT              (OMAP_LCDC_BASE + 0x18)
  57 #define OMAP_LCDC_DISPLAY_STATUS        (OMAP_LCDC_BASE + 0x1c)
  58
  59 #define OMAP_LCDC_STAT_DONE             (1 << 0)
  60 #define OMAP_LCDC_STAT_VSYNC            (1 << 1)
  61 #define OMAP_LCDC_STAT_SYNC_LOST        (1 << 2)
  62 #define OMAP_LCDC_STAT_ABC              (1 << 3)
  63 #define OMAP_LCDC_STAT_LINE_INT         (1 << 4)
  64 #define OMAP_LCDC_STAT_FUF              (1 << 5)
  65 #define OMAP_LCDC_STAT_LOADED_PALETTE   (1 << 6)
  66
  67 #define OMAP_LCDC_CTRL_LCD_EN           (1 << 0)
  68 #define OMAP_LCDC_CTRL_LCD_TFT          (1 << 7)
  69 #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
  70
  71 #define OMAP_LCDC_IRQ_VSYNC             (1 << 2)
  72 #define OMAP_LCDC_IRQ_DONE              (1 << 3)
  73 #define OMAP_LCDC_IRQ_LOADED_PALETTE    (1 << 4)
  74 #define OMAP_LCDC_IRQ_LINE_NIRQ         (1 << 5)
  75 #define OMAP_LCDC_IRQ_LINE              (1 << 6)
  76 #define OMAP_LCDC_IRQ_MASK              (((1 << 5) - 1) << 2)
  77
  78 #define MAX_PALETTE_SIZE                PAGE_SIZE
  79
  80 #define pr_err(fmt, args...) printk(KERN_ERR MODULE_NAME ": " fmt, ## args)
  81
  82 enum lcdc_load_mode {
  83         OMAP_LCDC_LOAD_PALETTE,
  84         OMAP_LCDC_LOAD_FRAME,
  85         OMAP_LCDC_LOAD_PALETTE_AND_FRAME
  86 };
  87
  88 static struct omap_lcd_controller {
  89         enum omapfb_update_mode update_mode;
  90
  91         unsigned long           frame_offset;
  92         int                     screen_width;
  93
  94         enum omapfb_color_format        color_mode;
  95         int                     bpp;
  96         int                     palette_org;
  97         int                     palette_code;
  98         int                     palette_size;
  99
 100         unsigned int            irq_mask;
 101         struct completion       last_frame_complete;
 102         struct completion       palette_load_complete;
 103         struct clk              *lcd_ck;
 104         struct omapfb_device    *fbdev;
 105
 106         dma_addr_t              vram_phys;
 107         void                    *vram_virt;
 108         unsigned long           vram_size;
 109 } omap_lcdc;
 110
 111 static void inline enable_irqs(int mask)
 112 {
 113         omap_lcdc.irq_mask |= mask;
 114 }
 115
 116 static void inline disable_irqs(int mask)
 117 {
 118         omap_lcdc.irq_mask &= ~mask;
 119 }
 120
 121 static void set_load_mode(enum lcdc_load_mode mode)
 122 {
 123         u32 l;
 124
 125         l = omap_readl(OMAP_LCDC_CONTROL);
 126         l &= ~(3 << 20);
 127         switch (mode) {
 128         case OMAP_LCDC_LOAD_PALETTE:
 129                 l |= 1 << 20;
 130                 break;
 131         case OMAP_LCDC_LOAD_FRAME:
 132                 l |= 2 << 20;
 133                 break;
 134         case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
 135                 break;
 136         default:
 137                 BUG();
 138         }
 139         omap_writel(l, OMAP_LCDC_CONTROL);
 140 }
 141
 142 static void enable_controller(void)
 143 {
 144         u32 l;
 145
 146         l = omap_readl(OMAP_LCDC_CONTROL);
 147         l |= OMAP_LCDC_CTRL_LCD_EN;
 148         l &= ~OMAP_LCDC_IRQ_MASK;
 149         l |= omap_lcdc.irq_mask | OMAP_LCDC_IRQ_DONE;   /* enabled IRQs */
 150         omap_writel(l, OMAP_LCDC_CONTROL);
 151 }
 152
 153 static void disable_controller_async(void)
 154 {
 155         u32 l;
 156         u32 mask;
 157
 158         l = omap_readl(OMAP_LCDC_CONTROL);
 159         mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
 160         /* Preserve the DONE mask, since we still want to get the
 161          * final DONE irq. It will be disabled in the IRQ handler.
 162          */
 163         mask &= ~OMAP_LCDC_IRQ_DONE;
 164         l &= ~mask;
 165         omap_writel(l, OMAP_LCDC_CONTROL);
 166 }
 167
 168 static void disable_controller(void)
 169 {
 170         init_completion(&omap_lcdc.last_frame_complete);
 171         disable_controller_async();
 172         if (!wait_for_completion_timeout(&omap_lcdc.last_frame_complete,
 173                                 msecs_to_jiffies(500)))
 174                 pr_err("timeout waiting for FRAME DONE\n");
 175 }
 176
 177 static void reset_controller(u32 status)
 178 {
 179         static unsigned long reset_count = 0;
 180         static unsigned long last_jiffies = 0;
 181
 182         disable_controller_async();
 183         reset_count++;
 184         if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
 185                 pr_err("resetting (status %#010x,reset count %lu)\n",
 186                           status, reset_count);
 187                 last_jiffies = jiffies;
 188         }
 189         if (reset_count < 100) {
 190                 enable_controller();
 191         } else {
 192                 reset_count = 0;
 193                 pr_err("too many reset attempts, giving up.\n");
 194         }
 195 }
 196
 197 /* Configure the LCD DMA according to the current mode specified by parameters
 198  * in omap_lcdc.fbdev and fbdev->var.
 199  */
 200 static void setup_lcd_dma(void)
 201 {
 202         static const int dma_elem_type[] = {
 203                 0,
 204                 OMAP_DMA_DATA_TYPE_S8,
 205                 OMAP_DMA_DATA_TYPE_S16,
 206                 0,
 207                 OMAP_DMA_DATA_TYPE_S32,
 208         };
 209         struct fb_var_screeninfo *var = &omap_lcdc.fbdev->fb_info->var;
 210         struct lcd_panel *panel = omap_lcdc.fbdev->panel;
 211         unsigned long   src;
 212         int             esize, xelem, yelem;
 213
 214         src = omap_lcdc.vram_phys + PAGE_ALIGN(MAX_PALETTE_SIZE) +
 215                 omap_lcdc.frame_offset;
 216
 217         switch (var->rotate) {
 218         case 0:
 219                 esize = omap_lcdc.fbdev->mirror || (src & 3) ? 2 : 4;
 220                 xelem = panel->x_res * omap_lcdc.bpp / 8 / esize;
 221                 yelem = panel->y_res;
 222                 break;
 223         case 90:
 224         case 180:
 225         case 270:
 226                 if (cpu_is_omap15xx()) {
 227                         BUG();
 228                 }
 229                 esize = 2;
 230                 xelem = panel->y_res * omap_lcdc.bpp / 16;
 231                 yelem = panel->x_res;
 232                 break;
 233         default:
 234                 BUG();
 235                 return;
 236         }
 237         DBGPRINT(1, "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
 238                  src, esize, xelem, yelem);
 239         omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
 240         omap_set_lcd_dma_single_transfer(0);
 241         if (!cpu_is_omap15xx()) {
 242                 /* Set virtual xres elem size */
 243                 omap_set_lcd_dma_b1_vxres(
 244                         omap_lcdc.screen_width * omap_lcdc.bpp / 8 / esize);
 245                 /* Setup transformations */
 246                 omap_set_lcd_dma_b1_rotation(var->rotate);
 247                 omap_set_lcd_dma_b1_mirror(omap_lcdc.fbdev->mirror);
 248         }
 249         omap_setup_lcd_dma();
 250 }
 251
 252 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id, struct pt_regs *fp)
 253 {
 254         u32 status;
 255
 256         status = omap_readl(OMAP_LCDC_STATUS);
 257
 258         if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
 259                 reset_controller(status);
 260         else {
 261                 if (status & OMAP_LCDC_STAT_DONE) {
 262                         u32 l;
 263
 264                         /* Disable IRQ_DONE. The status bit will be cleared
 265                          * only when the controller is reenabled and we don't
 266                          * want to get more interrupts.
 267                          */
 268                         l = omap_readl(OMAP_LCDC_CONTROL);
 269                         l &= ~OMAP_LCDC_IRQ_DONE;
 270                         omap_writel(l, OMAP_LCDC_CONTROL);
 271                         complete(&omap_lcdc.last_frame_complete);
 272                 }
 273                 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
 274                         disable_controller_async();
 275                         complete(&omap_lcdc.palette_load_complete);
 276                 }
 277         }
 278
 279         /* Clear these interrupt status bits.
 280          * Sync_lost, FUF bits were cleared by disabling the LCD controller
 281          * LOADED_PALETTE can be cleared this way only in palette only
 282          * load mode. In other load modes it's cleared by disabling the
 283          * controller.
 284          */
 285         status &= ~(OMAP_LCDC_STAT_VSYNC |
 286                     OMAP_LCDC_STAT_LOADED_PALETTE |
 287                     OMAP_LCDC_STAT_ABC |
 288                     OMAP_LCDC_STAT_LINE_INT);
 289         omap_writel(status, OMAP_LCDC_STATUS);
 290         return IRQ_HANDLED;
 291 }
 292
 293 /* Change to a new video mode. We defer this to a later time to avoid any
 294  * flicker and not to mess up the current LCD DMA context. For this we disable
 295  * the LCD controler, which will generate a DONE irq after the last frame has
 296  * been transferred. Then it'll be safe to reconfigure both the LCD controller
 297  * as well as the LCD DMA.
 298  */
 299 static int omap_lcdc_setup_plane(int plane, int channel_out,
 300                                  unsigned long offset, int screen_width,
 301                                  int pos_x, int pos_y, int width, int height,
 302                                  int color_mode)
 303 {
 304         struct fb_var_screeninfo *var = &omap_lcdc.fbdev->fb_info->var;
 305         struct lcd_panel *panel = omap_lcdc.fbdev->panel;
 306         int rot_x, rot_y;
 307
 308         DBGENTER(1);
 309
 310         if (var->rotate == 0) {
 311                 rot_x = panel->x_res;
 312                 rot_y = panel->y_res;
 313         } else {
 314                 rot_x = panel->y_res;
 315                 rot_y = panel->x_res;
 316         }
 317         if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
 318             width != rot_x || height != rot_y) {
 319                 DBGPRINT(1, "invalid plane params plane %d pos_x %d "
 320                         "pos_y %d w %d h %d\n", plane, pos_x, pos_y,
 321                         width, height);
 322                 return -EINVAL;
 323         }
 324
 325         omap_lcdc.frame_offset = offset;
 326         omap_lcdc.screen_width = screen_width;
 327         omap_lcdc.color_mode = color_mode;
 328
 329         switch (color_mode) {
 330         case OMAPFB_COLOR_CLUT_8BPP:
 331                 omap_lcdc.bpp = 8;
 332                 omap_lcdc.palette_code = 0x3000;
 333                 omap_lcdc.palette_size = 512;
 334                 break;
 335         case OMAPFB_COLOR_RGB565:
 336                 omap_lcdc.bpp = 16;
 337                 omap_lcdc.palette_code = 0x4000;
 338                 omap_lcdc.palette_size = 32;
 339                 break;
 340         default:
 341                 /* FIXME: other BPPs.
 342                  * bpp1: code  0,     size 256
 343                  * bpp2: code  0x1000 size 256
 344                  * bpp4: code  0x2000 size 256
 345                  * bpp12: code 0x4000 size 32
 346                  */
 347                 DBGPRINT(1, "invalid color mode %d\n", color_mode);
 348                 return -1;
 349         }
 350
 351         omap_lcdc.palette_org = PAGE_ALIGN(MAX_PALETTE_SIZE) -
 352                                         omap_lcdc.palette_size;
 353
 354         if (omap_lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 355                 disable_controller();
 356                 omap_stop_lcd_dma();
 357                 setup_lcd_dma();
 358                 enable_controller();
 359         }
 360
 361         DBGLEAVE(1);
 362
 363         return 0;
 364 }
 365
 366 static int omap_lcdc_enable_plane(int plane, int enable)
 367 {
 368         if (plane != 0 || enable != 1)
 369                 return -EINVAL;
 370
 371         return 0;
 372 }
 373
 374 /* Configure the LCD DMA for a palette load operation and do the palette
 375  * downloading synchronously. We don't use the frame+palette load mode of
 376  * the controller, since the palette can always be downloaded seperately.
 377  */
 378 static void load_palette(void)
 379 {
 380         u16     *palette;
 381
 382         DBGENTER(1);
 383
 384         palette = (u16 *)((u8 *)omap_lcdc.vram_virt + omap_lcdc.palette_org);
 385
 386         *(u16 *)palette &= 0x0fff;
 387         *(u16 *)palette |= omap_lcdc.palette_code;
 388
 389         omap_set_lcd_dma_b1(omap_lcdc.vram_phys + omap_lcdc.palette_org,
 390                 omap_lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
 391
 392         omap_set_lcd_dma_single_transfer(1);
 393         omap_setup_lcd_dma();
 394
 395         init_completion(&omap_lcdc.palette_load_complete);
 396         enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 397         set_load_mode(OMAP_LCDC_LOAD_PALETTE);
 398         enable_controller();
 399         if (!wait_for_completion_timeout(&omap_lcdc.palette_load_complete,
 400                                 msecs_to_jiffies(500)))
 401                 pr_err("timeout waiting for FRAME DONE\n");
 402         /* The controller gets disabled in the irq handler */
 403         disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 404         omap_stop_lcd_dma();
 405
 406         DBGLEAVE(1);
 407 }
 408
 409 static void calc_ck_div(int is_tft, int pck, int *pck_div)
 410 {
 411         unsigned long lck;
 412
 413         pck = max(1, pck);
 414         lck = clk_get_rate(omap_lcdc.lcd_ck);
 415         *pck_div = lck / pck;
 416         if (is_tft)
 417                 *pck_div = max(2, *pck_div);
 418         else
 419                 *pck_div = max(3, *pck_div);
 420         if (*pck_div > 255) {
 421                 /* FIXME: try to adjust logic clock divider as well */
 422                 *pck_div = 255;
 423                 printk(KERN_WARNING MODULE_NAME ": pixclock %d kHz too low.\n",
 424                                 pck / 1000);
 425         }
 426 }
 427
 428 static void inline setup_regs(void)
 429 {
 430         u32 l;
 431         struct lcd_panel *panel = omap_lcdc.fbdev->panel;
 432         int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
 433         unsigned long lck;
 434         int pcd;
 435
 436         l = omap_readl(OMAP_LCDC_CONTROL);
 437         l &= ~OMAP_LCDC_CTRL_LCD_TFT;
 438         l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
 439 #ifdef CONFIG_MACH_OMAP_PALMTE
 440 /* FIXME:if (machine_is_omap_palmte()) { */
 441                 /* PalmTE uses alternate TFT setting in 8BPP mode */
 442                 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
 443 /*      } */
 444 #endif
 445         omap_writel(l, OMAP_LCDC_CONTROL);
 446
 447         l = omap_readl(OMAP_LCDC_TIMING2);
 448         l &= ~(((1 << 6) - 1) << 20);
 449         l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
 450         omap_writel(l, OMAP_LCDC_TIMING2);
 451
 452         l = panel->x_res - 1;
 453         l |= (panel->hsw - 1) << 10;
 454         l |= (panel->hfp - 1) << 16;
 455         l |= (panel->hbp - 1) << 24;
 456         omap_writel(l, OMAP_LCDC_TIMING0);
 457
 458         l = panel->y_res - 1;
 459         l |= (panel->vsw - 1) << 10;
 460         l |= panel->vfp << 16;
 461         l |= panel->vbp << 24;
 462         omap_writel(l, OMAP_LCDC_TIMING1);
 463
 464         l = omap_readl(OMAP_LCDC_TIMING2);
 465         l &= ~0xff;
 466
 467         lck = clk_get_rate(omap_lcdc.lcd_ck);
 468
 469         if (!panel->pcd)
 470                 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
 471         else {
 472                 printk(KERN_WARNING
 473                     MODULE_NAME ": Pixel clock divider value is obsolete.\n"
 474                     MODULE_NAME ": Try to set pixel_clock to %lu and pcd to 0 "
 475                     "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
 476                         lck / panel->pcd / 1000, panel->name);
 477
 478                 pcd = panel->pcd;
 479         }
 480         l |= pcd & 0xff;
 481         l |= panel->acb << 8;
 482         omap_writel(l, OMAP_LCDC_TIMING2);
 483
 484         /* update panel info with the exact clock */
 485         panel->pixel_clock = lck / pcd / 1000;
 486 }
 487
 488 /* Configure the LCD controller, download the color palette and start a looped
 489  * DMA transfer of the frame image data. */
 490 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
 491 {
 492         int r = 0;
 493
 494         DBGENTER(1);
 495
 496         if (mode != omap_lcdc.update_mode) {
 497                 switch (mode) {
 498                 case OMAPFB_AUTO_UPDATE:
 499                         setup_regs();
 500                         load_palette();
 501
 502                         /* Setup and start LCD DMA */
 503                         setup_lcd_dma();
 504
 505                         set_load_mode(OMAP_LCDC_LOAD_FRAME);
 506                         enable_irqs(OMAP_LCDC_IRQ_DONE);
 507                         /* This will start the actual DMA transfer */
 508                         enable_controller();
 509                         omap_lcdc.update_mode = mode;
 510                         break;
 511                 case OMAPFB_UPDATE_DISABLED:
 512                         disable_controller();
 513                         omap_stop_lcd_dma();
 514                         omap_lcdc.update_mode = mode;
 515                         break;
 516                 default:
 517                         r = -EINVAL;
 518                 }
 519         }
 520
 521         DBGLEAVE(1);
 522         return r;
 523 }
 524
 525 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
 526 {
 527         return omap_lcdc.update_mode;
 528 }
 529
 530 static void omap_lcdc_suspend(void)
 531 {
 532         if (omap_lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 533                 disable_controller();
 534                 omap_stop_lcd_dma();
 535         }
 536 }
 537
 538 static void omap_lcdc_resume(void)
 539 {
 540         if (omap_lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 541                 setup_regs();
 542                 load_palette();
 543                 setup_lcd_dma();
 544                 set_load_mode(OMAP_LCDC_LOAD_FRAME);
 545                 enable_irqs(OMAP_LCDC_IRQ_DONE);
 546                 enable_controller();
 547         }
 548 }
 549
 550 static void omap_lcdc_get_vram_layout(unsigned long *size, void **virt,
 551                                         dma_addr_t *phys)
 552 {
 553         *size = omap_lcdc.vram_size - PAGE_ALIGN(MAX_PALETTE_SIZE);
 554         *virt = (u8 *)omap_lcdc.vram_virt + PAGE_ALIGN(MAX_PALETTE_SIZE);
 555         *phys = omap_lcdc.vram_phys + PAGE_ALIGN(MAX_PALETTE_SIZE);
 556 }
 557
 558 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
 559                           int req_vram_size)
 560 {
 561         int r;
 562         u32 l;
 563         int rate;
 564         struct clk *tc_ck;
 565         struct lcd_panel *panel = fbdev->panel;
 566         int frame_size;
 567
 568         DBGENTER(1);
 569
 570         omap_lcdc.irq_mask = 0;
 571
 572         omap_lcdc.fbdev = fbdev;
 573
 574         pr_info(MODULE_NAME ": init\n");
 575
 576         l = 0;
 577         omap_writel(l, OMAP_LCDC_CONTROL);
 578
 579         /* FIXME:
 580          * According to errata some platforms have a clock rate limitiation
 581          */
 582         omap_lcdc.lcd_ck = clk_get(NULL, "lcd_ck");
 583         if (IS_ERR(omap_lcdc.lcd_ck)) {
 584                 pr_err("unable to access LCD clock\n");
 585                 r = PTR_ERR(omap_lcdc.lcd_ck);
 586                 goto fail0;
 587         }
 588
 589         tc_ck = clk_get(NULL, "tc_ck");
 590         if (IS_ERR(tc_ck)) {
 591                 pr_err("unable to access TC clock\n");
 592                 r = PTR_ERR(tc_ck);
 593                 goto fail1;
 594         }
 595
 596         rate = clk_get_rate(tc_ck);
 597         clk_put(tc_ck);
 598
 599         if (machine_is_omap_h3())
 600                 rate /= 3;
 601         r = clk_set_rate(omap_lcdc.lcd_ck, rate);
 602         if (r) {
 603                 pr_err("failed to adjust LCD rate\n");
 604                 goto fail1;
 605         }
 606         clk_enable(omap_lcdc.lcd_ck);
 607
 608         r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, "omap-lcdc",
 609                         omap_lcdc.fbdev);
 610         if (r) {
 611                 pr_err("unable to get IRQ\n");
 612                 goto fail2;
 613         }
 614
 615         r = omap_request_lcd_dma(NULL, NULL);
 616         if (r) {
 617                 pr_err("unable to get LCD DMA\n");
 618                 goto fail3;
 619         }
 620
 621         frame_size = panel->x_res * panel->bpp * panel->y_res / 8;
 622         if (req_vram_size > frame_size)
 623                 frame_size = req_vram_size;
 624         omap_lcdc.vram_size = PAGE_ALIGN(MAX_PALETTE_SIZE) + frame_size;
 625         omap_lcdc.vram_virt = dma_alloc_writecombine(fbdev->dev,
 626                         omap_lcdc.vram_size, &omap_lcdc.vram_phys, GFP_KERNEL);
 627
 628         if (omap_lcdc.vram_virt == NULL) {
 629                 pr_err("unable to allocate fb DMA memory\n");
 630                 r = -ENOMEM;
 631                 goto fail4;
 632         }
 633
 634         DBGLEAVE(1);
 635         return 0;
 636 fail4:
 637         omap_free_lcd_dma();
 638 fail3:
 639         free_irq(OMAP_LCDC_IRQ, omap_lcdc.fbdev);
 640 fail2:
 641         clk_disable(omap_lcdc.lcd_ck);
 642 fail1:
 643         clk_put(omap_lcdc.lcd_ck);
 644 fail0:
 645         DBGLEAVE(1);
 646         return r;
 647 }
 648
 649 static void omap_lcdc_cleanup(void)
 650 {
 651         dma_free_writecombine(omap_lcdc.fbdev->dev, omap_lcdc.vram_size,
 652                               omap_lcdc.vram_virt, omap_lcdc.vram_phys);
 653         omap_free_lcd_dma();
 654         free_irq(OMAP_LCDC_IRQ, omap_lcdc.fbdev);
 655         clk_disable(omap_lcdc.lcd_ck);
 656         clk_put(omap_lcdc.lcd_ck);
 657 }
 658
 659 static unsigned long omap_lcdc_get_caps(void)
 660 {
 661         return 0;
 662 }
 663
 664 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
 665                                u16 transp, int update_hw_pal)
 666 {
 667         u16 *palette;
 668
 669         if (omap_lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
 670                 return -EINVAL;
 671
 672         palette = (u16 *)((u8*)omap_lcdc.vram_virt +
 673                         PAGE_ALIGN(MAX_PALETTE_SIZE) - omap_lcdc.palette_size);
 674
 675         palette[regno] &= ~0x0fff;
 676         palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
 677                            (blue >> 12);
 678
 679         if (update_hw_pal) {
 680                 disable_controller();
 681                 omap_stop_lcd_dma();
 682                 load_palette();
 683                 setup_lcd_dma();
 684                 set_load_mode(OMAP_LCDC_LOAD_FRAME);
 685                 enable_controller();
 686         }
 687
 688         return 0;
 689 }
 690
 691 struct lcd_ctrl omap1_int_ctrl = {
 692         .name                   = "internal",
 693         .init                   = omap_lcdc_init,
 694         .cleanup                = omap_lcdc_cleanup,
 695         .get_vram_layout        = omap_lcdc_get_vram_layout,
 696         .get_caps               = omap_lcdc_get_caps,
 697         .set_update_mode        = omap_lcdc_set_update_mode,
 698         .get_update_mode        = omap_lcdc_get_update_mode,
 699         .update_window          = NULL,
 700         .suspend                = omap_lcdc_suspend,
 701         .resume                 = omap_lcdc_resume,
 702         .setup_plane            = omap_lcdc_setup_plane,
 703         .enable_plane           = omap_lcdc_enable_plane,
 704         .setcolreg              = omap_lcdc_setcolreg,
 705 };
 706
 707 MODULE_DESCRIPTION("TI OMAP LCDC controller");
 708 MODULE_LICENSE("GPL");