drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * linux/drivers/i2c/i2c-omap.c
   3  *
   4  * TI OMAP I2C master mode driver
   5  *
   6  * Copyright (C) 2003 MontaVista Software, Inc.
   7  * Copyright (C) 2004 Texas Instruments.
   8  *
   9  * Updated to work with multiple I2C interfaces on 24xx by
  10  * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
  11  * Copyright (C) 2005 Nokia Corporation
  12  *
  13  * ----------------------------------------------------------------------------
  14  * This file was highly leveraged from i2c-elektor.c:
  15  *
  16  * Copyright 1995-97 Simon G. Vogl
  17  *           1998-99 Hans Berglund
  18  *
  19  * With some changes from Kysti M�kki <kmalkki@cc.hut.fi> and even
  20  * Frodo Looijaard <frodol@dds.nl>
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License as published by
  24  * the Free Software Foundation; either version 2 of the License, or
  25  * (at your option) any later version.
  26  *
  27  * This program is distributed in the hope that it will be useful,
  28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  30  * GNU General Public License for more details.
  31  *
  32  * You should have received a copy of the GNU General Public License
  33  * along with this program; if not, write to the Free Software
  34  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/delay.h>
  39 #include <linux/i2c.h>
  40 #include <linux/err.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/platform_device.h>
  43
  44 #include <asm/io.h>
  45 #include <asm/hardware/clock.h>
  46
  47 /* ----- global defines ----------------------------------------------- */
  48 static const char driver_name[] = "i2c_omap";
  49
  50 #define MODULE_NAME "OMAP I2C"
  51 #define OMAP_I2C_TIMEOUT (1*HZ) /* timeout waiting for an I2C transaction */
  52
  53 #define pr_err(format, arg...) \
  54                 printk(KERN_ERR MODULE_NAME " ERROR: " format "\n", ## arg )
  55
  56 #define DEFAULT_OWN             1       /* default own I2C address */
  57 #define MAX_MESSAGES            65536   /* max number of messages */
  58
  59 #define OMAP_I2C_REV            0x00
  60 #define OMAP_I2C_IE             0x04
  61 #define OMAP_I2C_STAT           0x08
  62 #define OMAP_I2C_IV             0x0c
  63 #define OMAP_I2C_SYSS           0x10
  64 #define OMAP_I2C_BUF            0x14
  65 #define OMAP_I2C_CNT            0x18
  66 #define OMAP_I2C_DATA           0x1c
  67 #define OMAP_I2C_SYSC           0x20
  68 #define OMAP_I2C_CON            0x24
  69 #define OMAP_I2C_OA             0x28
  70 #define OMAP_I2C_SA             0x2c
  71 #define OMAP_I2C_PSC            0x30
  72 #define OMAP_I2C_SCLL           0x34
  73 #define OMAP_I2C_SCLH           0x38
  74 #define OMAP_I2C_SYSTEST        0x3c
  75
  76 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  77 #define OMAP_I2C_IE_XRDY_IE     (1 << 4)        /* TX data ready int enable */
  78 #define OMAP_I2C_IE_RRDY_IE     (1 << 3)        /* RX data ready int enable */
  79 #define OMAP_I2C_IE_ARDY_IE     (1 << 2)        /* Access ready int enable */
  80 #define OMAP_I2C_IE_NACK_IE     (1 << 1)        /* No ack interrupt enable */
  81 #define OMAP_I2C_IE_AL_IE       (1 << 0)        /* Arbitration lost int ena */
  82
  83 /* I2C Status Register (OMAP_I2C_STAT): */
  84 #define OMAP_I2C_STAT_SBD       (1 << 15)       /* Single byte data */
  85 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  86 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  87 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  88 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  89 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  90 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  91 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  92 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  93 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  94 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  95
  96 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  97 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  98 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  99
 100 /* I2C Configuration Register (OMAP_I2C_CON): */
 101 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 102 #define OMAP_I2C_CON_RST        (0 << 15)       /* I2C module reset */
 103 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 104 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 105 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 106 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 107 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 108 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 109 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 110 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 111
 112 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 113 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 114 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 115 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 116 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 117 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 118 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 119 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 120 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 121
 122 /* I2C System Status register (OMAP_I2C_SYSS): */
 123 #define OMAP_I2C_SYSS_RDONE             1               /* Reset Done */
 124
 125 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 126 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 127
 128 /* ------- debugging ---------------------------------------------------*/
 129
 130 #define I2C_OMAP_DEBUG
 131 #ifdef I2c_OMAP_DEBUG
 132 static int i2c_debug;
 133
 134 module_param(i2c_debug, int, 0);
 135 MODULE_PARM_DESC(i2c_debug,
 136                 "debug level - 0 off; 1 normal; 2,3 more verbose; "
 137                 "9 omap-protocol");
 138
 139 #define DEB(level, format, arg...) do { \
 140         if (i2c_debug >= level) \
 141                 printk(KERN_DEBUG MODULE_NAME " DEBUG: " format "\n", ## arg); \
 142         } while(0)
 143
 144 #define DEB0(format, arg...) DEB(0, format, arg)
 145 #define DEB1(format, arg...) DEB(1, format, arg)
 146 #define DEB2(format, arg...) DEB(2, format, arg)
 147 #define DEB3(format, arg...) DEB(3, format, arg)
 148 #define DEB9(format, arg...) DEB(9, format, arg)
 149
 150 #else
 151
 152 #define DEB0(fmt, args...)
 153 #define DEB1(fmt, args...)
 154 #define DEB2(fmt, args...)
 155 #define DEB3(fmt, args...)
 156 #define DEB9(fmt, args...)
 157
 158 #endif
 159
 160 static int clock = 100; /* Default: Fast Mode = 400 KHz, Standard = 100 KHz */
 161 module_param(clock, int, 0);
 162 MODULE_PARM_DESC(clock, "Set I2C clock in KHz: 100 or 400 (Fast Mode)");
 163
 164 static int own;
 165 module_param(own, int, 0);
 166 MODULE_PARM_DESC(own, "Address of OMAP i2c master (0 for default == 1)");
 167
 168 struct omap_i2c_dev {
 169         struct device           *dev;
 170         void __iomem            *base;          /* virtual */
 171         int                     irq;
 172         struct clk              *iclk;          /* Interface clock */
 173         struct clk              *fclk;          /* Functional clock */
 174         int                     cmd_complete, cmd_err;
 175         wait_queue_head_t       cmd_wait;
 176         u8                      *buf;
 177         size_t                  buf_len;
 178         struct i2c_adapter      adapter;
 179         int                     rev1;
 180 };
 181
 182 static void inline omap_i2c_write(struct omap_i2c_dev *i2c_dev,
 183                                   int val, int reg)
 184 {
 185         __raw_writew(val, i2c_dev->base + reg);
 186 }
 187
 188 static int inline omap_i2c_read(struct omap_i2c_dev *i2c_dev, int reg)
 189 {
 190         return __raw_readw(i2c_dev->base + reg);
 191 }
 192
 193 static void omap_i2c_reset(struct omap_i2c_dev *omap_i2c_dev)
 194 {
 195         unsigned long timeout;
 196         u16 psc = 0;
 197         unsigned long fclk_rate;
 198
 199         /* Soft reset, hard reset needed only for rev1 */
 200         if (!omap_i2c_dev->rev1)
 201                 omap_i2c_write(omap_i2c_dev, OMAP_I2C_SYSC_SRST, OMAP_I2C_SYSC);
 202         else
 203                 omap_i2c_write(omap_i2c_dev, OMAP_I2C_CON_RST, OMAP_I2C_CON);
 204
 205         fclk_rate = 12000000;
 206
 207         if (!cpu_is_omap24xx()) {
 208                 struct clk *armxor_ck;
 209                 unsigned long armxor_rate;
 210
 211                 armxor_ck = clk_get(NULL, "armxor_ck");
 212                 if (IS_ERR(armxor_ck)) {
 213                         printk(KERN_WARNING "i2c: Could not get armxor_ck\n");
 214                         armxor_rate = 12000000;
 215                 } else {
 216                         armxor_rate = clk_get_rate(armxor_ck);
 217                         clk_put(armxor_ck);
 218                 }
 219
 220                 if (armxor_rate > 16000000)
 221                         psc = (armxor_rate + 8000000) / 12000000;
 222
 223                 fclk_rate = armxor_rate;
 224         }
 225
 226         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 227         omap_i2c_write(omap_i2c_dev, psc, OMAP_I2C_PSC);
 228
 229         /* Program desired operating rate */
 230         fclk_rate /= (psc + 1) * 1000;
 231         if (psc > 2)
 232                 psc = 2;
 233         omap_i2c_write(omap_i2c_dev,
 234                         fclk_rate / (clock * 2) - 7 + psc, OMAP_I2C_SCLL);
 235         omap_i2c_write(omap_i2c_dev,
 236                         fclk_rate / (clock * 2) - 7 + psc, OMAP_I2C_SCLH);
 237
 238         /* Set Own Address: */
 239         omap_i2c_write(omap_i2c_dev, own, OMAP_I2C_OA);
 240
 241         /* Enable interrupts */
 242         omap_i2c_write(omap_i2c_dev,
 243                         (OMAP_I2C_IE_XRDY_IE | OMAP_I2C_IE_RRDY_IE |
 244                          OMAP_I2C_IE_ARDY_IE | OMAP_I2C_IE_NACK_IE |
 245                          OMAP_I2C_IE_AL_IE),
 246                         OMAP_I2C_IE);
 247
 248         /* Take the I2C module out of reset: */
 249         omap_i2c_write(omap_i2c_dev, OMAP_I2C_CON_EN, OMAP_I2C_CON);
 250
 251         if (!omap_i2c_dev->rev1){
 252                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 253                 while (!(omap_i2c_read(omap_i2c_dev, OMAP_I2C_SYSS) &
 254                                         OMAP_I2C_SYSS_RDONE)) {
 255                         if (time_after(jiffies, timeout)) {
 256                                 pr_err("timeout waiting for I2C reset");
 257                                 break;
 258                         }
 259                         msleep(1);
 260                 }
 261         }
 262 }
 263
 264 /*
 265  * Waiting on Bus Busy
 266  */
 267 static int
 268 omap_i2c_wait_for_bb(struct omap_i2c_dev *omap_i2c_dev, char allow_sleep)
 269 {
 270         unsigned long timeout;
 271
 272         timeout = jiffies + OMAP_I2C_TIMEOUT;
 273         while (omap_i2c_read(omap_i2c_dev, OMAP_I2C_STAT) & OMAP_I2C_STAT_BB) {
 274                 if (time_after(jiffies, timeout)) {
 275                         printk(KERN_WARNING "timeout waiting for bus ready\n");
 276                         return -ETIMEDOUT;
 277                 }
 278                 if (allow_sleep)
 279                         msleep(1);
 280         }
 281
 282         return 0;
 283 }
 284
 285 /*
 286  * Low level master read/write transaction.
 287  */
 288 static int
 289 omap_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 290 {
 291         struct omap_i2c_dev *omap_i2c_dev = i2c_get_adapdata(adap);
 292         u8 zero_byte = 0;
 293         int r;
 294         u16 w;
 295
 296         DEB2("addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 297              msg->addr, msg->len, msg->flags, stop);
 298
 299         omap_i2c_write(omap_i2c_dev, msg->addr, OMAP_I2C_SA);
 300
 301         /* Sigh, seems we can't do zero length transactions. Thus, we
 302          * can't probe for devices w/o actually sending/receiving at least
 303          * a single byte. So we'll set count to 1 for the zero length
 304          * transaction case and hope we don't cause grief for some
 305          * arbitrary device due to random byte write/read during
 306          * probes.
 307          */
 308         if (msg->len == 0) {
 309                 omap_i2c_dev->buf = &zero_byte;
 310                 omap_i2c_dev->buf_len = 1;
 311         } else {
 312                 omap_i2c_dev->buf = msg->buf;
 313                 omap_i2c_dev->buf_len = msg->len;
 314         }
 315         omap_i2c_write(omap_i2c_dev, omap_i2c_dev->buf_len, OMAP_I2C_CNT);
 316         omap_i2c_dev->cmd_complete = 0;
 317         omap_i2c_dev->cmd_err = 0;
 318         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 319         if (msg->flags & I2C_M_TEN)
 320                 w |= OMAP_I2C_CON_XA;
 321         if (!(msg->flags & I2C_M_RD))
 322                 w |= OMAP_I2C_CON_TRX;
 323         if (stop)
 324                 w |= OMAP_I2C_CON_STP;
 325         omap_i2c_write(omap_i2c_dev, w, OMAP_I2C_CON);
 326
 327         r = wait_event_interruptible_timeout(omap_i2c_dev->cmd_wait,
 328                                              omap_i2c_dev->cmd_complete,
 329                                              OMAP_I2C_TIMEOUT);
 330
 331         omap_i2c_dev->buf_len = 0;
 332         if (r < 0)
 333                 return r;
 334         if (!omap_i2c_dev->cmd_complete) {
 335                 omap_i2c_reset(omap_i2c_dev);
 336                 return -ETIMEDOUT;
 337         }
 338         if (!omap_i2c_dev->cmd_err)
 339                 return msg->len;
 340
 341         /* We have an error */
 342         if (omap_i2c_dev->cmd_err & OMAP_I2C_STAT_NACK) {
 343                 if (msg->flags & I2C_M_IGNORE_NAK)
 344                         return msg->len;
 345                 if (stop)
 346                         omap_i2c_write(omap_i2c_dev,
 347                                 omap_i2c_read(omap_i2c_dev, OMAP_I2C_CON) |
 348                                                 OMAP_I2C_CON_STP,
 349                                 OMAP_I2C_CON);
 350                 return -EREMOTEIO;
 351         }
 352         if ((OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)
 353                         & omap_i2c_dev->cmd_err) {
 354                 omap_i2c_reset(omap_i2c_dev);
 355                 return -EIO;
 356         }
 357         return msg->len;
 358 }
 359
 360 /*
 361  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 362  * to do the work during IRQ processing.
 363  */
 364 static int
 365 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 366 {
 367         struct omap_i2c_dev *omap_i2c_dev = i2c_get_adapdata(adap);
 368         int i;
 369         int r = 0;
 370
 371         DEB1("msgs: %d\n", num);
 372
 373         if (num < 1 || num > MAX_MESSAGES)
 374                 return -EINVAL;
 375
 376         /* Check for valid parameters in messages */
 377         for (i = 0; i < num; i++)
 378                 if (msgs[i].buf == NULL)
 379                         return -EINVAL;
 380
 381 // REVISIT: initialize and use adap->retries
 382
 383         if ((r = omap_i2c_wait_for_bb(omap_i2c_dev, 1)) < 0)
 384                 return r;
 385
 386         for (i = 0; i < num; i++) {
 387                 DEB2("msg: %d, addr: 0x%04x, len: %d, flags: 0x%x\n",
 388                      i, msgs[i].addr, msgs[i].len, msgs[i].flags);
 389
 390                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 391
 392                 DEB2("r: %d\n", r);
 393
 394                 if (r != msgs[i].len)
 395                         break;
 396         }
 397
 398         if (r >= 0 && num > 1)
 399                 r = num;
 400
 401         DEB2("r: %d\n", r);
 402
 403         return r;
 404 }
 405
 406 static u32
 407 omap_i2c_func(struct i2c_adapter *adap)
 408 {
 409         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 410 }
 411
 412 static inline void
 413 omap_i2c_complete_cmd(struct omap_i2c_dev *dev)
 414 {
 415         dev->cmd_complete = 1;
 416         wake_up(&dev->cmd_wait);
 417 }
 418
 419 static irqreturn_t
 420 omap_i2c_isr(int this_irq, void *dev_id, struct pt_regs *regs)
 421 {
 422         struct omap_i2c_dev *omap_i2c_dev = dev_id;
 423         u16 bits;
 424         u16 stat, w;
 425         int count = 0;
 426         u16 iv_read;
 427
 428         bits = omap_i2c_read(omap_i2c_dev, OMAP_I2C_IE);
 429         while ((stat = omap_i2c_read(omap_i2c_dev, OMAP_I2C_STAT)) & bits) {
 430
 431                 if (count++ == 100) {
 432                         printk(KERN_WARNING "Too much work in one IRQ\n");
 433                         break;
 434                 }
 435
 436                 omap_i2c_write(omap_i2c_dev, stat, OMAP_I2C_STAT);
 437                 if (stat & OMAP_I2C_STAT_ARDY) {
 438                         omap_i2c_complete_cmd(omap_i2c_dev);
 439                         omap_i2c_write(omap_i2c_dev, OMAP_I2C_STAT_ARDY,
 440                                        OMAP_I2C_STAT);
 441                         if (omap_i2c_dev->rev1)
 442                                 iv_read = omap_i2c_read(omap_i2c_dev,
 443                                                         OMAP_I2C_IV);
 444                         continue;
 445                 }
 446                 if (stat & OMAP_I2C_STAT_RRDY) {
 447                         w = omap_i2c_read(omap_i2c_dev, OMAP_I2C_DATA);
 448                         if (omap_i2c_dev->buf_len) {
 449                                 *omap_i2c_dev->buf++ = w;
 450                                 omap_i2c_dev->buf_len--;
 451                                 if (omap_i2c_dev->buf_len) {
 452                                         *omap_i2c_dev->buf++ = w >> 8;
 453                                         omap_i2c_dev->buf_len--;
 454                                 }
 455                                 if (omap_i2c_dev->rev1 &&
 456                                     !omap_i2c_dev->buf_len)
 457                                         omap_i2c_complete_cmd(omap_i2c_dev);
 458                         } else
 459                                 pr_err("RRDY IRQ while no data requested");
 460                         omap_i2c_write(omap_i2c_dev, OMAP_I2C_STAT_RRDY,
 461                                         OMAP_I2C_STAT);
 462                         if (omap_i2c_dev->rev1)
 463                                 iv_read = omap_i2c_read(omap_i2c_dev,
 464                                                         OMAP_I2C_IV);
 465                         continue;
 466                 }
 467                 if (stat & OMAP_I2C_STAT_XRDY) {
 468                         w = 0;
 469                         if (omap_i2c_dev->buf_len) {
 470                                 w = *omap_i2c_dev->buf++;
 471                                 omap_i2c_dev->buf_len--;
 472                                 if (omap_i2c_dev->buf_len) {
 473                                         w |= *omap_i2c_dev->buf++ << 8;
 474                                         omap_i2c_dev->buf_len--;
 475                                 }
 476                         } else {
 477                                 pr_err("XRDY IRQ while no data to send");
 478                                 /* FIXME: shouldn't we bail out here? */
 479                         }
 480                         omap_i2c_write(omap_i2c_dev, w, OMAP_I2C_DATA);
 481                         /* We have to make sure the XRDY bit is reset */
 482                         omap_i2c_write(omap_i2c_dev, OMAP_I2C_STAT_XRDY,
 483                                         OMAP_I2C_STAT);
 484                         if (omap_i2c_dev->rev1) {
 485                                 iv_read = omap_i2c_read(omap_i2c_dev,
 486                                                         OMAP_I2C_IV);
 487                                 if (!omap_i2c_dev->buf_len)
 488                                         omap_i2c_complete_cmd(omap_i2c_dev);
 489                         }
 490                         continue;
 491                 }
 492                 if (stat & OMAP_I2C_STAT_ROVR) {
 493                         pr_err("Receive overrun\n");
 494                         omap_i2c_dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 495                 }
 496                 if (stat & OMAP_I2C_STAT_XUDF) {
 497                         pr_err("Transmit overflow\n");
 498                         omap_i2c_dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 499                 }
 500                 if (stat & OMAP_I2C_STAT_NACK) {
 501                         omap_i2c_dev->cmd_err |= OMAP_I2C_STAT_NACK;
 502                         omap_i2c_complete_cmd(omap_i2c_dev);
 503                         omap_i2c_write(omap_i2c_dev, OMAP_I2C_CON_STP,
 504                                        OMAP_I2C_CON);
 505                 }
 506                 if (stat & OMAP_I2C_STAT_AL) {
 507                         pr_err("Arbitration lost\n");
 508                         omap_i2c_dev->cmd_err |= OMAP_I2C_STAT_AL;
 509                         omap_i2c_complete_cmd(omap_i2c_dev);
 510                 }
 511                 if (omap_i2c_dev->rev1)
 512                         iv_read = omap_i2c_read(omap_i2c_dev, OMAP_I2C_IV);
 513
 514         }
 515         return IRQ_HANDLED;
 516 }
 517
 518 static struct i2c_algorithm omap_i2c_algo = {
 519         .master_xfer    = omap_i2c_xfer,
 520         .functionality  = omap_i2c_func,
 521 };
 522
 523 #ifdef CONFIG_ARCH_OMAP24XX
 524 static int omap_i2c_24xx_get_clocks(struct omap_i2c_dev *omap_i2c_dev, int bus)
 525 {
 526         if (!cpu_is_omap24xx())
 527                 return 0;
 528
 529         omap_i2c_dev->iclk = clk_get(NULL,
 530                 bus == 1 ? "i2c1_ick" : "i2c2_ick");
 531         if (IS_ERR(omap_i2c_dev->iclk)) {
 532                 return -ENODEV;
 533         }
 534
 535         omap_i2c_dev->fclk = clk_get(NULL,
 536                 bus == 1 ? "i2c1_fck" : "i2c2_fck");
 537         if (IS_ERR(omap_i2c_dev->fclk)) {
 538                 clk_put(omap_i2c_dev->fclk);
 539                 return -ENODEV;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static void omap_i2c_24xx_put_clocks(struct omap_i2c_dev *omap_i2c_dev)
 546 {
 547         if (cpu_is_omap24xx()) {
 548                 clk_put(omap_i2c_dev->fclk);
 549                 clk_put(omap_i2c_dev->iclk);
 550         }
 551 }
 552
 553 static void omap_i2c_24xx_enable_clocks(struct omap_i2c_dev *omap_i2c_dev,
 554                                         int enable)
 555 {
 556         if (cpu_is_omap24xx()) {
 557                 if (enable) {
 558                         clk_enable(omap_i2c_dev->iclk);
 559                         clk_enable(omap_i2c_dev->fclk);
 560                 } else {
 561                         clk_disable(omap_i2c_dev->iclk);
 562                         clk_disable(omap_i2c_dev->fclk);
 563                 }
 564         }
 565 }
 566
 567 #else
 568 #define omap_i2c_24xx_get_clocks(x, y)          0
 569 #define omap_i2c_24xx_enable_clocks(x, y)       do {} while (0)
 570 #define omap_i2c_24xx_put_clocks(x)             do {} while (0)
 571 #endif
 572
 573 static int
 574 omap_i2c_probe(struct platform_device *pdev)
 575 {
 576         struct omap_i2c_dev     *omap_i2c_dev;
 577         struct i2c_adapter      *adap;
 578         struct resource         *mem, *irq;
 579         int r;
 580
 581         /* NOTE: driver uses the static register mapping */
 582         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 583         if (!mem) {
 584                 pr_err("%s: no mem resource?\n", driver_name);
 585                 return -ENODEV;
 586         }
 587         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 588         if (!irq) {
 589                 pr_err("%s: no irq resource?\n", driver_name);
 590                 return -ENODEV;
 591         }
 592
 593         r = (int) request_mem_region(mem->start, (mem->end - mem->start) + 1,
 594                         driver_name);
 595         if (!r) {
 596                 pr_err("%s: I2C region already claimed\n", driver_name);
 597                 return -EBUSY;
 598         }
 599
 600         if (clock > 200)
 601                 clock = 400;    /* Fast mode */
 602         else
 603                 clock = 100;    /* Standard mode */
 604
 605         if (own < 1 || own > 0x7f)
 606                 own = DEFAULT_OWN;
 607
 608         omap_i2c_dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 609         if (!omap_i2c_dev) {
 610                 r = -ENOMEM;
 611                 goto do_release_region;
 612         }
 613
 614         omap_i2c_dev->dev = &pdev->dev;
 615         omap_i2c_dev->irq = irq->start;
 616         omap_i2c_dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 617         platform_set_drvdata(pdev, omap_i2c_dev);
 618         init_waitqueue_head(&omap_i2c_dev->cmd_wait);
 619
 620         if ((r = omap_i2c_24xx_get_clocks(omap_i2c_dev, pdev->id)) != 0)
 621                 goto do_free_mem;
 622
 623         omap_i2c_24xx_enable_clocks(omap_i2c_dev, 1);
 624
 625 #ifdef CONFIG_ARCH_OMAP15XX
 626         omap_i2c_dev->rev1 = omap_i2c_read(omap_i2c_dev, OMAP_I2C_REV) < 0x20;
 627 #endif
 628
 629         /* reset ASAP, clearing any IRQs */
 630         omap_i2c_reset(omap_i2c_dev);
 631
 632         r = request_irq(omap_i2c_dev->irq, omap_i2c_isr, 0,
 633                         driver_name, omap_i2c_dev);
 634         if (r) {
 635                 pr_err("%s: failure requesting irq %i\n",
 636                          driver_name, omap_i2c_dev->irq);
 637                 goto do_unuse_clocks;
 638         }
 639         r = omap_i2c_read(omap_i2c_dev, OMAP_I2C_REV) & 0xff;
 640         pr_info("%s: bus %d rev%d.%d at %d KHz\n", driver_name,
 641                         pdev->id - 1, r >> 4, r & 0xf, clock);
 642
 643         adap = &omap_i2c_dev->adapter;
 644         i2c_set_adapdata(adap, omap_i2c_dev);
 645         adap->owner = THIS_MODULE;
 646         adap->class = I2C_CLASS_HWMON;
 647         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 648         adap->algo = &omap_i2c_algo;
 649         adap->dev.parent = &pdev->dev;
 650         /* i2c device drivers may be active on return from add_adapter() */
 651         r = i2c_add_adapter(adap);
 652         if (r) {
 653                 pr_err("%s: failure adding adapter\n", driver_name);
 654                 goto do_free_irq;
 655         }
 656
 657         return 0;
 658
 659 do_free_irq:
 660         free_irq(omap_i2c_dev->irq, omap_i2c_dev);
 661 do_unuse_clocks:
 662         omap_i2c_24xx_enable_clocks(omap_i2c_dev, 0);
 663         omap_i2c_24xx_put_clocks(omap_i2c_dev);
 664 do_free_mem:
 665         kfree(omap_i2c_dev);
 666 do_release_region:
 667         omap_i2c_write(omap_i2c_dev, 0, OMAP_I2C_CON);
 668         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 669
 670         return r;
 671 }
 672
 673 static int
 674 omap_i2c_remove(struct platform_device *pdev)
 675 {
 676         struct omap_i2c_dev     *omap_i2c_dev = platform_get_drvdata(pdev);
 677         struct resource         *mem;
 678
 679         omap_i2c_write(omap_i2c_dev, 0, OMAP_I2C_CON);
 680         i2c_del_adapter(&omap_i2c_dev->adapter);
 681         free_irq(omap_i2c_dev->irq, omap_i2c_dev);
 682         omap_i2c_24xx_enable_clocks(omap_i2c_dev, 0);
 683         omap_i2c_24xx_put_clocks(omap_i2c_dev);
 684         kfree(omap_i2c_dev);
 685         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 686         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 687         return 0;
 688 }
 689
 690 static struct platform_driver omap_i2c_driver = {
 691         .probe          = omap_i2c_probe,
 692         .remove         = omap_i2c_remove,
 693         .driver         = {
 694                 .name   = (char *)driver_name,
 695         },
 696 };
 697
 698 /* i2c may be needed to bring up other drivers */
 699 static int __init
 700 omap_i2c_init_driver(void)
 701 {
 702         return platform_driver_register(&omap_i2c_driver);
 703 }
 704 subsys_initcall(omap_i2c_init_driver);
 705
 706 static void __exit omap_i2c_exit_driver(void)
 707 {
 708         platform_driver_unregister(&omap_i2c_driver);
 709 }
 710 module_exit(omap_i2c_exit_driver);
 711
 712 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 713 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 714 MODULE_LICENSE("GPL");