arch/blackfin/mach-common/clocks-init.c

   1 /*
   2  * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/linkage.h>
  10 #include <linux/init.h>
  11 #include <asm/blackfin.h>
  12
  13 #include <asm/dma.h>
  14 #include <asm/clocks.h>
  15 #include <asm/mem_init.h>
  16
  17 #define PLL_CTL_VAL \
  18         (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
  19          (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0))
  20
  21 __attribute__((l1_text))
  22 static void do_sync(void)
  23 {
  24         __builtin_bfin_ssync();
  25 }
  26
  27 __attribute__((l1_text))
  28 void init_clocks(void)
  29 {
  30         /* Kill any active DMAs as they may trigger external memory accesses
  31          * in the middle of reprogramming things, and that'll screw us up.
  32          * For example, any automatic DMAs left by U-Boot for splash screens.
  33          */
  34         size_t i;
  35         for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
  36                 struct dma_register *dma = dma_io_base_addr[i];
  37                 dma->cfg = 0;
  38         }
  39
  40         do_sync();
  41
  42 #ifdef SIC_IWR0
  43         bfin_write_SIC_IWR0(IWR_ENABLE(0));
  44 # ifdef SIC_IWR1
  45         /* BF52x system reset does not properly reset SIC_IWR1 which
  46          * will screw up the bootrom as it relies on MDMA0/1 waking it
  47          * up from IDLE instructions.  See this report for more info:
  48          * http://blackfin.uclinux.org/gf/tracker/4323
  49          */
  50         if (ANOMALY_05000435)
  51                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
  52         else
  53                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
  54 # endif
  55 # ifdef SIC_IWR2
  56         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
  57 # endif
  58 #else
  59         bfin_write_SIC_IWR(IWR_ENABLE(0));
  60 #endif
  61         do_sync();
  62 #ifdef EBIU_SDGCTL
  63         bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
  64         do_sync();
  65 #endif
  66
  67 #ifdef CLKBUFOE
  68         bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
  69         do_sync();
  70         __asm__ __volatile__("IDLE;");
  71 #endif
  72         bfin_write_PLL_LOCKCNT(0x300);
  73         do_sync();
  74         bfin_write16(PLL_CTL, PLL_CTL_VAL);
  75         __asm__ __volatile__("IDLE;");
  76         bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
  77 #ifdef EBIU_SDGCTL
  78         bfin_write_EBIU_SDRRC(mem_SDRRC);
  79         bfin_write_EBIU_SDGCTL(mem_SDGCTL);
  80 #else
  81         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
  82         do_sync();
  83         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
  84         bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
  85         bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
  86         bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
  87 #ifdef CONFIG_MEM_EBIU_DDRQUE
  88         bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
  89 #endif
  90 #endif
  91         do_sync();
  92         bfin_read16(0);
  93 }