arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/wait.h>
  19 #include <linux/completion.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28 #include <asm/arch/dma.h>
  29 #include <asm/arch/mux.h>
  30 #include <asm/arch/irqs.h>
  31 #include <asm/arch/mcbsp.h>
  32 #include <asm/arch/dsp_common.h>
  33
  34 #ifdef CONFIG_MCBSP_DEBUG
  35 #define DBG(x...)       printk(x)
  36 #else
  37 #define DBG(x...)                       do { } while (0)
  38 #endif
  39
  40 struct omap_mcbsp {
  41         u32                          io_base;
  42         u8                           id;
  43         u8                           free;
  44         omap_mcbsp_word_length       rx_word_length;
  45         omap_mcbsp_word_length       tx_word_length;
  46
  47         omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
  48         /* IRQ based TX/RX */
  49         int                          rx_irq;
  50         int                          tx_irq;
  51
  52         /* DMA stuff */
  53         u8                           dma_rx_sync;
  54         short                        dma_rx_lch;
  55         u8                           dma_tx_sync;
  56         short                        dma_tx_lch;
  57
  58         /* Completion queues */
  59         struct completion            tx_irq_completion;
  60         struct completion            rx_irq_completion;
  61         struct completion            tx_dma_completion;
  62         struct completion            rx_dma_completion;
  63
  64         spinlock_t                   lock;
  65 };
  66
  67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
  68 #ifdef CONFIG_ARCH_OMAP1
  69 static struct clk *mcbsp_dsp_ck = 0;
  70 static struct clk *mcbsp_api_ck = 0;
  71 static struct clk *mcbsp_dspxor_ck = 0;
  72 #endif
  73 #ifdef CONFIG_ARCH_OMAP2
  74 static struct clk *mcbsp1_ick = 0;
  75 static struct clk *mcbsp1_fck = 0;
  76 static struct clk *mcbsp2_ick = 0;
  77 static struct clk *mcbsp2_fck = 0;
  78 #endif
  79
  80 static void omap_mcbsp_dump_reg(u8 id)
  81 {
  82         DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
  83         DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
  84         DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
  85         DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
  86         DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
  87         DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
  88         DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
  89         DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
  90         DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
  91         DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
  92         DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
  93         DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
  94         DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
  95         DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
  96         DBG("***********************\n");
  97 }
  98
  99 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 100 {
 101         struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
 102
 103         DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
 104
 105         complete(&mcbsp_tx->tx_irq_completion);
 106         return IRQ_HANDLED;
 107 }
 108
 109 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 110 {
 111         struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
 112
 113         DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 114
 115         complete(&mcbsp_rx->rx_irq_completion);
 116         return IRQ_HANDLED;
 117 }
 118
 119 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 120 {
 121         struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
 122
 123         DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 124
 125         /* We can free the channels */
 126         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 127         mcbsp_dma_tx->dma_tx_lch = -1;
 128
 129         complete(&mcbsp_dma_tx->tx_dma_completion);
 130 }
 131
 132 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 133 {
 134         struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
 135
 136         DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 137
 138         /* We can free the channels */
 139         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 140         mcbsp_dma_rx->dma_rx_lch = -1;
 141
 142         complete(&mcbsp_dma_rx->rx_dma_completion);
 143 }
 144
 145
 146 /*
 147  * omap_mcbsp_config simply write a config to the
 148  * appropriate McBSP.
 149  * You either call this function or set the McBSP registers
 150  * by yourself before calling omap_mcbsp_start().
 151  */
 152
 153 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
 154 {
 155         u32 io_base = mcbsp[id].io_base;
 156
 157         DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
 158
 159         /* We write the given config */
 160         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 161         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 162         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 163         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 164         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 165         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 166         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 167         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 168         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 169         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 170         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 171 }
 172
 173
 174
 175 static int omap_mcbsp_check(unsigned int id)
 176 {
 177         if (cpu_is_omap730()) {
 178                 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
 179                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 180                        return -1;
 181                 }
 182                 return 0;
 183         }
 184
 185         if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
 186                 if (id > OMAP_MAX_MCBSP_COUNT) {
 187                         printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 188                         return -1;
 189                 }
 190                 return 0;
 191         }
 192
 193         return -1;
 194 }
 195
 196 #ifdef CONFIG_ARCH_OMAP1
 197 static void omap_mcbsp_dsp_request(void)
 198 {
 199         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 200                 omap_dsp_request_mem();
 201                 clk_enable(mcbsp_dsp_ck);
 202                 clk_enable(mcbsp_api_ck);
 203
 204                 /* enable 12MHz clock to mcbsp 1 & 3 */
 205                 clk_enable(mcbsp_dspxor_ck);
 206
 207                 /*
 208                  * DSP external peripheral reset
 209                  * FIXME: This should be moved to dsp code
 210                  */
 211                 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
 212                              DSP_RSTCT2);
 213         }
 214 }
 215
 216 static void omap_mcbsp_dsp_free(void)
 217 {
 218         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 219                 omap_dsp_release_mem();
 220                 clk_disable(mcbsp_dspxor_ck);
 221                 clk_disable(mcbsp_dsp_ck);
 222                 clk_disable(mcbsp_api_ck);
 223         }
 224 }
 225 #endif
 226
 227 #ifdef CONFIG_ARCH_OMAP2
 228 static void omap2_mcbsp2_mux_setup(void)
 229 {
 230         if (cpu_is_omap2420()) {
 231                 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
 232                 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
 233                 omap_cfg_reg(W15_24XX_MCBSP2_DR);
 234                 omap_cfg_reg(V15_24XX_MCBSP2_DX);
 235                 omap_cfg_reg(V14_24XX_GPIO117);
 236         }
 237         /*
 238          * Need to add MUX settings for OMAP 2430 SDP
 239          */
 240 }
 241 #endif
 242
 243 /*
 244  * We can choose between IRQ based or polled IO.
 245  * This needs to be called before omap_mcbsp_request().
 246  */
 247 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 248 {
 249         if (omap_mcbsp_check(id) < 0)
 250                 return -EINVAL;
 251
 252         spin_lock(&mcbsp[id].lock);
 253
 254         if (!mcbsp[id].free) {
 255                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 256                 spin_unlock(&mcbsp[id].lock);
 257                 return -EINVAL;
 258         }
 259
 260         mcbsp[id].io_type = io_type;
 261
 262         spin_unlock(&mcbsp[id].lock);
 263
 264         return 0;
 265 }
 266
 267 int omap_mcbsp_request(unsigned int id)
 268 {
 269         int err;
 270
 271         if (omap_mcbsp_check(id) < 0)
 272                 return -EINVAL;
 273
 274 #ifdef CONFIG_ARCH_OMAP1
 275         /*
 276          * On 1510, 1610 and 1710, McBSP1 and McBSP3
 277          * are DSP public peripherals.
 278          */
 279         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 280                 omap_mcbsp_dsp_request();
 281 #endif
 282
 283 #ifdef CONFIG_ARCH_OMAP2
 284         if (cpu_is_omap24xx()) {
 285                 if (id == OMAP_MCBSP1) {
 286                         clk_enable(mcbsp1_ick);
 287                         clk_enable(mcbsp1_fck);
 288                 } else {
 289                         clk_enable(mcbsp2_ick);
 290                         clk_enable(mcbsp2_fck);
 291                 }
 292         }
 293 #endif
 294
 295         spin_lock(&mcbsp[id].lock);
 296         if (!mcbsp[id].free) {
 297                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 298                 spin_unlock(&mcbsp[id].lock);
 299                 return -1;
 300         }
 301
 302         mcbsp[id].free = 0;
 303         spin_unlock(&mcbsp[id].lock);
 304
 305         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 306                 /* We need to get IRQs here */
 307                 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
 308                                   "McBSP",
 309                                   (void *) (&mcbsp[id]));
 310                 if (err != 0) {
 311                         printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
 312                                mcbsp[id].tx_irq, mcbsp[id].id);
 313                         return err;
 314                 }
 315
 316                 init_completion(&(mcbsp[id].tx_irq_completion));
 317
 318
 319                 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
 320                                   "McBSP",
 321                                   (void *) (&mcbsp[id]));
 322                 if (err != 0) {
 323                         printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
 324                                mcbsp[id].rx_irq, mcbsp[id].id);
 325                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 326                         return err;
 327                 }
 328
 329                 init_completion(&(mcbsp[id].rx_irq_completion));
 330         }
 331
 332         return 0;
 333
 334 }
 335
 336 void omap_mcbsp_free(unsigned int id)
 337 {
 338         if (omap_mcbsp_check(id) < 0)
 339                 return;
 340
 341 #ifdef CONFIG_ARCH_OMAP1
 342         if (cpu_class_is_omap1()) {
 343                 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 344                         omap_mcbsp_dsp_free();
 345         }
 346 #endif
 347
 348 #ifdef CONFIG_ARCH_OMAP2
 349         if (cpu_is_omap24xx()) {
 350                 if (id == OMAP_MCBSP1) {
 351                         clk_disable(mcbsp1_ick);
 352                         clk_disable(mcbsp1_fck);
 353                 } else {
 354                         clk_disable(mcbsp2_ick);
 355                         clk_disable(mcbsp2_fck);
 356                 }
 357         }
 358 #endif
 359
 360         spin_lock(&mcbsp[id].lock);
 361         if (mcbsp[id].free) {
 362                 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
 363                 spin_unlock(&mcbsp[id].lock);
 364                 return;
 365         }
 366
 367         mcbsp[id].free = 1;
 368         spin_unlock(&mcbsp[id].lock);
 369
 370         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 371                 /* Free IRQs */
 372                 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
 373                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 374         }
 375 }
 376
 377 /*
 378  * Here we start the McBSP, by enabling the sample
 379  * generator, both transmitter and receivers,
 380  * and the frame sync.
 381  */
 382 void omap_mcbsp_start(unsigned int id)
 383 {
 384         u32 io_base;
 385         u16 w;
 386
 387         if (omap_mcbsp_check(id) < 0)
 388                 return;
 389
 390         io_base = mcbsp[id].io_base;
 391
 392         mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
 393         mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
 394
 395         /* Start the sample generator */
 396         w = OMAP_MCBSP_READ(io_base, SPCR2);
 397         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 398
 399         /* Enable transmitter and receiver */
 400         w = OMAP_MCBSP_READ(io_base, SPCR2);
 401         OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
 402
 403         w = OMAP_MCBSP_READ(io_base, SPCR1);
 404         OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
 405
 406         udelay(100);
 407
 408         /* Start frame sync */
 409         w = OMAP_MCBSP_READ(io_base, SPCR2);
 410         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 411
 412         /* Dump McBSP Regs */
 413         omap_mcbsp_dump_reg(id);
 414
 415 }
 416
 417 void omap_mcbsp_stop(unsigned int id)
 418 {
 419         u32 io_base;
 420         u16 w;
 421
 422         if (omap_mcbsp_check(id) < 0)
 423                 return;
 424
 425         io_base = mcbsp[id].io_base;
 426
 427         /* Reset transmitter */
 428         w = OMAP_MCBSP_READ(io_base, SPCR2);
 429         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 430
 431         /* Reset receiver */
 432         w = OMAP_MCBSP_READ(io_base, SPCR1);
 433         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
 434
 435         /* Reset the sample rate generator */
 436         w = OMAP_MCBSP_READ(io_base, SPCR2);
 437         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 438 }
 439
 440
 441 /* polled mcbsp i/o operations */
 442 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 443 {
 444         u32 base = mcbsp[id].io_base;
 445         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 446         /* if frame sync error - clear the error */
 447         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 448                 /* clear error */
 449                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 450                        base + OMAP_MCBSP_REG_SPCR2);
 451                 /* resend */
 452                 return -1;
 453         } else {
 454                 /* wait for transmit confirmation */
 455                 int attemps = 0;
 456                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 457                         if (attemps++ > 1000) {
 458                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 459                                        (~XRST),
 460                                        base + OMAP_MCBSP_REG_SPCR2);
 461                                 udelay(10);
 462                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 463                                        (XRST),
 464                                        base + OMAP_MCBSP_REG_SPCR2);
 465                                 udelay(10);
 466                                 printk(KERN_ERR
 467                                        " Could not write to McBSP Register\n");
 468                                 return -2;
 469                         }
 470                 }
 471         }
 472         return 0;
 473 }
 474
 475 int omap_mcbsp_pollread(unsigned int id, u16 * buf)
 476 {
 477         u32 base = mcbsp[id].io_base;
 478         /* if frame sync error - clear the error */
 479         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 480                 /* clear error */
 481                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 482                        base + OMAP_MCBSP_REG_SPCR1);
 483                 /* resend */
 484                 return -1;
 485         } else {
 486                 /* wait for recieve confirmation */
 487                 int attemps = 0;
 488                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 489                         if (attemps++ > 1000) {
 490                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 491                                        (~RRST),
 492                                        base + OMAP_MCBSP_REG_SPCR1);
 493                                 udelay(10);
 494                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 495                                        (RRST),
 496                                        base + OMAP_MCBSP_REG_SPCR1);
 497                                 udelay(10);
 498                                 printk(KERN_ERR
 499                                        " Could not read from McBSP Register\n");
 500                                 return -2;
 501                         }
 502                 }
 503         }
 504         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 505         return 0;
 506 }
 507
 508 /*
 509  * IRQ based word transmission.
 510  */
 511 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 512 {
 513         u32 io_base;
 514         omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
 515
 516         if (omap_mcbsp_check(id) < 0)
 517                 return;
 518
 519         io_base = mcbsp[id].io_base;
 520
 521         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 522
 523         if (word_length > OMAP_MCBSP_WORD_16)
 524                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 525         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 526 }
 527
 528 u32 omap_mcbsp_recv_word(unsigned int id)
 529 {
 530         u32 io_base;
 531         u16 word_lsb, word_msb = 0;
 532         omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
 533
 534         if (omap_mcbsp_check(id) < 0)
 535                 return -EINVAL;
 536
 537         io_base = mcbsp[id].io_base;
 538
 539         wait_for_completion(&(mcbsp[id].rx_irq_completion));
 540
 541         if (word_length > OMAP_MCBSP_WORD_16)
 542                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 543         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 544
 545         return (word_lsb | (word_msb << 16));
 546 }
 547
 548
 549 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 550 {
 551         u32 io_base = mcbsp[id].io_base;
 552         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 553         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 554         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 555
 556         if (tx_word_length != rx_word_length)
 557                 return -EINVAL;
 558
 559         /* First we wait for the transmitter to be ready */
 560         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 561         while (!(spcr2 & XRDY)) {
 562                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 563                 if (attempts++ > 1000) {
 564                         /* We must reset the transmitter */
 565                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 566                         udelay(10);
 567                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 568                         udelay(10);
 569                         printk("McBSP transmitter not ready\n");
 570                         return -EAGAIN;
 571                 }
 572         }
 573
 574         /* Now we can push the data */
 575         if (tx_word_length > OMAP_MCBSP_WORD_16)
 576                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 577         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 578
 579         /* We wait for the receiver to be ready */
 580         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 581         while (!(spcr1 & RRDY)) {
 582                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 583                 if (attempts++ > 1000) {
 584                         /* We must reset the receiver */
 585                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 586                         udelay(10);
 587                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 588                         udelay(10);
 589                         printk("McBSP receiver not ready\n");
 590                         return -EAGAIN;
 591                 }
 592         }
 593
 594         /* Receiver is ready, let's read the dummy data */
 595         if (rx_word_length > OMAP_MCBSP_WORD_16)
 596                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 597         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 598
 599         return 0;
 600 }
 601
 602 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
 603 {
 604         u32 io_base = mcbsp[id].io_base, clock_word = 0;
 605         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 606         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 607         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 608
 609         if (tx_word_length != rx_word_length)
 610                 return -EINVAL;
 611
 612         /* First we wait for the transmitter to be ready */
 613         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 614         while (!(spcr2 & XRDY)) {
 615                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 616                 if (attempts++ > 1000) {
 617                         /* We must reset the transmitter */
 618                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 619                         udelay(10);
 620                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 621                         udelay(10);
 622                         printk("McBSP transmitter not ready\n");
 623                         return -EAGAIN;
 624                 }
 625         }
 626
 627         /* We first need to enable the bus clock */
 628         if (tx_word_length > OMAP_MCBSP_WORD_16)
 629                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 630         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 631
 632         /* We wait for the receiver to be ready */
 633         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 634         while (!(spcr1 & RRDY)) {
 635                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 636                 if (attempts++ > 1000) {
 637                         /* We must reset the receiver */
 638                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 639                         udelay(10);
 640                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 641                         udelay(10);
 642                         printk("McBSP receiver not ready\n");
 643                         return -EAGAIN;
 644                 }
 645         }
 646
 647         /* Receiver is ready, there is something for us */
 648         if (rx_word_length > OMAP_MCBSP_WORD_16)
 649                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 650         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 651
 652         word[0] = (word_lsb | (word_msb << 16));
 653
 654         return 0;
 655 }
 656
 657
 658 /*
 659  * Simple DMA based buffer rx/tx routines.
 660  * Nothing fancy, just a single buffer tx/rx through DMA.
 661  * The DMA resources are released once the transfer is done.
 662  * For anything fancier, you should use your own customized DMA
 663  * routines and callbacks.
 664  */
 665 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 666 {
 667         int dma_tx_ch;
 668         int src_port = 0;
 669         int dest_port = 0;
 670         int sync_dev = 0;
 671
 672         if (omap_mcbsp_check(id) < 0)
 673                 return -EINVAL;
 674
 675         if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
 676                              &mcbsp[id],
 677                              &dma_tx_ch)) {
 678                 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
 679                 return -EAGAIN;
 680         }
 681         mcbsp[id].dma_tx_lch = dma_tx_ch;
 682
 683         DBG("TX DMA on channel %d\n", dma_tx_ch);
 684
 685         init_completion(&(mcbsp[id].tx_dma_completion));
 686
 687         if (cpu_class_is_omap1()) {
 688                 src_port = OMAP_DMA_PORT_TIPB;
 689                 dest_port = OMAP_DMA_PORT_EMIFF;
 690         }
 691         if (cpu_is_omap24xx())
 692                 sync_dev = mcbsp[id].dma_tx_sync;
 693
 694         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
 695                                      OMAP_DMA_DATA_TYPE_S16,
 696                                      length >> 1, 1,
 697                                      OMAP_DMA_SYNC_ELEMENT,
 698          sync_dev, 0);
 699
 700         omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
 701                                  src_port,
 702                                  OMAP_DMA_AMODE_CONSTANT,
 703                                  mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
 704                                  0, 0);
 705
 706         omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
 707                                 dest_port,
 708                                 OMAP_DMA_AMODE_POST_INC,
 709                                 buffer,
 710                                 0, 0);
 711
 712         omap_start_dma(mcbsp[id].dma_tx_lch);
 713         wait_for_completion(&(mcbsp[id].tx_dma_completion));
 714         return 0;
 715 }
 716
 717
 718 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 719 {
 720         int dma_rx_ch;
 721         int src_port = 0;
 722         int dest_port = 0;
 723         int sync_dev = 0;
 724
 725         if (omap_mcbsp_check(id) < 0)
 726                 return -EINVAL;
 727
 728         if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
 729                              &mcbsp[id],
 730                              &dma_rx_ch)) {
 731                 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
 732                 return -EAGAIN;
 733         }
 734         mcbsp[id].dma_rx_lch = dma_rx_ch;
 735
 736         DBG("RX DMA on channel %d\n", dma_rx_ch);
 737
 738         init_completion(&(mcbsp[id].rx_dma_completion));
 739
 740         if (cpu_class_is_omap1()) {
 741                 src_port = OMAP_DMA_PORT_TIPB;
 742                 dest_port = OMAP_DMA_PORT_EMIFF;
 743         }
 744         if (cpu_is_omap24xx())
 745                 sync_dev = mcbsp[id].dma_rx_sync;
 746
 747         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
 748                                      OMAP_DMA_DATA_TYPE_S16,
 749                                      length >> 1, 1,
 750                                      OMAP_DMA_SYNC_ELEMENT,
 751          sync_dev, 0);
 752
 753         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
 754                                 src_port,
 755                                 OMAP_DMA_AMODE_CONSTANT,
 756                                 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
 757                                 0, 0);
 758
 759         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
 760                                  dest_port,
 761                                  OMAP_DMA_AMODE_POST_INC,
 762                                  buffer,
 763                                  0, 0);
 764
 765         omap_start_dma(mcbsp[id].dma_rx_lch);
 766         wait_for_completion(&(mcbsp[id].rx_dma_completion));
 767         return 0;
 768 }
 769
 770
 771 /*
 772  * SPI wrapper.
 773  * Since SPI setup is much simpler than the generic McBSP one,
 774  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 775  * Once this is done, you can call omap_mcbsp_start().
 776  */
 777 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
 778 {
 779         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 780
 781         if (omap_mcbsp_check(id) < 0)
 782                 return;
 783
 784         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 785
 786         /* SPI has only one frame */
 787         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 788         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 789
 790         /* Clock stop mode */
 791         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 792                 mcbsp_cfg.spcr1 |= (1 << 12);
 793         else
 794                 mcbsp_cfg.spcr1 |= (3 << 11);
 795
 796         /* Set clock parities */
 797         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 798                 mcbsp_cfg.pcr0 |= CLKRP;
 799         else
 800                 mcbsp_cfg.pcr0 &= ~CLKRP;
 801
 802         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 803                 mcbsp_cfg.pcr0 &= ~CLKXP;
 804         else
 805                 mcbsp_cfg.pcr0 |= CLKXP;
 806
 807         /* Set SCLKME to 0 and CLKSM to 1 */
 808         mcbsp_cfg.pcr0 &= ~SCLKME;
 809         mcbsp_cfg.srgr2 |= CLKSM;
 810
 811         /* Set FSXP */
 812         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
 813                 mcbsp_cfg.pcr0 &= ~FSXP;
 814         else
 815                 mcbsp_cfg.pcr0 |= FSXP;
 816
 817         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
 818                 mcbsp_cfg.pcr0 |= CLKXM;
 819                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
 820                 mcbsp_cfg.pcr0 |= FSXM;
 821                 mcbsp_cfg.srgr2 &= ~FSGM;
 822                 mcbsp_cfg.xcr2 |= XDATDLY(1);
 823                 mcbsp_cfg.rcr2 |= RDATDLY(1);
 824         }
 825         else {
 826                 mcbsp_cfg.pcr0 &= ~CLKXM;
 827                 mcbsp_cfg.srgr1 |= CLKGDV(1);
 828                 mcbsp_cfg.pcr0 &= ~FSXM;
 829                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
 830                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
 831         }
 832
 833         mcbsp_cfg.xcr2 &= ~XPHASE;
 834         mcbsp_cfg.rcr2 &= ~RPHASE;
 835
 836         omap_mcbsp_config(id, &mcbsp_cfg);
 837 }
 838
 839
 840 /*
 841  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 842  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 843  */
 844 struct omap_mcbsp_info {
 845         u32 virt_base;
 846         u8 dma_rx_sync, dma_tx_sync;
 847         u16 rx_irq, tx_irq;
 848 };
 849
 850 #ifdef CONFIG_ARCH_OMAP730
 851 static const struct omap_mcbsp_info mcbsp_730[] = {
 852         [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
 853                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 854                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 855                 .rx_irq = INT_730_McBSP1RX,
 856                 .tx_irq = INT_730_McBSP1TX },
 857         [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
 858                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 859                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 860                 .rx_irq = INT_730_McBSP2RX,
 861                 .tx_irq = INT_730_McBSP2TX },
 862 };
 863 #endif
 864
 865 #ifdef CONFIG_ARCH_OMAP15XX
 866 static const struct omap_mcbsp_info mcbsp_1510[] = {
 867         [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
 868                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 869                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 870                 .rx_irq = INT_McBSP1RX,
 871                 .tx_irq = INT_McBSP1TX },
 872         [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
 873                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 874                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 875                 .rx_irq = INT_1510_SPI_RX,
 876                 .tx_irq = INT_1510_SPI_TX },
 877         [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
 878                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 879                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 880                 .rx_irq = INT_McBSP3RX,
 881                 .tx_irq = INT_McBSP3TX },
 882 };
 883 #endif
 884
 885 #if defined(CONFIG_ARCH_OMAP16XX)
 886 static const struct omap_mcbsp_info mcbsp_1610[] = {
 887         [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
 888                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 889                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 890                 .rx_irq = INT_McBSP1RX,
 891                 .tx_irq = INT_McBSP1TX },
 892         [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
 893                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 894                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 895                 .rx_irq = INT_1610_McBSP2_RX,
 896                 .tx_irq = INT_1610_McBSP2_TX },
 897         [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
 898                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 899                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 900                 .rx_irq = INT_McBSP3RX,
 901                 .tx_irq = INT_McBSP3TX },
 902 };
 903 #endif
 904
 905 #if defined(CONFIG_ARCH_OMAP24XX)
 906 static const struct omap_mcbsp_info mcbsp_24xx[] = {
 907         [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
 908                 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
 909                 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
 910                 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
 911                 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
 912                 },
 913         [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
 914                 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
 915                 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
 916                 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
 917                 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
 918                 },
 919 };
 920 #endif
 921
 922 static int __init omap_mcbsp_init(void)
 923 {
 924         int mcbsp_count = 0, i;
 925         static const struct omap_mcbsp_info *mcbsp_info;
 926
 927         printk("Initializing OMAP McBSP system\n");
 928
 929 #ifdef CONFIG_ARCH_OMAP1
 930         mcbsp_dsp_ck = clk_get(0, "dsp_ck");
 931         if (IS_ERR(mcbsp_dsp_ck)) {
 932                 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
 933                 return PTR_ERR(mcbsp_dsp_ck);
 934         }
 935         mcbsp_api_ck = clk_get(0, "api_ck");
 936         if (IS_ERR(mcbsp_api_ck)) {
 937                 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
 938                 return PTR_ERR(mcbsp_api_ck);
 939         }
 940         mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
 941         if (IS_ERR(mcbsp_dspxor_ck)) {
 942                 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
 943                 return PTR_ERR(mcbsp_dspxor_ck);
 944         }
 945 #endif
 946 #ifdef CONFIG_ARCH_OMAP2
 947         mcbsp1_ick = clk_get(0, "mcbsp1_ick");
 948         if (IS_ERR(mcbsp1_ick)) {
 949                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
 950                 return PTR_ERR(mcbsp1_ick);
 951         }
 952         mcbsp1_fck = clk_get(0, "mcbsp1_fck");
 953         if (IS_ERR(mcbsp1_fck)) {
 954                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
 955                 return PTR_ERR(mcbsp1_fck);
 956         }
 957         mcbsp2_ick = clk_get(0, "mcbsp2_ick");
 958         if (IS_ERR(mcbsp2_ick)) {
 959                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
 960                 return PTR_ERR(mcbsp2_ick);
 961         }
 962         mcbsp2_fck = clk_get(0, "mcbsp2_fck");
 963         if (IS_ERR(mcbsp2_fck)) {
 964                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
 965                 return PTR_ERR(mcbsp2_fck);
 966         }
 967 #endif
 968
 969 #ifdef CONFIG_ARCH_OMAP730
 970         if (cpu_is_omap730()) {
 971                 mcbsp_info = mcbsp_730;
 972                 mcbsp_count = ARRAY_SIZE(mcbsp_730);
 973         }
 974 #endif
 975 #ifdef CONFIG_ARCH_OMAP15XX
 976         if (cpu_is_omap15xx()) {
 977                 mcbsp_info = mcbsp_1510;
 978                 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
 979         }
 980 #endif
 981 #if defined(CONFIG_ARCH_OMAP16XX)
 982         if (cpu_is_omap16xx()) {
 983                 mcbsp_info = mcbsp_1610;
 984                 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
 985         }
 986 #endif
 987 #if defined(CONFIG_ARCH_OMAP24XX)
 988         if (cpu_is_omap24xx()) {
 989                 mcbsp_info = mcbsp_24xx;
 990                 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
 991                 omap2_mcbsp2_mux_setup();
 992         }
 993 #endif
 994         for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
 995                 if (i >= mcbsp_count) {
 996                         mcbsp[i].io_base = 0;
 997                         mcbsp[i].free = 0;
 998                         continue;
 999                 }
1000                 mcbsp[i].id = i + 1;
1001                 mcbsp[i].free = 1;
1002                 mcbsp[i].dma_tx_lch = -1;
1003                 mcbsp[i].dma_rx_lch = -1;
1004
1005                 mcbsp[i].io_base = mcbsp_info[i].virt_base;
1006                 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
1007                 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1008                 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1009                 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1010                 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1011                 spin_lock_init(&mcbsp[i].lock);
1012         }
1013
1014         return 0;
1015 }
1016
1017 arch_initcall(omap_mcbsp_init);
1018
1019 EXPORT_SYMBOL(omap_mcbsp_config);
1020 EXPORT_SYMBOL(omap_mcbsp_request);
1021 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1022 EXPORT_SYMBOL(omap_mcbsp_free);
1023 EXPORT_SYMBOL(omap_mcbsp_start);
1024 EXPORT_SYMBOL(omap_mcbsp_stop);
1025 EXPORT_SYMBOL(omap_mcbsp_pollread);
1026 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1027 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1028 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1029 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1030 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1031 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1032 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1033 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);