From 70a5d71a0e94b38138ad45fb27fb0ed253a299f7 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 12 Nov 2007 15:24:02 -0800 Subject: [PATCH] ARM: OMAP: re-organize duplicated 32k-timer code On OMAP2/3, the gp-timer code can be used for a 32kHz timer simply by setting the source to be the 32k clock instead of sys_clk. This patch uses the mach-omap2/timer-gp.c code for 32kHz timer on OMAP2, moving the logic into mach-omap2/timer-gp.c, and not using plat-omap/timer32k.c which, for OMAP2, is redundant with the timer-gp code. Also, if CONFIG_OMAP_32K_TIMER is enabled, the gptimer-based clocksource is not used. Instead the default 32k sync counter is used as the clocksource (see the clocksource in plat-omap/common.c.) This is important for sleep/suspend so there is a valid counter during sleep. Note that the suspend/sleep code needs fixing to check for overflows of this counter. In addition, the OMAP2/3 details are removed from timer32k.c leaving that with only OMAP1 specifics. A follow-up patch will move it from plat-omap common code to mach-omap1. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 4 +-- arch/arm/mach-omap2/timer-gp.c | 14 ++++++++++ arch/arm/plat-omap/Makefile | 2 ++ arch/arm/plat-omap/timer32k.c | 47 +--------------------------------- 4 files changed, 18 insertions(+), 49 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 88adcd432bb..5bf2dd1b2b6 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -4,9 +4,7 @@ # Common support obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \ - serial.o gpmc.o - -obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o + serial.o gpmc.o timer-gp.o # Power Management obj-$(CONFIG_PM) += pm.o sleep.o diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index c377d830a1d..78d05f203ff 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -104,7 +104,11 @@ static void __init omap2_gp_clockevent_init(void) gptimer = omap_dm_timer_request_specific(1); BUG_ON(gptimer == NULL); +#if defined(CONFIG_OMAP_32K_TIMER) + omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); +#else omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); +#endif tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); omap2_gp_timer_irq.dev_id = (void *)gptimer; @@ -122,6 +126,15 @@ static void __init omap2_gp_clockevent_init(void) clockevents_register_device(&clockevent_gpt); } +#ifdef CONFIG_OMAP_32K_TIMER +/* + * When 32k-timer is enabled, don't use GPTimer for clocksource + * instead, just leave default clocksource which uses the 32k + * sync counter. See clocksource setup in see plat-omap/common.c. + */ + +static inline void __init omap2_gp_clocksource_init(void) {} +#else /* * clocksource */ @@ -167,6 +180,7 @@ static void __init omap2_gp_clocksource_init(void) if (clocksource_register(&clocksource_gpt)) printk(err2, clocksource_gpt.name); } +#endif static void __init omap2_gp_timer_init(void) { diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 9d97ae53899..fdae85243a3 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -9,7 +9,9 @@ obj-m := obj-n := obj- := +ifeq ($(CONFIG_ARCH_OMAP1),y) obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o +endif # OCPI interconnect support for 1710, 1610 and 5912 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c index 1eaec1c179e..61fdf417574 100644 --- a/arch/arm/plat-omap/timer32k.c +++ b/arch/arm/plat-omap/timer32k.c @@ -70,10 +70,6 @@ struct sys_timer omap_timer; #if defined(CONFIG_ARCH_OMAP16XX) #define TIMER_32K_SYNCHRONIZED 0xfffbc410 -#elif defined(CONFIG_ARCH_OMAP24XX) -#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10) -#elif defined(CONFIG_ARCH_OMAP34XX) -#define TIMER_32K_SYNCHRONIZED 0x48320010 #else #error OMAP 32KHz timer does not currently work on 15XX! #endif @@ -95,8 +91,6 @@ struct sys_timer omap_timer; #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ (((nr_jiffies) * (clock_rate)) / HZ) -#if defined(CONFIG_ARCH_OMAP1) - static inline void omap_32k_timer_write(int val, int reg) { omap_writew(val, OMAP1_32K_TIMER_BASE + reg); @@ -122,30 +116,6 @@ static inline void omap_32k_timer_stop(void) #define omap_32k_timer_ack_irq() -#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - -static struct omap_dm_timer *gptimer; - -static inline void omap_32k_timer_start(unsigned long load_val) -{ - omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val); - omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); - omap_dm_timer_start(gptimer); -} - -static inline void omap_32k_timer_stop(void) -{ - omap_dm_timer_stop(gptimer); -} - -static inline void omap_32k_timer_ack_irq(void) -{ - u32 status = omap_dm_timer_read_status(gptimer); - omap_dm_timer_write_status(gptimer, status); -} - -#endif - static int omap_32k_timer_set_next_event(unsigned long delta, struct clock_event_device *dev) { @@ -233,22 +203,7 @@ static struct irqaction omap_32k_timer_irq = { static __init void omap_init_32k_timer(void) { - if (cpu_class_is_omap1()) - setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */ - if (cpu_class_is_omap2()) { - gptimer = omap_dm_timer_request_specific(1); - BUG_ON(gptimer == NULL); - - omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); - setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq); - omap_dm_timer_set_int_enable(gptimer, - OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW | - OMAP_TIMER_INT_MATCH); - } -#endif + setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, NSEC_PER_SEC, -- 2.41.0