OMAP2/3 clock: use clk->prcm_mod for all struct clk register addressing

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock34xx.h

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 9727e1df14c247a703e327820cf389aaaf949810..ccdd3f2476fa1cec27147d7cfea5ae9a0fdfe16b 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -58,18 +58,6 @@ static struct clk dpll2_fck;
 #define DPLL_LOW_POWER_BYPASS          0x5
 #define DPLL_LOCKED                    0x7
 
-#define _OMAP34XX_PRM_REGADDR(module, reg)                             \
-       ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
-
-#define OMAP3430_PRM_CLKSRC_CTRL                                       \
-       _OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET)
-
-#define OMAP3430_PRM_CLKSEL                                            \
-       _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET)
-
-#define OMAP3430_PRM_CLKOUT_CTRL                                       \
-       _OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET)
-
 /* PRM CLOCKS */
 
 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
@@ -192,7 +180,7 @@ static struct clk osc_sys_ck = {
        .name           = "osc_sys_ck",
        .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSEL,
+       .clksel_reg     = OMAP3_PRM_CLKSEL_OFFSET,
        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
        .clksel         = osc_sys_clksel,
        /* REVISIT: deal with autoextclkmode? */
@@ -220,7 +208,7 @@ static struct clk sys_ck = {
        .parent         = &osc_sys_ck,
        .prcm_mod       = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = (__force void __iomem *)OMAP3430_PRM_CLKSRC_CTRL,
+       .clksel_reg     = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
        .clksel         = sys_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -253,7 +241,7 @@ static struct clk sys_clkout1 = {
        .name           = "sys_clkout1",
        .parent         = &osc_sys_ck,
        .prcm_mod       = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
-       .enable_reg     = (__force void __iomem *)OMAP3430_PRM_CLKOUT_CTRL,
+       .enable_reg     = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -284,29 +272,23 @@ static const struct clksel_rate div16_dpll_rates[] = {
        { .div = 0 }
 };
 
-#define _OMAP34XX_CM_REGADDR(module, reg)                              \
-       ((__force void __iomem *)(OMAP34XX_CM_REGADDR((module), (reg))))
-
-#define _OMAP34XX_PRM_REGADDR(module, reg)                             \
-       ((__force void __iomem *)(OMAP34XX_PRM_REGADDR((module), (reg))))
-
 /* DPLL1 */
 /* MPU clock source */
 /* Type: DPLL */
 static struct dpll_data dpll1_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+       .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+       .control_reg    = OMAP3430_CM_CLKEN_PLL,
        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+       .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+       .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .bypass_clk     = &dpll1_fck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -354,7 +336,7 @@ static struct clk dpll1_x2m2_ck = {
        .parent         = &dpll1_x2_ck,
        .prcm_mod       = MPU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+       .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll1_x2m2_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -368,20 +350,20 @@ static struct clk dpll1_x2m2_ck = {
 /* Type: DPLL */
 
 static struct dpll_data dpll2_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+       .mult_div1_reg  = OMAP3430_CM_CLKSEL1_PLL,
        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+       .control_reg    = OMAP3430_CM_CLKEN_PLL,
        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
                                (1 << DPLL_LOW_POWER_BYPASS),
        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+       .autoidle_reg   = OMAP3430_CM_AUTOIDLE_PLL,
        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+       .idlest_reg     = OMAP3430_CM_IDLEST_PLL,
        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
        .bypass_clk     = &dpll2_fck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -417,8 +399,7 @@ static struct clk dpll2_m2_ck = {
        .parent         = &dpll2_ck,
        .prcm_mod       = OMAP3430_IVA2_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
-                                         OMAP3430_CM_CLKSEL2_PLL),
+       .clksel_reg     = OMAP3430_CM_CLKSEL2_PLL,
        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div16_dpll2_m2x2_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -433,18 +414,18 @@ static struct clk dpll2_m2_ck = {
  * REVISIT: Also supports fast relock bypass - not included below
  */
 static struct dpll_data dpll3_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .mult_div1_reg  = CM_CLKSEL1,
        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .control_reg    = CM_CLKEN,
        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+       .autoidle_reg   = CM_AUTOIDLE,
        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
+       .idlest_reg     = CM_IDLEST,
        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -522,7 +503,7 @@ static struct clk dpll3_m2_ck = {
        .parent         = &dpll3_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
        .clksel         = div31_dpll3m2_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -563,7 +544,7 @@ static struct clk dpll3_m3_ck = {
        .parent         = &dpll3_ck,
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
        .clksel         = div16_dpll3_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -577,7 +558,7 @@ static struct clk dpll3_m3x2_ck = {
        .name           = "dpll3_m3x2_ck",
        .parent         = &dpll3_m3_ck,
        .prcm_mod       = PLL_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll3_clkdm" },
@@ -597,19 +578,19 @@ static struct clk emu_core_alwon_ck = {
 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 /* Type: DPLL */
 static struct dpll_data dpll4_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+       .mult_div1_reg  = CM_CLKSEL2,
        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .control_reg    = CM_CLKEN,
        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+       .autoidle_reg   = CM_AUTOIDLE,
        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST),
+       .idlest_reg     = CM_IDLEST,
        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -656,7 +637,7 @@ static struct clk dpll4_m2_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+       .clksel_reg     = OMAP3430_CM_CLKSEL3,
        .clksel_mask    = OMAP3430_DIV_96M_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -670,7 +651,7 @@ static struct clk dpll4_m2x2_ck = {
        .name           = "dpll4_m2x2_ck",
        .parent         = &dpll4_m2_ck,
        .prcm_mod       = PLL_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -722,7 +703,7 @@ static struct clk omap_96m_fck = {
        .parent         = &sys_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
        .clksel         = omap_96m_fck_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -737,7 +718,7 @@ static struct clk dpll4_m3_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = OMAP3430_DSS_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -752,7 +733,7 @@ static struct clk dpll4_m3x2_ck = {
        .parent         = &dpll4_m3_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -779,7 +760,7 @@ static struct clk omap_54m_fck = {
        .name           = "omap_54m_fck",
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
        .clksel         = omap_54m_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -808,7 +789,7 @@ static struct clk omap_48m_fck = {
        .name           = "omap_48m_fck",
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
        .clksel         = omap_48m_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -833,7 +814,7 @@ static struct clk dpll4_m4_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = OMAP3430_DSS_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -847,7 +828,7 @@ static struct clk dpll4_m4x2_ck = {
        .name           = "dpll4_m4x2_ck",
        .parent         = &dpll4_m4_ck,
        .prcm_mod       = PLL_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -860,7 +841,7 @@ static struct clk dpll4_m5_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = OMAP3430_CAM_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -874,7 +855,7 @@ static struct clk dpll4_m5x2_ck = {
        .name           = "dpll4_m5x2_ck",
        .parent         = &dpll4_m5_ck,
        .prcm_mod       = PLL_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -887,7 +868,7 @@ static struct clk dpll4_m6_ck = {
        .parent         = &dpll4_ck,
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
        .clksel         = div16_dpll4_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -902,7 +883,7 @@ static struct clk dpll4_m6x2_ck = {
        .parent         = &dpll4_m6_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_reg     = CM_CLKEN,
        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
        .clkdm          = { .name = "dpll4_clkdm" },
@@ -923,19 +904,19 @@ static struct clk emu_per_alwon_ck = {
 /* Type: DPLL */
 /* 3430ES2 only */
 static struct dpll_data dpll5_dd = {
-       .mult_div1_reg  = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+       .mult_div1_reg  = OMAP3430ES2_CM_CLKSEL4,
        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
-       .control_reg    = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+       .control_reg    = OMAP3430ES2_CM_CLKEN2,
        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
-       .autoidle_reg   = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+       .autoidle_reg   = OMAP3430ES2_CM_AUTOIDLE2_PLL,
        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
-       .idlest_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+       .idlest_reg     = CM_IDLEST2,
        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
        .bypass_clk     = &sys_ck,
        .max_multiplier = OMAP3_MAX_DPLL_MULT,
@@ -967,7 +948,7 @@ static struct clk dpll5_m2_ck = {
        .parent         = &dpll5_ck,
        .prcm_mod       = PLL_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+       .clksel_reg     = OMAP3430ES2_CM_CLKSEL5,
        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
        .clksel         = div16_dpll5_clksel,
        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
@@ -1010,9 +991,9 @@ static struct clk clkout2_src_ck = {
        .name           = "clkout2_src_ck",
        .prcm_mod       = OMAP3430_CCR_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+       .enable_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
-       .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+       .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
        .clksel         = clkout2_src_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
@@ -1038,7 +1019,7 @@ static struct clk sys_clkout2 = {
        .name           = "sys_clkout2",
        .prcm_mod       = OMAP3430_CCR_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = (__force void __iomem *)OMAP3430_CM_CLKOUT_CTRL,
+       .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
        .clksel         = sys_clkout2_clksel,
        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
@@ -1076,7 +1057,7 @@ static struct clk dpll1_fck = {
        .parent         = &core_ck,
        .prcm_mod       = MPU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+       .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
        .clksel         = div4_core_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1111,7 +1092,7 @@ static struct clk arm_fck = {
        .parent         = &mpu_ck,
        .prcm_mod       = MPU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+       .clksel_reg     = OMAP3430_CM_IDLEST_PLL,
        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
        .clksel         = arm_fck_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1140,7 +1121,7 @@ static struct clk dpll2_fck = {
        .parent         = &core_ck,
        .prcm_mod       = OMAP3430_IVA2_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+       .clksel_reg     = OMAP3430_CM_CLKSEL1_PLL,
        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
        .clksel         = div4_core_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1154,7 +1135,7 @@ static struct clk iva2_ck = {
        .parent         = &dpll2_m2_ck,
        .prcm_mod       = OMAP3430_IVA2_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
        .clkdm          = { .name = "iva2_clkdm" },
@@ -1173,7 +1154,7 @@ static struct clk l3_ick = {
        .parent         = &core_ck,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
        .clksel         = div2_core_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1192,7 +1173,7 @@ static struct clk l4_ick = {
        .parent         = &l3_ick,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
        .clksel         = div2_l3_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
@@ -1212,7 +1193,7 @@ static struct clk rm_ick = {
        .parent         = &l4_ick,
        .prcm_mod       = WKUP_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
        .clksel         = div2_l4_clksel,
        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
@@ -1235,7 +1216,7 @@ static struct clk gfx_l3_ck = {
        .parent         = &l3_ick,
        .prcm_mod       = GFX_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP_EN_GFX_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "gfx_3430es1_clkdm" },
@@ -1247,7 +1228,7 @@ static struct clk gfx_l3_fck = {
        .parent         = &gfx_l3_ck,
        .prcm_mod       = GFX_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
        .clksel         = gfx_l3_clksel,
        .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
@@ -1268,7 +1249,7 @@ static struct clk gfx_cg1_ck = {
        .name           = "gfx_cg1_ck",
        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
        .prcm_mod       = GFX_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "gfx_3430es1_clkdm" },
@@ -1279,7 +1260,7 @@ static struct clk gfx_cg2_ck = {
        .name           = "gfx_cg2_ck",
        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
        .prcm_mod       = GFX_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "gfx_3430es1_clkdm" },
@@ -1310,9 +1291,9 @@ static struct clk sgx_fck = {
        .name           = "sgx_fck",
        .init           = &omap2_init_clksel_parent,
        .prcm_mod       = OMAP3430ES2_SGX_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
        .clksel         = sgx_clksel,
        .flags          = CLOCK_IN_OMAP3430ES2,
@@ -1324,7 +1305,7 @@ static struct clk sgx_ick = {
        .name           = "sgx_ick",
        .parent         = &l3_ick,
        .prcm_mod       = OMAP3430ES2_SGX_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "sgx_clkdm" },
@@ -1337,7 +1318,7 @@ static struct clk d2d_26m_fck = {
        .name           = "d2d_26m_fck",
        .parent         = &sys_ck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "d2d_clkdm" },
@@ -1355,9 +1336,9 @@ static struct clk gpt10_fck = {
        .parent         = &sys_ck,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -1370,9 +1351,9 @@ static struct clk gpt11_fck = {
        .parent         = &sys_ck,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -1384,7 +1365,7 @@ static struct clk cpefuse_fck = {
        .name           = "cpefuse_fck",
        .parent         = &sys_ck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+       .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "cm_clkdm" },
@@ -1395,7 +1376,7 @@ static struct clk ts_fck = {
        .name           = "ts_fck",
        .parent         = &omap_32k_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+       .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1406,7 +1387,7 @@ static struct clk usbtll_fck = {
        .name           = "usbtll_fck",
        .parent         = &dpll5_m2_ck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+       .enable_reg     = OMAP3430ES2_CM_FCLKEN3,
        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1429,7 +1410,7 @@ static struct clk mmchs3_fck = {
        .id             = 3,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1441,7 +1422,7 @@ static struct clk mmchs2_fck = {
        .id             = 2,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1452,7 +1433,7 @@ static struct clk mspro_fck = {
        .name           = "mspro_fck",
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1464,7 +1445,7 @@ static struct clk mmchs1_fck = {
        .id             = 1,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1476,7 +1457,7 @@ static struct clk i2c3_fck = {
        .id             = 3,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1488,7 +1469,7 @@ static struct clk i2c2_fck = {
        .id             = 2,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1500,7 +1481,7 @@ static struct clk i2c1_fck = {
        .id             = 1,
        .parent         = &core_96m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1532,7 +1513,7 @@ static struct clk mcbsp5_src_fck = {
        .id             = 5,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
        .clksel         = mcbsp_15_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -1545,7 +1526,7 @@ static struct clk mcbsp5_fck = {
        .id             = 5,
        .parent         = &mcbsp5_src_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1557,7 +1538,7 @@ static struct clk mcbsp1_src_fck = {
        .id             = 1,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+       .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
        .clksel         = mcbsp_15_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -1570,7 +1551,7 @@ static struct clk mcbsp1_fck = {
        .id             = 1,
        .parent         = &mcbsp1_src_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1593,7 +1574,7 @@ static struct clk mcspi4_fck = {
        .id             = 4,
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1605,7 +1586,7 @@ static struct clk mcspi3_fck = {
        .id             = 3,
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1617,7 +1598,7 @@ static struct clk mcspi2_fck = {
        .id             = 2,
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1629,7 +1610,7 @@ static struct clk mcspi1_fck = {
        .id             = 1,
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1640,7 +1621,7 @@ static struct clk uart2_fck = {
        .name           = "uart2_fck",
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1651,7 +1632,7 @@ static struct clk uart1_fck = {
        .name           = "uart1_fck",
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1662,7 +1643,7 @@ static struct clk fshostusb_fck = {
        .name           = "fshostusb_fck",
        .parent         = &core_48m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1684,7 +1665,7 @@ static struct clk hdq_fck = {
        .name           = "hdq_fck",
        .parent         = &core_12m_fck,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1712,9 +1693,9 @@ static struct clk ssi_ssr_fck = {
        .name           = "ssi_ssr_fck",
        .init           = &omap2_init_clksel_parent,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_reg     = CM_FCLKEN1,
        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
        .clksel         = ssi_ssr_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
@@ -1752,7 +1733,7 @@ static struct clk hsotgusb_ick = {
        .name           = "hsotgusb_ick",
        .parent         = &core_l3_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l3_clkdm" },
@@ -1763,7 +1744,7 @@ static struct clk sdrc_ick = {
        .name           = "sdrc_ick",
        .parent         = &core_l3_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
        .clkdm          = { .name = "core_l3_clkdm" },
@@ -1794,7 +1775,7 @@ static struct clk pka_ick = {
        .name           = "pka_ick",
        .parent         = &security_l3_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l3_clkdm" },
@@ -1816,7 +1797,7 @@ static struct clk usbtll_ick = {
        .name           = "usbtll_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+       .enable_reg     = CM_ICLKEN3,
        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1828,7 +1809,7 @@ static struct clk mmchs3_ick = {
        .id             = 3,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1840,7 +1821,7 @@ static struct clk icr_ick = {
        .name           = "icr_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1851,7 +1832,7 @@ static struct clk aes2_ick = {
        .name           = "aes2_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1862,7 +1843,7 @@ static struct clk sha12_ick = {
        .name           = "sha12_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1873,7 +1854,7 @@ static struct clk des2_ick = {
        .name           = "des2_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1885,7 +1866,7 @@ static struct clk mmchs2_ick = {
        .id             = 2,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1897,7 +1878,7 @@ static struct clk mmchs1_ick = {
        .id             = 1,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1908,7 +1889,7 @@ static struct clk mspro_ick = {
        .name           = "mspro_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1919,7 +1900,7 @@ static struct clk hdq_ick = {
        .name           = "hdq_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1931,7 +1912,7 @@ static struct clk mcspi4_ick = {
        .id             = 4,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1943,7 +1924,7 @@ static struct clk mcspi3_ick = {
        .id             = 3,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1955,7 +1936,7 @@ static struct clk mcspi2_ick = {
        .id             = 2,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1967,7 +1948,7 @@ static struct clk mcspi1_ick = {
        .id             = 1,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1979,7 +1960,7 @@ static struct clk i2c3_ick = {
        .id             = 3,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -1991,7 +1972,7 @@ static struct clk i2c2_ick = {
        .id             = 2,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2003,7 +1984,7 @@ static struct clk i2c1_ick = {
        .id             = 1,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2014,7 +1995,7 @@ static struct clk uart2_ick = {
        .name           = "uart2_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2025,7 +2006,7 @@ static struct clk uart1_ick = {
        .name           = "uart1_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2036,7 +2017,7 @@ static struct clk gpt11_ick = {
        .name           = "gpt11_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2047,7 +2028,7 @@ static struct clk gpt10_ick = {
        .name           = "gpt10_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2059,7 +2040,7 @@ static struct clk mcbsp5_ick = {
        .id             = 5,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2071,7 +2052,7 @@ static struct clk mcbsp1_ick = {
        .id             = 1,
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2082,7 +2063,7 @@ static struct clk fac_ick = {
        .name           = "fac_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES1,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2093,7 +2074,7 @@ static struct clk mailboxes_ick = {
        .name           = "mailboxes_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2104,7 +2085,7 @@ static struct clk omapctrl_ick = {
        .name           = "omapctrl_ick",
        .parent         = &core_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2126,7 +2107,7 @@ static struct clk ssi_ick = {
        .name           = "ssi_ick",
        .parent         = &ssi_l4_ick,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2146,9 +2127,9 @@ static struct clk usb_l4_ick = {
        .parent         = &l4_ick,
        .prcm_mod       = CORE_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_reg     = CM_ICLKEN1,
        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
        .clksel         = usb_l4_clksel,
        .flags          = CLOCK_IN_OMAP3430ES1,
@@ -2173,7 +2154,7 @@ static struct clk aes1_ick = {
        .name           = "aes1_ick",
        .parent         = &security_l4_ick2,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2184,7 +2165,7 @@ static struct clk rng_ick = {
        .name           = "rng_ick",
        .parent         = &security_l4_ick2,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2195,7 +2176,7 @@ static struct clk sha11_ick = {
        .name           = "sha11_ick",
        .parent         = &security_l4_ick2,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2206,7 +2187,7 @@ static struct clk des1_ick = {
        .name           = "des1_ick",
        .parent         = &security_l4_ick2,
        .prcm_mod       = CORE_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_reg     = CM_ICLKEN2,
        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "core_l4_clkdm" },
@@ -2218,7 +2199,7 @@ static struct clk dss1_alwon_fck = {
        .name           = "dss1_alwon_fck",
        .parent         = &dpll4_m4x2_ck,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" },
@@ -2229,7 +2210,7 @@ static struct clk dss_tv_fck = {
        .name           = "dss_tv_fck",
        .parent         = &omap_54m_fck,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_TV_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
@@ -2240,7 +2221,7 @@ static struct clk dss_96m_fck = {
        .name           = "dss_96m_fck",
        .parent         = &omap_96m_fck,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_TV_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" },
@@ -2251,7 +2232,7 @@ static struct clk dss2_alwon_fck = {
        .name           = "dss2_alwon_fck",
        .parent         = &sys_ck,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" },
@@ -2263,7 +2244,7 @@ static struct clk dss_ick = {
        .name           = "dss_ick",
        .parent         = &l4_ick,
        .prcm_mod       = OMAP3430_DSS_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "dss_clkdm" },
@@ -2276,7 +2257,7 @@ static struct clk cam_mclk = {
        .name           = "cam_mclk",
        .parent         = &dpll4_m5x2_ck,
        .prcm_mod       = OMAP3430_CAM_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "cam_clkdm" },
@@ -2288,7 +2269,7 @@ static struct clk cam_ick = {
        .name           = "cam_ick",
        .parent         = &l4_ick,
        .prcm_mod       = OMAP3430_CAM_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "cam_clkdm" },
@@ -2299,7 +2280,7 @@ static struct clk csi2_96m_fck = {
        .name           = "csi2_96m_fck",
        .parent         = &core_96m_fck,
        .prcm_mod       = OMAP3430_CAM_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "cam_clkdm" },
@@ -2312,7 +2293,7 @@ static struct clk usbhost_120m_fck = {
        .name           = "usbhost_120m_fck",
        .parent         = &dpll5_m2_ck,
        .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "usbhost_clkdm" },
@@ -2323,7 +2304,7 @@ static struct clk usbhost_48m_fck = {
        .name           = "usbhost_48m_fck",
        .parent         = &omap_48m_fck,
        .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "usbhost_clkdm" },
@@ -2335,7 +2316,7 @@ static struct clk usbhost_ick = {
        .name           = "usbhost_ick",
        .parent         = &l4_ick,
        .prcm_mod       = OMAP3430ES2_USBHOST_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "usbhost_clkdm" },
@@ -2372,9 +2353,9 @@ static struct clk usim_fck = {
        .name           = "usim_fck",
        .prcm_mod       = WKUP_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
        .clksel         = usim_clksel,
        .flags          = CLOCK_IN_OMAP3430ES2,
@@ -2387,9 +2368,9 @@ static struct clk gpt1_fck = {
        .name           = "gpt1_fck",
        .prcm_mod       = WKUP_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2409,7 +2390,7 @@ static struct clk gpio1_fck = {
        .name           = "gpio1_fck",
        .parent         = &wkup_32k_fck,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2420,7 +2401,7 @@ static struct clk wdt2_fck = {
        .name           = "wdt2_fck",
        .parent         = &wkup_32k_fck,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2441,7 +2422,7 @@ static struct clk usim_ick = {
        .name           = "usim_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2452,7 +2433,7 @@ static struct clk wdt2_ick = {
        .name           = "wdt2_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2463,7 +2444,7 @@ static struct clk wdt1_ick = {
        .name           = "wdt1_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2474,7 +2455,7 @@ static struct clk gpio1_ick = {
        .name           = "gpio1_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2485,7 +2466,7 @@ static struct clk omap_32ksync_ick = {
        .name           = "omap_32ksync_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2496,7 +2477,7 @@ static struct clk gpt12_ick = {
        .name           = "gpt12_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2507,7 +2488,7 @@ static struct clk gpt1_ick = {
        .name           = "gpt1_ick",
        .parent         = &wkup_l4_ick,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "prm_clkdm" },
@@ -2540,7 +2521,7 @@ static struct clk uart3_fck = {
        .name           = "uart3_fck",
        .parent         = &per_48m_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2551,9 +2532,9 @@ static struct clk gpt2_fck = {
        .name           = "gpt2_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2565,9 +2546,9 @@ static struct clk gpt3_fck = {
        .name           = "gpt3_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2579,9 +2560,9 @@ static struct clk gpt4_fck = {
        .name           = "gpt4_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2593,9 +2574,9 @@ static struct clk gpt5_fck = {
        .name           = "gpt5_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2607,9 +2588,9 @@ static struct clk gpt6_fck = {
        .name           = "gpt6_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2621,9 +2602,9 @@ static struct clk gpt7_fck = {
        .name           = "gpt7_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2635,9 +2616,9 @@ static struct clk gpt8_fck = {
        .name           = "gpt8_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2649,9 +2630,9 @@ static struct clk gpt9_fck = {
        .name           = "gpt9_fck",
        .prcm_mod       = OMAP3430_PER_MOD,
        .init           = &omap2_init_clksel_parent,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+       .clksel_reg     = CM_CLKSEL,
        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
        .clksel         = omap343x_gpt_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2671,7 +2652,7 @@ static struct clk gpio6_fck = {
        .name           = "gpio6_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2682,7 +2663,7 @@ static struct clk gpio5_fck = {
        .name           = "gpio5_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2693,7 +2674,7 @@ static struct clk gpio4_fck = {
        .name           = "gpio4_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2704,7 +2685,7 @@ static struct clk gpio3_fck = {
        .name           = "gpio3_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2715,7 +2696,7 @@ static struct clk gpio2_fck = {
        .name           = "gpio2_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2726,7 +2707,7 @@ static struct clk wdt3_fck = {
        .name           = "wdt3_fck",
        .parent         = &per_32k_alwon_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2746,7 +2727,7 @@ static struct clk gpio6_ick = {
        .name           = "gpio6_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2757,7 +2738,7 @@ static struct clk gpio5_ick = {
        .name           = "gpio5_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2768,7 +2749,7 @@ static struct clk gpio4_ick = {
        .name           = "gpio4_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2779,7 +2760,7 @@ static struct clk gpio3_ick = {
        .name           = "gpio3_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2790,7 +2771,7 @@ static struct clk gpio2_ick = {
        .name           = "gpio2_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2801,7 +2782,7 @@ static struct clk wdt3_ick = {
        .name           = "wdt3_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2812,7 +2793,7 @@ static struct clk uart3_ick = {
        .name           = "uart3_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2823,7 +2804,7 @@ static struct clk gpt9_ick = {
        .name           = "gpt9_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2834,7 +2815,7 @@ static struct clk gpt8_ick = {
        .name           = "gpt8_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2845,7 +2826,7 @@ static struct clk gpt7_ick = {
        .name           = "gpt7_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2856,7 +2837,7 @@ static struct clk gpt6_ick = {
        .name           = "gpt6_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2867,7 +2848,7 @@ static struct clk gpt5_ick = {
        .name           = "gpt5_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2878,7 +2859,7 @@ static struct clk gpt4_ick = {
        .name           = "gpt4_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2889,7 +2870,7 @@ static struct clk gpt3_ick = {
        .name           = "gpt3_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2900,7 +2881,7 @@ static struct clk gpt2_ick = {
        .name           = "gpt2_ick",
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2912,7 +2893,7 @@ static struct clk mcbsp2_ick = {
        .id             = 2,
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2924,7 +2905,7 @@ static struct clk mcbsp3_ick = {
        .id             = 3,
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2936,7 +2917,7 @@ static struct clk mcbsp4_ick = {
        .id             = 4,
        .parent         = &per_l4_ick,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+       .enable_reg     = CM_ICLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2954,7 +2935,7 @@ static struct clk mcbsp2_src_fck = {
        .id             = 2,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+       .clksel_reg     = OMAP2_CONTROL_DEVCONF0,
        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2967,7 +2948,7 @@ static struct clk mcbsp2_fck = {
        .id             = 2,
        .parent         = &mcbsp2_src_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -2979,7 +2960,7 @@ static struct clk mcbsp3_src_fck = {
        .id             = 3,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -2992,7 +2973,7 @@ static struct clk mcbsp3_fck = {
        .id             = 3,
        .parent         = &mcbsp3_src_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -3004,7 +2985,7 @@ static struct clk mcbsp4_src_fck = {
        .id             = 4,
        .prcm_mod       = CLK_REG_IN_SCM,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+       .clksel_reg     = OMAP343X_CONTROL_DEVCONF1,
        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
        .clksel         = mcbsp_234_clksel,
        .flags          = CLOCK_IN_OMAP343X,
@@ -3017,7 +2998,7 @@ static struct clk mcbsp4_fck = {
        .id             = 4,
        .parent         = &mcbsp4_src_fck,
        .prcm_mod       = OMAP3430_PER_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
        .flags          = CLOCK_IN_OMAP343X,
        .clkdm          = { .name = "per_clkdm" },
@@ -3065,7 +3046,7 @@ static struct clk emu_src_ck = {
        .name           = "emu_src_ck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
        .clksel         = emu_src_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3090,7 +3071,7 @@ static struct clk pclk_fck = {
        .name           = "pclk_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
        .clksel         = pclk_emu_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3114,7 +3095,7 @@ static struct clk pclkx2_fck = {
        .name           = "pclkx2_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
        .clksel         = pclkx2_emu_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3131,7 +3112,7 @@ static struct clk atclk_fck = {
        .name           = "atclk_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
        .clksel         = atclk_emu_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3143,7 +3124,7 @@ static struct clk traceclk_src_fck = {
        .name           = "traceclk_src_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
        .clksel         = emu_src_clksel,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
@@ -3167,7 +3148,7 @@ static struct clk traceclk_fck = {
        .name           = "traceclk_fck",
        .prcm_mod       = OMAP3430_EMU_MOD,
        .init           = &omap2_init_clksel_parent,
-       .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+       .clksel_reg     = CM_CLKSEL1,
        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
        .clksel         = traceclk_clksel,
        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
@@ -3182,7 +3163,7 @@ static struct clk sr1_fck = {
        .name           = "sr1_fck",
        .parent         = &sys_ck,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
        .clkdm          = { .name = "prm_clkdm" },
@@ -3194,7 +3175,7 @@ static struct clk sr2_fck = {
        .name           = "sr2_fck",
        .parent         = &sys_ck,
        .prcm_mod       = WKUP_MOD,
-       .enable_reg     = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+       .enable_reg     = CM_FCLKEN,
        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
        .clkdm          = { .name = "prm_clkdm" },