#include "prm.h"
#include "prm-regbits-34xx.h"
-static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
- u8 rate_storage);
-static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
- u8 rate_storage);
+static unsigned long omap3_dpll_recalc(struct clk *clk);
+static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
static void omap3_dpll_allow_idle(struct clk *clk);
static void omap3_dpll_deny_idle(struct clk *clk);
static u32 omap3_dpll_autoidle_read(struct clk *clk);
-static int omap3_noncore_dpll_enable(struct clk *clk);
-static void omap3_noncore_dpll_disable(struct clk *clk);
static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
/* Maximum DPLL multiplier, divider values for OMAP3 */
/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
static struct clk omap_32k_fck = {
.name = "omap_32k_fck",
+ .ops = &clkops_null,
.rate = 32768,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
};
static struct clk secure_32k_fck = {
.name = "secure_32k_fck",
+ .ops = &clkops_null,
.rate = 32768,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
};
/* Virtual source clocks for osc_sys_ck */
static struct clk virt_12m_ck = {
.name = "virt_12m_ck",
+ .ops = &clkops_null,
.rate = 12000000,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
};
static struct clk virt_13m_ck = {
.name = "virt_13m_ck",
+ .ops = &clkops_null,
.rate = 13000000,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
};
static struct clk virt_16_8m_ck = {
.name = "virt_16_8m_ck",
+ .ops = &clkops_null,
.rate = 16800000,
- .flags = CLOCK_IN_OMAP3430ES2 | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
};
static struct clk virt_19_2m_ck = {
.name = "virt_19_2m_ck",
+ .ops = &clkops_null,
.rate = 19200000,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
};
static struct clk virt_26m_ck = {
.name = "virt_26m_ck",
+ .ops = &clkops_null,
.rate = 26000000,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
};
static struct clk virt_38_4m_ck = {
.name = "virt_38_4m_ck",
+ .ops = &clkops_null,
.rate = 38400000,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
};
static const struct clksel_rate osc_sys_12m_rates[] = {
/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
static struct clk osc_sys_ck = {
.name = "osc_sys_ck",
- .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3_PRM_CLKSEL_OFFSET,
+ .clksel_reg = OMAP3430_PRM_CLKSEL,
.clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
.clksel = osc_sys_clksel,
/* REVISIT: deal with autoextclkmode? */
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .flags = RATE_FIXED,
.recalc = &omap2_clksel_recalc,
};
/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
static struct clk sys_ck = {
.name = "sys_ck",
+ .ops = &clkops_null,
.parent = &osc_sys_ck,
- .prcm_mod = OMAP3430_GR_MOD | CLK_REG_IN_PRM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3_PRM_CLKSRC_CTRL_OFFSET,
+ .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
.clksel_mask = OMAP_SYSCLKDIV_MASK,
.clksel = sys_clksel,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
static struct clk sys_altclk = {
.name = "sys_altclk",
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "cm_clkdm" },
+ .ops = &clkops_null,
};
-/*
- * Optional external clock input for some McBSPs
- * Apparently this is not really in prm_clkdm, but rather is fed into
- * both CORE and PER separately.
- */
+/* Optional external clock input for some McBSPs */
static struct clk mcbsp_clks = {
.name = "mcbsp_clks",
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .ops = &clkops_null,
};
/* PRM EXTERNAL CLOCK OUTPUT */
static struct clk sys_clkout1 = {
.name = "sys_clkout1",
+ .ops = &clkops_omap2_dflt,
.parent = &osc_sys_ck,
- .prcm_mod = OMAP3430_CCR_MOD | CLK_REG_IN_PRM,
- .enable_reg = OMAP3_PRM_CLKOUT_CTRL_OFFSET,
+ .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
/* MPU clock source */
/* Type: DPLL */
static struct dpll_data dpll1_dd = {
- .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
+ .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
.mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
.div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
+ .clk_bypass = &dpll1_fck,
+ .clk_ref = &sys_ck,
.freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
- .control_reg = OMAP3430_CM_CLKEN_PLL,
+ .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
.enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
- .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
+ .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
.autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
- .idlest_reg = OMAP3430_CM_IDLEST_PLL,
+ .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
.idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
- .bypass_clk = &dpll1_fck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
static struct clk dpll1_ck = {
.name = "dpll1_ck",
+ .ops = &clkops_null,
.parent = &sys_ck,
- .prcm_mod = MPU_MOD,
.dpll_data = &dpll1_dd,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .clkdm = { .name = "dpll1_clkdm" },
+ .clkdm_name = "dpll1_clkdm",
.recalc = &omap3_dpll_recalc,
};
*/
static struct clk dpll1_x2_ck = {
.name = "dpll1_x2_ck",
+ .ops = &clkops_null,
.parent = &dpll1_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll1_clkdm" },
+ .clkdm_name = "dpll1_clkdm",
.recalc = &omap3_clkoutx2_recalc,
};
*/
static struct clk dpll1_x2m2_ck = {
.name = "dpll1_x2m2_ck",
+ .ops = &clkops_null,
.parent = &dpll1_x2_ck,
- .prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
.clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
.clksel = div16_dpll1_x2m2_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll1_clkdm" },
+ .clkdm_name = "dpll1_clkdm",
.recalc = &omap2_clksel_recalc,
};
/* Type: DPLL */
static struct dpll_data dpll2_dd = {
- .mult_div1_reg = OMAP3430_CM_CLKSEL1_PLL,
+ .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
.mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
.div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
+ .clk_bypass = &dpll2_fck,
+ .clk_ref = &sys_ck,
.freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
- .control_reg = OMAP3430_CM_CLKEN_PLL,
+ .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
.enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
(1 << DPLL_LOW_POWER_BYPASS),
.auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
- .autoidle_reg = OMAP3430_CM_AUTOIDLE_PLL,
+ .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
.autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
- .idlest_reg = OMAP3430_CM_IDLEST_PLL,
+ .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
.idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
- .bypass_clk = &dpll2_fck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
static struct clk dpll2_ck = {
.name = "dpll2_ck",
+ .ops = &clkops_noncore_dpll_ops,
.parent = &sys_ck,
- .prcm_mod = OMAP3430_IVA2_MOD,
.dpll_data = &dpll2_dd,
- .flags = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .clkdm = { .name = "dpll2_clkdm" },
+ .clkdm_name = "dpll2_clkdm",
.recalc = &omap3_dpll_recalc,
};
*/
static struct clk dpll2_m2_ck = {
.name = "dpll2_m2_ck",
+ .ops = &clkops_null,
.parent = &dpll2_ck,
- .prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_CM_CLKSEL2_PLL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+ OMAP3430_CM_CLKSEL2_PLL),
.clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
.clksel = div16_dpll2_m2x2_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll2_clkdm" },
+ .clkdm_name = "dpll2_clkdm",
.recalc = &omap2_clksel_recalc,
};
* REVISIT: Also supports fast relock bypass - not included below
*/
static struct dpll_data dpll3_dd = {
- .mult_div1_reg = CM_CLKSEL1,
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
.div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
+ .clk_bypass = &sys_ck,
+ .clk_ref = &sys_ck,
.freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
- .control_reg = CM_CLKEN,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
.auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
- .autoidle_reg = CM_AUTOIDLE,
+ .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
.autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
- .idlest_reg = CM_IDLEST,
+ .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
- .bypass_clk = &sys_ck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
static struct clk dpll3_ck = {
.name = "dpll3_ck",
+ .ops = &clkops_null,
.parent = &sys_ck,
- .prcm_mod = PLL_MOD,
.dpll_data = &dpll3_dd,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | RECALC_ON_ENABLE,
.round_rate = &omap2_dpll_round_rate,
- .clkdm = { .name = "dpll3_clkdm" },
+ .clkdm_name = "dpll3_clkdm",
.recalc = &omap3_dpll_recalc,
};
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed
+ */
+static struct clk dpll3_x2_ck = {
+ .name = "dpll3_x2_ck",
+ .ops = &clkops_null,
+ .parent = &dpll3_ck,
+ .clkdm_name = "dpll3_clkdm",
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
static const struct clksel_rate div31_dpll3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
{ .div = 2, .val = 2, .flags = RATE_IN_343X },
/* DPLL3 output M2 - primary control point for CORE speed */
static struct clk dpll3_m2_ck = {
.name = "dpll3_m2_ck",
+ .ops = &clkops_null,
.parent = &dpll3_ck,
- .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
.clksel = div31_dpll3m2_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll3_clkdm" },
+ .clkdm_name = "dpll3_clkdm",
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap3_core_dpll_m2_set_rate,
.recalc = &omap2_clksel_recalc,
static struct clk core_ck = {
.name = "core_ck",
+ .ops = &clkops_null,
.parent = &dpll3_m2_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk dpll3_m2x2_ck = {
.name = "dpll3_m2x2_ck",
- .parent = &dpll3_m2_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll3_clkdm" },
- .recalc = &omap3_clkoutx2_recalc,
+ .ops = &clkops_null,
+ .parent = &dpll3_x2_ck,
+ .clkdm_name = "dpll3_clkdm",
+ .recalc = &followparent_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
/* This virtual clock is the source for dpll3_m3x2_ck */
static struct clk dpll3_m3_ck = {
.name = "dpll3_m3_ck",
+ .ops = &clkops_null,
.parent = &dpll3_ck,
- .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_DIV_DPLL3_MASK,
.clksel = div16_dpll3_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll3_clkdm" },
+ .clkdm_name = "dpll3_clkdm",
.recalc = &omap2_clksel_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll3_m3x2_ck = {
.name = "dpll3_m3x2_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll3_m3_ck,
- .prcm_mod = PLL_MOD,
- .enable_reg = CM_CLKEN,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
- .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
- .clkdm = { .name = "dpll3_clkdm" },
+ .flags = INVERT_ENABLE,
+ .clkdm_name = "dpll3_clkdm",
.recalc = &omap3_clkoutx2_recalc,
};
static struct clk emu_core_alwon_ck = {
.name = "emu_core_alwon_ck",
+ .ops = &clkops_null,
.parent = &dpll3_m3x2_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll3_clkdm" },
+ .clkdm_name = "dpll3_clkdm",
.recalc = &followparent_recalc,
};
/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
/* Type: DPLL */
static struct dpll_data dpll4_dd = {
- .mult_div1_reg = CM_CLKSEL2,
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
.mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
.div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
+ .clk_bypass = &sys_ck,
+ .clk_ref = &sys_ck,
.freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
- .control_reg = CM_CLKEN,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
- .autoidle_reg = CM_AUTOIDLE,
+ .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
.autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
- .idlest_reg = CM_IDLEST,
+ .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
.idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
- .bypass_clk = &sys_ck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
static struct clk dpll4_ck = {
.name = "dpll4_ck",
+ .ops = &clkops_noncore_dpll_ops,
.parent = &sys_ck,
- .prcm_mod = PLL_MOD,
.dpll_data = &dpll4_dd,
- .flags = CLOCK_IN_OMAP343X | RECALC_ON_ENABLE,
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
- .clkdm = { .name = "dpll4_clkdm" },
+ .set_rate = &omap3_dpll4_set_rate,
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap3_dpll_recalc,
};
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed --
+ * XXX does this serve any downstream clocks?
+ */
+static struct clk dpll4_x2_ck = {
+ .name = "dpll4_x2_ck",
+ .ops = &clkops_null,
+ .parent = &dpll4_ck,
+ .clkdm_name = "dpll4_clkdm",
+ .recalc = &omap3_clkoutx2_recalc,
+};
+
static const struct clksel div16_dpll4_clksel[] = {
{ .parent = &dpll4_ck, .rates = div16_dpll_rates },
{ .parent = NULL }
/* This virtual clock is the source for dpll4_m2x2_ck */
static struct clk dpll4_m2_ck = {
.name = "dpll4_m2_ck",
+ .ops = &clkops_null,
.parent = &dpll4_ck,
- .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_CM_CLKSEL3,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
.clksel_mask = OMAP3430_DIV_96M_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll4_clkdm" },
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m2x2_ck = {
.name = "dpll4_m2x2_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m2_ck,
- .prcm_mod = PLL_MOD,
- .enable_reg = CM_CLKEN,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_96M_SHIFT,
- .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
- .clkdm = { .name = "dpll4_clkdm" },
+ .flags = INVERT_ENABLE,
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap3_clkoutx2_recalc,
};
*/
static struct clk omap_96m_alwon_fck = {
.name = "omap_96m_alwon_fck",
+ .ops = &clkops_null,
.parent = &dpll4_m2x2_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk cm_96m_fck = {
.name = "cm_96m_fck",
+ .ops = &clkops_null,
.parent = &omap_96m_alwon_fck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk omap_96m_fck = {
.name = "omap_96m_fck",
+ .ops = &clkops_null,
.parent = &sys_ck,
- .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_96M_MASK,
.clksel = omap_96m_fck_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
/* This virtual clock is the source for dpll4_m3x2_ck */
static struct clk dpll4_m3_ck = {
.name = "dpll4_m3_ck",
+ .ops = &clkops_null,
.parent = &dpll4_ck,
- .prcm_mod = OMAP3430_DSS_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_TV_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll4_clkdm" },
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m3x2_ck = {
.name = "dpll4_m3x2_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m3_ck,
- .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_CLKEN,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
- .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
- .clkdm = { .name = "dpll4_clkdm" },
+ .flags = INVERT_ENABLE,
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap3_clkoutx2_recalc,
};
static struct clk omap_54m_fck = {
.name = "omap_54m_fck",
- .prcm_mod = PLL_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_54M_MASK,
.clksel = omap_54m_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
static struct clk omap_48m_fck = {
.name = "omap_48m_fck",
- .prcm_mod = PLL_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_SOURCE_48M_MASK,
.clksel = omap_48m_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
static struct clk omap_12m_fck = {
.name = "omap_12m_fck",
+ .ops = &clkops_null,
.parent = &omap_48m_fck,
.fixed_div = 4,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};
/* This virstual clock is the source for dpll4_m4x2_ck */
static struct clk dpll4_m4_ck = {
.name = "dpll4_m4_ck",
+ .ops = &clkops_null,
.parent = &dpll4_ck,
- .prcm_mod = OMAP3430_DSS_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll4_clkdm" },
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
.set_rate = &omap2_clksel_set_rate,
.round_rate = &omap2_clksel_round_rate,
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m4x2_ck = {
.name = "dpll4_m4x2_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m4_ck,
- .prcm_mod = PLL_MOD,
- .enable_reg = CM_CLKEN,
- .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
- .clkdm = { .name = "dpll4_clkdm" },
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
+ .flags = INVERT_ENABLE,
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap3_clkoutx2_recalc,
};
/* This virtual clock is the source for dpll4_m5x2_ck */
static struct clk dpll4_m5_ck = {
.name = "dpll4_m5_ck",
+ .ops = &clkops_null,
.parent = &dpll4_ck,
- .prcm_mod = OMAP3430_CAM_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll4_clkdm" },
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m5x2_ck = {
.name = "dpll4_m5x2_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m5_ck,
- .prcm_mod = PLL_MOD,
- .enable_reg = CM_CLKEN,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
- .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
- .clkdm = { .name = "dpll4_clkdm" },
+ .flags = INVERT_ENABLE,
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap3_clkoutx2_recalc,
};
/* This virtual clock is the source for dpll4_m6x2_ck */
static struct clk dpll4_m6_ck = {
.name = "dpll4_m6_ck",
+ .ops = &clkops_null,
.parent = &dpll4_ck,
- .prcm_mod = OMAP3430_EMU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_DIV_DPLL4_MASK,
.clksel = div16_dpll4_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll4_clkdm" },
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap2_clksel_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
static struct clk dpll4_m6x2_ck = {
.name = "dpll4_m6x2_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m6_ck,
- .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_CLKEN,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
- .flags = CLOCK_IN_OMAP343X | INVERT_ENABLE,
- .clkdm = { .name = "dpll4_clkdm" },
+ .flags = INVERT_ENABLE,
+ .clkdm_name = "dpll4_clkdm",
.recalc = &omap3_clkoutx2_recalc,
};
static struct clk emu_per_alwon_ck = {
.name = "emu_per_alwon_ck",
+ .ops = &clkops_null,
.parent = &dpll4_m6x2_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll4_clkdm" },
+ .clkdm_name = "dpll4_clkdm",
.recalc = &followparent_recalc,
};
/* Type: DPLL */
/* 3430ES2 only */
static struct dpll_data dpll5_dd = {
- .mult_div1_reg = OMAP3430ES2_CM_CLKSEL4,
+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
.mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
.div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+ .clk_bypass = &sys_ck,
+ .clk_ref = &sys_ck,
.freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
- .control_reg = OMAP3430ES2_CM_CLKEN2,
+ .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
.enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
.auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
.recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
.recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
- .autoidle_reg = OMAP3430ES2_CM_AUTOIDLE2_PLL,
+ .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
.autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
- .idlest_reg = CM_IDLEST2,
+ .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
.idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
- .bypass_clk = &sys_ck,
.max_multiplier = OMAP3_MAX_DPLL_MULT,
.min_divider = 1,
.max_divider = OMAP3_MAX_DPLL_DIV,
static struct clk dpll5_ck = {
.name = "dpll5_ck",
+ .ops = &clkops_noncore_dpll_ops,
.parent = &sys_ck,
- .prcm_mod = PLL_MOD,
.dpll_data = &dpll5_dd,
- .flags = CLOCK_IN_OMAP3430ES2 | RECALC_ON_ENABLE,
- .enable = &omap3_noncore_dpll_enable,
- .disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
- .clkdm = { .name = "dpll5_clkdm" },
+ .clkdm_name = "dpll5_clkdm",
.recalc = &omap3_dpll_recalc,
};
static struct clk dpll5_m2_ck = {
.name = "dpll5_m2_ck",
+ .ops = &clkops_null,
.parent = &dpll5_ck,
- .prcm_mod = PLL_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430ES2_CM_CLKSEL5,
+ .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
.clksel_mask = OMAP3430ES2_DIV_120M_MASK,
.clksel = div16_dpll5_clksel,
- .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "dpll5_clkdm" },
+ .clkdm_name = "dpll5_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk clkout2_src_ck = {
.name = "clkout2_src_ck",
- .prcm_mod = OMAP3430_CCR_MOD,
+ .ops = &clkops_omap2_dflt,
.init = &omap2_init_clksel_parent,
- .enable_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
+ .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
- .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
+ .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
.clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
.clksel = clkout2_src_clksel,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "cm_clkdm" },
+ .clkdm_name = "core_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk sys_clkout2 = {
.name = "sys_clkout2",
- .prcm_mod = OMAP3430_CCR_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_CM_CLKOUT_CTRL_OFFSET,
+ .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
.clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
static struct clk corex2_fck = {
.name = "corex2_fck",
+ .ops = &clkops_null,
.parent = &dpll3_m2x2_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
{ .parent = NULL }
};
+/*
+ * REVISIT: Are these in DPLL power domain or CM power domain? docs
+ * may be inconsistent here?
+ */
static struct clk dpll1_fck = {
.name = "dpll1_fck",
+ .ops = &clkops_null,
.parent = &core_ck,
- .prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
.clksel = div4_core_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
static struct clk mpu_ck = {
.name = "mpu_ck",
+ .ops = &clkops_null,
.parent = &dpll1_x2m2_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "mpu_clkdm" },
+ .clkdm_name = "mpu_clkdm",
.recalc = &followparent_recalc,
};
static struct clk arm_fck = {
.name = "arm_fck",
+ .ops = &clkops_null,
.parent = &mpu_ck,
- .prcm_mod = MPU_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_CM_IDLEST_PLL,
+ .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
.clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
.clksel = arm_fck_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "mpu_clkdm" },
.recalc = &omap2_clksel_recalc,
};
*/
static struct clk emu_mpu_alwon_ck = {
.name = "emu_mpu_alwon_ck",
+ .ops = &clkops_null,
.parent = &mpu_ck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "mpu_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk dpll2_fck = {
.name = "dpll2_fck",
+ .ops = &clkops_null,
.parent = &core_ck,
- .prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP3430_CM_CLKSEL1_PLL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
.clksel = div4_core_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
static struct clk iva2_ck = {
.name = "iva2_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll2_m2_ck,
- .prcm_mod = OMAP3430_IVA2_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "iva2_clkdm" },
+ .clkdm_name = "iva2_clkdm",
.recalc = &followparent_recalc,
};
static struct clk l3_ick = {
.name = "l3_ick",
+ .ops = &clkops_null,
.parent = &core_ck,
- .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_L3_MASK,
.clksel = div2_core_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l3_clkdm" },
+ .clkdm_name = "core_l3_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk l4_ick = {
.name = "l4_ick",
+ .ops = &clkops_null,
.parent = &l3_ick,
- .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_L4_MASK,
.clksel = div2_l3_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk rm_ick = {
.name = "rm_ick",
+ .ops = &clkops_null,
.parent = &l4_ick,
- .prcm_mod = WKUP_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_RM_MASK,
.clksel = div2_l4_clksel,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
static struct clk gfx_l3_ck = {
.name = "gfx_l3_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l3_ick,
- .prcm_mod = GFX_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk gfx_l3_fck = {
.name = "gfx_l3_fck",
+ .ops = &clkops_null,
.parent = &gfx_l3_ck,
- .prcm_mod = GFX_MOD,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_l3_clksel,
- .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "gfx_3430es1_clkdm" },
+ .clkdm_name = "gfx_3430es1_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gfx_l3_ick = {
.name = "gfx_l3_ick",
+ .ops = &clkops_null,
.parent = &gfx_l3_ck,
- .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "gfx_3430es1_clkdm" },
+ .clkdm_name = "gfx_3430es1_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gfx_cg1_ck = {
.name = "gfx_cg1_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &gfx_l3_fck, /* REVISIT: correct? */
- .prcm_mod = GFX_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "gfx_3430es1_clkdm" },
+ .clkdm_name = "gfx_3430es1_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gfx_cg2_ck = {
.name = "gfx_cg2_ck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &gfx_l3_fck, /* REVISIT: correct? */
- .prcm_mod = GFX_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "gfx_3430es1_clkdm" },
+ .clkdm_name = "gfx_3430es1_clkdm",
.recalc = &followparent_recalc,
};
static struct clk sgx_fck = {
.name = "sgx_fck",
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .prcm_mod = OMAP3430ES2_SGX_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
.clksel = sgx_clksel,
- .flags = CLOCK_IN_OMAP3430ES2,
- .clkdm = { .name = "sgx_clkdm" },
+ .clkdm_name = "sgx_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk sgx_ick = {
.name = "sgx_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l3_ick,
- .prcm_mod = OMAP3430ES2_SGX_MOD,
- .enable_reg = CM_ICLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
- .clkdm = { .name = "sgx_clkdm" },
+ .clkdm_name = "sgx_clkdm",
.recalc = &followparent_recalc,
};
static struct clk d2d_26m_fck = {
.name = "d2d_26m_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "d2d_clkdm" },
+ .clkdm_name = "d2d_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt10_fck = {
.name = "gpt10_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
- .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gpt11_fck = {
.name = "gpt11_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
- .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk cpefuse_fck = {
.name = "cpefuse_fck",
+ .ops = &clkops_omap2_dflt,
.parent = &sys_ck,
- .prcm_mod = CORE_MOD,
- .enable_reg = OMAP3430ES2_CM_FCLKEN3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_CPEFUSE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk ts_fck = {
.name = "ts_fck",
+ .ops = &clkops_omap2_dflt,
.parent = &omap_32k_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = OMAP3430ES2_CM_FCLKEN3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk usbtll_fck = {
.name = "usbtll_fck",
+ .ops = &clkops_omap2_dflt,
.parent = &dpll5_m2_ck,
- .prcm_mod = CORE_MOD,
- .enable_reg = OMAP3430ES2_CM_FCLKEN3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk core_96m_fck = {
.name = "core_96m_fck",
+ .ops = &clkops_null,
.parent = &omap_96m_fck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mmchs3_fck = {
.name = "mmchs_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &core_96m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mmchs2_fck = {
.name = "mmchs_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &core_96m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
- .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mspro_fck = {
.name = "mspro_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_96m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
- .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mmchs1_fck = {
.name = "mmchs_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_96m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
- .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk i2c3_fck = {
.name = "i2c_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &core_96m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
- .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk i2c2_fck = {
.name = "i2c_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &core_96m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
- .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk i2c1_fck = {
.name = "i2c_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &core_96m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
- .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
{ .parent = NULL }
};
-static struct clk mcbsp5_src_fck = {
- .name = "mcbsp_src_fck",
+static struct clk mcbsp5_fck = {
+ .name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 5,
- .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
.clksel = mcbsp_15_clksel,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
-static struct clk mcbsp5_fck = {
+static struct clk mcbsp1_fck = {
.name = "mcbsp_fck",
- .id = 5,
- .parent = &mcbsp5_src_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
- .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
- .recalc = &followparent_recalc,
-};
-
-static struct clk mcbsp1_src_fck = {
- .name = "mcbsp_src_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
- .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP2_CONTROL_DEVCONF0,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
.clksel = mcbsp_15_clksel,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
-static struct clk mcbsp1_fck = {
- .name = "mcbsp_fck",
- .id = 1,
- .parent = &mcbsp1_src_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
- .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
- .recalc = &followparent_recalc,
-};
-
/* CORE_48M_FCK-derived clocks */
static struct clk core_48m_fck = {
.name = "core_48m_fck",
+ .ops = &clkops_null,
.parent = &omap_48m_fck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcspi4_fck = {
.name = "mcspi_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 4,
.parent = &core_48m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
- .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk mcspi3_fck = {
.name = "mcspi_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &core_48m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
- .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk mcspi2_fck = {
.name = "mcspi_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &core_48m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
- .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk mcspi1_fck = {
.name = "mcspi_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &core_48m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
- .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk uart2_fck = {
.name = "uart2_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_48m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
- .idlest_bit = OMAP3430_ST_UART2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk uart1_fck = {
.name = "uart1_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_48m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
- .idlest_bit = OMAP3430_ST_UART1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
-/* XXX doublecheck: is this idle or standby? */
static struct clk fshostusb_fck = {
.name = "fshostusb_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_48m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
- .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk core_12m_fck = {
.name = "core_12m_fck",
+ .ops = &clkops_null,
.parent = &omap_12m_fck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk hdq_fck = {
.name = "hdq_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_12m_fck,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
- .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
{ .parent = NULL }
};
-static struct clk ssi_ssr_fck_3430es1 = {
+static struct clk ssi_ssr_fck = {
.name = "ssi_ssr_fck",
+ .ops = &clkops_omap2_dflt,
.init = &omap2_init_clksel_parent,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_clksel,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
-static struct clk ssi_ssr_fck_3430es2 = {
- .name = "ssi_ssr_fck",
- .init = &omap2_init_clksel_parent,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_FCLKEN1,
- .enable_bit = OMAP3430_EN_SSI_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
- .clksel_reg = CM_CLKSEL,
- .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
- .clksel = ssi_ssr_clksel,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
- .recalc = &omap2_clksel_recalc,
-};
-
-/* It's unfortunate that we need to duplicate this clock. */
-static struct clk ssi_sst_fck_3430es1 = {
+static struct clk ssi_sst_fck = {
.name = "ssi_sst_fck",
- .parent = &ssi_ssr_fck_3430es1,
+ .ops = &clkops_null,
+ .parent = &ssi_ssr_fck,
.fixed_div = 2,
- .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
- .recalc = &omap2_fixed_divisor_recalc,
-};
-
-static struct clk ssi_sst_fck_3430es2 = {
- .name = "ssi_sst_fck",
- .parent = &ssi_ssr_fck_3430es2,
- .fixed_div = 2,
- .flags = CLOCK_IN_OMAP3430ES2 | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};
*/
static struct clk core_l3_ick = {
.name = "core_l3_ick",
+ .ops = &clkops_null,
.parent = &l3_ick,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l3_clkdm" },
+ .init = &omap2_init_clk_clkdm,
+ .clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc,
};
-static struct clk hsotgusb_ick_3430es1 = {
+static struct clk hsotgusb_ick = {
.name = "hsotgusb_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "core_l3_clkdm" },
- .recalc = &followparent_recalc,
-};
-
-static struct clk hsotgusb_ick_3430es2 = {
- .name = "hsotgusb_ick",
- .parent = &core_l3_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
- .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "core_l3_clkdm" },
+ .clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc,
};
static struct clk sdrc_ick = {
.name = "sdrc_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l3_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SDRC_SHIFT,
- .idlest_bit = OMAP3430_ST_SDRC_SHIFT,
- .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
- .clkdm = { .name = "core_l3_clkdm" },
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpmc_fck = {
.name = "gpmc_fck",
+ .ops = &clkops_null,
.parent = &core_l3_ick,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
- ENABLE_ON_INIT,
- .clkdm = { .name = "core_l3_clkdm" },
+ .flags = ENABLE_ON_INIT, /* huh? */
+ .clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc,
};
static struct clk security_l3_ick = {
.name = "security_l3_ick",
+ .ops = &clkops_null,
.parent = &l3_ick,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk pka_ick = {
.name = "pka_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &security_l3_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_PKA_SHIFT,
- .idlest_bit = OMAP3430_ST_PKA_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk core_l4_ick = {
.name = "core_l4_ick",
+ .ops = &clkops_null,
.parent = &l4_ick,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
+ .init = &omap2_init_clk_clkdm,
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk usbtll_ick = {
.name = "usbtll_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mmchs3_ick = {
.name = "mmchs_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_MMC3_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
/* Intersystem Communication Registers - chassis mode only */
static struct clk icr_ick = {
.name = "icr_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_ICR_SHIFT,
- .idlest_bit = OMAP3430_ST_ICR_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk aes2_ick = {
.name = "aes2_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_AES2_SHIFT,
- .idlest_bit = OMAP3430_ST_AES2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk sha12_ick = {
.name = "sha12_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
- .idlest_bit = OMAP3430_ST_SHA12_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk des2_ick = {
.name = "des2_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_DES2_SHIFT,
- .idlest_bit = OMAP3430_ST_DES2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mmchs2_ick = {
.name = "mmchs_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
- .idlest_bit = OMAP3430_ST_MMC2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mmchs1_ick = {
.name = "mmchs_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
- .idlest_bit = OMAP3430_ST_MMC1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mspro_ick = {
.name = "mspro_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
- .idlest_bit = OMAP3430_ST_MSPRO_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk hdq_ick = {
.name = "hdq_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
- .idlest_bit = OMAP3430_ST_HDQ_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcspi4_ick = {
.name = "mcspi_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 4,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
- .idlest_bit = OMAP3430_ST_MCSPI4_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcspi3_ick = {
.name = "mcspi_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
- .idlest_bit = OMAP3430_ST_MCSPI3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcspi2_ick = {
.name = "mcspi_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
- .idlest_bit = OMAP3430_ST_MCSPI2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcspi1_ick = {
.name = "mcspi_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
- .idlest_bit = OMAP3430_ST_MCSPI1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk i2c3_ick = {
.name = "i2c_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
- .idlest_bit = OMAP3430_ST_I2C3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk i2c2_ick = {
.name = "i2c_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
- .idlest_bit = OMAP3430_ST_I2C2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk i2c1_ick = {
.name = "i2c_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
- .idlest_bit = OMAP3430_ST_I2C1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk uart2_ick = {
.name = "uart2_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
- .idlest_bit = OMAP3430_ST_UART2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk uart1_ick = {
.name = "uart1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
- .idlest_bit = OMAP3430_ST_UART1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt11_ick = {
.name = "gpt11_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT11_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt10_ick = {
.name = "gpt10_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT10_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcbsp5_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 5,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP5_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcbsp1_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 1,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk fac_ick = {
.name = "fac_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
- .idlest_bit = OMAP3430ES1_ST_FAC_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
- .idlest_bit = OMAP3430_ST_MAILBOXES_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
- .idlest_bit = OMAP3430_ST_OMAPCTRL_SHIFT,
- .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
+ .flags = ENABLE_ON_INIT,
.recalc = &followparent_recalc,
};
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
+ .ops = &clkops_null,
.parent = &l4_ick,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
-static struct clk ssi_ick_3430es1 = {
+static struct clk ssi_ick = {
.name = "ssi_ick",
+ .ops = &clkops_omap2_dflt,
.parent = &ssi_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
-static struct clk ssi_ick_3430es2 = {
- .name = "ssi_ick",
- .parent = &ssi_l4_ick,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN1,
- .enable_bit = OMAP3430_EN_SSI_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
- .recalc = &followparent_recalc,
-};
+/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me */
-/*
- * REVISIT: Technically the TRM claims that this is CORE_CLK based,
- * but l4_ick makes more sense to me
- */
static const struct clksel usb_l4_clksel[] = {
{ .parent = &l4_ick, .rates = div2_rates },
{ .parent = NULL },
static struct clk usb_l4_ick = {
.name = "usb_l4_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ick,
- .prcm_mod = CORE_MOD,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_ICLKEN1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
- .idlest_bit = OMAP3430ES1_ST_FSHOSTUSB_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
.clksel = usb_l4_clksel,
- .flags = CLOCK_IN_OMAP3430ES1 | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};
static struct clk security_l4_ick2 = {
.name = "security_l4_ick2",
+ .ops = &clkops_null,
.parent = &l4_ick,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk aes1_ick = {
.name = "aes1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &security_l4_ick2,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_AES1_SHIFT,
- .idlest_bit = OMAP3430_ST_AES1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk rng_ick = {
.name = "rng_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &security_l4_ick2,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_RNG_SHIFT,
- .idlest_bit = OMAP3430_ST_RNG_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk sha11_ick = {
.name = "sha11_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &security_l4_ick2,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
- .idlest_bit = OMAP3430_ST_SHA11_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk des1_ick = {
.name = "des1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &security_l4_ick2,
- .prcm_mod = CORE_MOD,
- .enable_reg = CM_ICLKEN2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP3430_EN_DES1_SHIFT,
- .idlest_bit = OMAP3430_ST_DES1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};
/* DSS */
-static struct clk dss1_alwon_fck_3430es1 = {
+static struct clk dss1_alwon_fck = {
.name = "dss1_alwon_fck",
+ .ops = &clkops_omap2_dflt,
.parent = &dpll4_m4x2_ck,
- .prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "dss_clkdm" },
- .recalc = &followparent_recalc,
-};
-
-static struct clk dss1_alwon_fck_3430es2 = {
- .name = "dss1_alwon_fck",
- .parent = &dpll4_m4x2_ck,
- .init = &omap2_init_clksel_parent,
- .prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = CM_FCLKEN,
- .enable_bit = OMAP3430_EN_DSS1_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "dss_clkdm" },
+ .clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
static struct clk dss_tv_fck = {
.name = "dss_tv_fck",
+ .ops = &clkops_omap2_dflt,
.parent = &omap_54m_fck,
- .prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
+ .clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
static struct clk dss_96m_fck = {
.name = "dss_96m_fck",
+ .ops = &clkops_omap2_dflt,
.parent = &omap_96m_fck,
- .prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "dss_clkdm" },
+ .clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
static struct clk dss2_alwon_fck = {
.name = "dss2_alwon_fck",
+ .ops = &clkops_omap2_dflt,
.parent = &sys_ck,
- .prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "dss_clkdm" },
+ .clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
-static struct clk dss_ick_3430es1 = {
+static struct clk dss_ick = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
+ .ops = &clkops_omap2_dflt,
.parent = &l4_ick,
- .prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = CM_ICLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES1,
- .clkdm = { .name = "dss_clkdm" },
- .recalc = &followparent_recalc,
-};
-
-static struct clk dss_ick_3430es2 = {
- /* Handles both L3 and L4 clocks */
- .name = "dss_ick",
- .parent = &l4_ick,
- .prcm_mod = OMAP3430_DSS_MOD,
- .enable_reg = CM_ICLKEN,
- .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "dss_clkdm" },
+ .clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
static struct clk cam_mclk = {
.name = "cam_mclk",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m5x2_ck,
- .prcm_mod = OMAP3430_CAM_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "cam_clkdm" },
+ .clkdm_name = "cam_clkdm",
.recalc = &followparent_recalc,
};
static struct clk cam_ick = {
/* Handles both L3 and L4 clocks */
.name = "cam_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ick,
- .prcm_mod = OMAP3430_CAM_MOD,
- .enable_reg = CM_ICLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "cam_clkdm" },
+ .clkdm_name = "cam_clkdm",
.recalc = &followparent_recalc,
};
static struct clk csi2_96m_fck = {
.name = "csi2_96m_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &core_96m_fck,
- .prcm_mod = OMAP3430_CAM_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CSI2_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "cam_clkdm" },
+ .clkdm_name = "cam_clkdm",
.recalc = &followparent_recalc,
};
static struct clk usbhost_120m_fck = {
.name = "usbhost_120m_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &dpll5_m2_ck,
- .prcm_mod = OMAP3430ES2_USBHOST_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2,
- .clkdm = { .name = "usbhost_clkdm" },
+ .clkdm_name = "usbhost_clkdm",
.recalc = &followparent_recalc,
};
static struct clk usbhost_48m_fck = {
.name = "usbhost_48m_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &omap_48m_fck,
- .prcm_mod = OMAP3430ES2_USBHOST_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "usbhost_clkdm" },
+ .clkdm_name = "usbhost_clkdm",
.recalc = &followparent_recalc,
};
static struct clk usbhost_ick = {
/* Handles both L3 and L4 clocks */
.name = "usbhost_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &l4_ick,
- .prcm_mod = OMAP3430ES2_USBHOST_MOD,
- .enable_reg = CM_ICLKEN,
+ .init = &omap2_init_clk_clkdm,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "usbhost_clkdm" },
+ .clkdm_name = "usbhost_clkdm",
.recalc = &followparent_recalc,
};
/* 3430ES2 only */
static struct clk usim_fck = {
.name = "usim_fck",
- .prcm_mod = WKUP_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
.clksel = usim_clksel,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};
/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
static struct clk gpt1_fck = {
.name = "gpt1_fck",
- .prcm_mod = WKUP_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk wkup_32k_fck = {
.name = "wkup_32k_fck",
+ .ops = &clkops_null,
+ .init = &omap2_init_clk_clkdm,
.parent = &omap_32k_fck,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio1_dbck = {
.name = "gpio1_dbck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_32k_fck,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk wdt2_fck = {
.name = "wdt2_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_32k_fck,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
- .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk wkup_l4_ick = {
.name = "wkup_l4_ick",
+ .ops = &clkops_null,
.parent = &sys_ck,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
static struct clk usim_ick = {
.name = "usim_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_l4_ick,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
- .idlest_bit = OMAP3430ES2_ST_USIMOCP_SHIFT,
- .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk wdt2_ick = {
.name = "wdt2_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_l4_ick,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
- .idlest_bit = OMAP3430_ST_WDT2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk wdt1_ick = {
.name = "wdt1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_l4_ick,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
- .idlest_bit = OMAP3430_ST_WDT1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio1_ick = {
.name = "gpio1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_l4_ick,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk omap_32ksync_ick = {
.name = "omap_32ksync_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_l4_ick,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
- .idlest_bit = OMAP3430_ST_32KSYNC_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
+/* XXX This clock no longer exists in 3430 TRM rev F */
static struct clk gpt12_ick = {
.name = "gpt12_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_l4_ick,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt1_ick = {
.name = "gpt1_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &wkup_l4_ick,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
+ .clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
static struct clk per_96m_fck = {
.name = "per_96m_fck",
+ .ops = &clkops_null,
.parent = &omap_96m_alwon_fck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "per_clkdm" },
+ .init = &omap2_init_clk_clkdm,
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk per_48m_fck = {
.name = "per_48m_fck",
+ .ops = &clkops_null,
.parent = &omap_48m_fck,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "per_clkdm" },
+ .init = &omap2_init_clk_clkdm,
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk uart3_fck = {
.name = "uart3_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_48m_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
- .idlest_bit = OMAP3430_ST_UART3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt2_fck = {
.name = "gpt2_fck",
- .prcm_mod = OMAP3430_PER_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gpt3_fck = {
.name = "gpt3_fck",
- .prcm_mod = OMAP3430_PER_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gpt4_fck = {
.name = "gpt4_fck",
- .prcm_mod = OMAP3430_PER_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gpt5_fck = {
.name = "gpt5_fck",
- .prcm_mod = OMAP3430_PER_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gpt6_fck = {
.name = "gpt6_fck",
- .prcm_mod = OMAP3430_PER_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gpt7_fck = {
.name = "gpt7_fck",
- .prcm_mod = OMAP3430_PER_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gpt8_fck = {
.name = "gpt8_fck",
- .prcm_mod = OMAP3430_PER_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk gpt9_fck = {
.name = "gpt9_fck",
- .prcm_mod = OMAP3430_PER_MOD,
+ .ops = &clkops_omap2_dflt_wait,
.init = &omap2_init_clksel_parent,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
- .clksel_reg = CM_CLKSEL,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
.clksel = omap343x_gpt_clksel,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk per_32k_alwon_fck = {
.name = "per_32k_alwon_fck",
+ .ops = &clkops_null,
.parent = &omap_32k_fck,
- .clkdm = { .name = "per_clkdm" },
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio6_dbck = {
.name = "gpio6_dbck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_32k_alwon_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio5_dbck = {
.name = "gpio5_dbck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_32k_alwon_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio4_dbck = {
.name = "gpio4_dbck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_32k_alwon_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio3_dbck = {
.name = "gpio3_dbck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_32k_alwon_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio2_dbck = {
.name = "gpio2_dbck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_32k_alwon_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk wdt3_fck = {
.name = "wdt3_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_32k_alwon_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
- .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk per_l4_ick = {
.name = "per_l4_ick",
+ .ops = &clkops_null,
.parent = &l4_ick,
- .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio6_ick = {
.name = "gpio6_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO6_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio5_ick = {
.name = "gpio5_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO5_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio4_ick = {
.name = "gpio4_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO4_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio3_ick = {
.name = "gpio3_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpio2_ick = {
.name = "gpio2_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
- .idlest_bit = OMAP3430_ST_GPIO2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk wdt3_ick = {
.name = "wdt3_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
- .idlest_bit = OMAP3430_ST_WDT3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk uart3_ick = {
.name = "uart3_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
- .idlest_bit = OMAP3430_ST_UART3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt9_ick = {
.name = "gpt9_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT9_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt8_ick = {
.name = "gpt8_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT8_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt7_ick = {
.name = "gpt7_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT7_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt6_ick = {
.name = "gpt6_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT6_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt5_ick = {
.name = "gpt5_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT5_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt4_ick = {
.name = "gpt4_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT4_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt3_ick = {
.name = "gpt3_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk gpt2_ick = {
.name = "gpt2_ick",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
- .idlest_bit = OMAP3430_ST_GPT2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcbsp2_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcbsp3_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
static struct clk mcbsp4_ick = {
.name = "mcbsp_ick",
+ .ops = &clkops_omap2_dflt_wait,
.id = 4,
.parent = &per_l4_ick,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_ICLKEN,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
{ .parent = NULL }
};
-static struct clk mcbsp2_src_fck = {
- .name = "mcbsp_src_fck",
- .id = 2,
- .prcm_mod = CLK_REG_IN_SCM,
- .init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP2_CONTROL_DEVCONF0,
- .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
- .clksel = mcbsp_234_clksel,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "per_clkdm" },
- .recalc = &omap2_clksel_recalc,
-};
-
static struct clk mcbsp2_fck = {
.name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 2,
- .parent = &mcbsp2_src_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
- .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk mcbsp3_src_fck = {
- .name = "mcbsp_src_fck",
- .id = 3,
- .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
- .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+ .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
.clksel = mcbsp_234_clksel,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk mcbsp3_fck = {
.name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 3,
- .parent = &mcbsp3_src_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
- .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP3_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
- .recalc = &omap2_clksel_recalc,
-};
-
-static struct clk mcbsp4_src_fck = {
- .name = "mcbsp_src_fck",
- .id = 4,
- .prcm_mod = CLK_REG_IN_SCM,
.init = &omap2_init_clksel_parent,
- .clksel_reg = OMAP343X_CONTROL_DEVCONF1,
- .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
.clksel = mcbsp_234_clksel,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "per_clkdm" },
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk mcbsp4_fck = {
.name = "mcbsp_fck",
+ .ops = &clkops_omap2_dflt_wait,
.id = 4,
- .parent = &mcbsp4_src_fck,
- .prcm_mod = OMAP3430_PER_MOD,
- .enable_reg = CM_FCLKEN,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
- .idlest_bit = OMAP3430_ST_MCBSP4_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "per_clkdm" },
+ .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+ .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
+ .clksel = mcbsp_234_clksel,
+ .clkdm_name = "per_clkdm",
.recalc = &omap2_clksel_recalc,
};
*/
static struct clk emu_src_ck = {
.name = "emu_src_ck",
- .prcm_mod = OMAP3430_EMU_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_MUX_CTRL_MASK,
.clksel = emu_src_clksel,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "emu_clkdm" },
+ .clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk pclk_fck = {
.name = "pclk_fck",
- .prcm_mod = OMAP3430_EMU_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
.clksel = pclk_emu_clksel,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "emu_clkdm" },
+ .clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk pclkx2_fck = {
.name = "pclkx2_fck",
- .prcm_mod = OMAP3430_EMU_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
.clksel = pclkx2_emu_clksel,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "emu_clkdm" },
+ .clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk atclk_fck = {
.name = "atclk_fck",
- .prcm_mod = OMAP3430_EMU_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
.clksel = atclk_emu_clksel,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "emu_clkdm" },
+ .clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk traceclk_src_fck = {
.name = "traceclk_src_fck",
- .prcm_mod = OMAP3430_EMU_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
.clksel = emu_src_clksel,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "emu_clkdm" },
+ .clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk traceclk_fck = {
.name = "traceclk_fck",
- .prcm_mod = OMAP3430_EMU_MOD,
+ .ops = &clkops_null,
.init = &omap2_init_clksel_parent,
- .clksel_reg = CM_CLKSEL1,
+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
.clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
.clksel = traceclk_clksel,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "emu_clkdm" },
+ .clkdm_name = "emu_clkdm",
.recalc = &omap2_clksel_recalc,
};
/* SmartReflex fclk (VDD1) */
static struct clk sr1_fck = {
.name = "sr1_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR1_SHIFT,
- .idlest_bit = OMAP3430_ST_SR1_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
/* SmartReflex fclk (VDD2) */
static struct clk sr2_fck = {
.name = "sr2_fck",
+ .ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
- .prcm_mod = WKUP_MOD,
- .enable_reg = CM_FCLKEN,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR2_SHIFT,
- .idlest_bit = OMAP3430_ST_SR2_SHIFT,
- .flags = CLOCK_IN_OMAP343X | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk sr_l4_ick = {
.name = "sr_l4_ick",
+ .ops = &clkops_null, /* RMK: missing? */
.parent = &l4_ick,
- .flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
/* SECURE_32K_FCK clocks */
-/* XXX Make sure idlest_bit/wait_ready with no enable_bit works */
+/* XXX This clock no longer exists in 3430 TRM rev F */
static struct clk gpt12_fck = {
.name = "gpt12_fck",
+ .ops = &clkops_null,
.parent = &secure_32k_fck,
- .idlest_bit = OMAP3430_ST_GPT12_SHIFT,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED | WAIT_READY,
- .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};
static struct clk wdt1_fck = {
.name = "wdt1_fck",
+ .ops = &clkops_null,
.parent = &secure_32k_fck,
- .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm = { .name = "prm_clkdm" },
- .recalc = &followparent_recalc,
-};
-
-static struct clk *onchip_34xx_clks[] __initdata = {
- &omap_32k_fck,
- &virt_12m_ck,
- &virt_13m_ck,
- &virt_16_8m_ck,
- &virt_19_2m_ck,
- &virt_26m_ck,
- &virt_38_4m_ck,
- &osc_sys_ck,
- &sys_ck,
- &sys_altclk,
- &mcbsp_clks,
- &sys_clkout1,
- &dpll1_ck,
- &dpll1_x2_ck,
- &dpll1_x2m2_ck,
- &dpll2_ck,
- &dpll2_m2_ck,
- &dpll3_ck,
- &core_ck,
- &dpll3_m2_ck,
- &dpll3_m2x2_ck,
- &dpll3_m3_ck,
- &dpll3_m3x2_ck,
- &emu_core_alwon_ck,
- &dpll4_ck,
- &omap_96m_alwon_fck,
- &omap_96m_fck,
- &cm_96m_fck,
- &omap_54m_fck,
- &omap_48m_fck,
- &omap_12m_fck,
- &dpll4_m2_ck,
- &dpll4_m2x2_ck,
- &dpll4_m3_ck,
- &dpll4_m3x2_ck,
- &dpll4_m4_ck,
- &dpll4_m4x2_ck,
- &dpll4_m5_ck,
- &dpll4_m5x2_ck,
- &dpll4_m6_ck,
- &dpll4_m6x2_ck,
- &emu_per_alwon_ck,
- &dpll5_ck,
- &dpll5_m2_ck,
- &clkout2_src_ck,
- &sys_clkout2,
- &corex2_fck,
- &dpll1_fck,
- &mpu_ck,
- &arm_fck,
- &emu_mpu_alwon_ck,
- &dpll2_fck,
- &iva2_ck,
- &l3_ick,
- &l4_ick,
- &rm_ick,
- &gfx_l3_ck,
- &gfx_l3_fck,
- &gfx_l3_ick,
- &gfx_cg1_ck,
- &gfx_cg2_ck,
- &sgx_fck,
- &sgx_ick,
- &d2d_26m_fck,
- &gpt10_fck,
- &gpt11_fck,
- &cpefuse_fck,
- &ts_fck,
- &usbtll_fck,
- &core_96m_fck,
- &mmchs3_fck,
- &mmchs2_fck,
- &mspro_fck,
- &mmchs1_fck,
- &i2c3_fck,
- &i2c2_fck,
- &i2c1_fck,
- &mcbsp5_src_fck,
- &mcbsp5_fck,
- &mcbsp1_src_fck,
- &mcbsp1_fck,
- &core_48m_fck,
- &mcspi4_fck,
- &mcspi3_fck,
- &mcspi2_fck,
- &mcspi1_fck,
- &uart2_fck,
- &uart1_fck,
- &fshostusb_fck,
- &core_12m_fck,
- &hdq_fck,
- &ssi_ssr_fck_3430es1,
- &ssi_ssr_fck_3430es2,
- &ssi_sst_fck_3430es1,
- &ssi_sst_fck_3430es2,
- &core_l3_ick,
- &hsotgusb_ick_3430es1,
- &hsotgusb_ick_3430es2,
- &sdrc_ick,
- &gpmc_fck,
- &security_l3_ick,
- &pka_ick,
- &core_l4_ick,
- &usbtll_ick,
- &mmchs3_ick,
- &icr_ick,
- &aes2_ick,
- &sha12_ick,
- &des2_ick,
- &mmchs2_ick,
- &mmchs1_ick,
- &mspro_ick,
- &hdq_ick,
- &mcspi4_ick,
- &mcspi3_ick,
- &mcspi2_ick,
- &mcspi1_ick,
- &i2c3_ick,
- &i2c2_ick,
- &i2c1_ick,
- &uart2_ick,
- &uart1_ick,
- &gpt11_ick,
- &gpt10_ick,
- &mcbsp5_ick,
- &mcbsp1_ick,
- &fac_ick,
- &mailboxes_ick,
- &omapctrl_ick,
- &ssi_l4_ick,
- &ssi_ick_3430es1,
- &ssi_ick_3430es2,
- &usb_l4_ick,
- &security_l4_ick2,
- &aes1_ick,
- &rng_ick,
- &sha11_ick,
- &des1_ick,
- &dss1_alwon_fck_3430es1,
- &dss1_alwon_fck_3430es2,
- &dss_tv_fck,
- &dss_96m_fck,
- &dss2_alwon_fck,
- &dss_ick_3430es1,
- &dss_ick_3430es2,
- &cam_mclk,
- &cam_ick,
- &csi2_96m_fck,
- &usbhost_120m_fck,
- &usbhost_48m_fck,
- &usbhost_ick,
- &usim_fck,
- &gpt1_fck,
- &wkup_32k_fck,
- &gpio1_dbck,
- &wdt2_fck,
- &wkup_l4_ick,
- &usim_ick,
- &wdt2_ick,
- &wdt1_ick,
- &gpio1_ick,
- &omap_32ksync_ick,
- &gpt12_ick,
- &gpt1_ick,
- &per_96m_fck,
- &per_48m_fck,
- &uart3_fck,
- &gpt2_fck,
- &gpt3_fck,
- &gpt4_fck,
- &gpt5_fck,
- &gpt6_fck,
- &gpt7_fck,
- &gpt8_fck,
- &gpt9_fck,
- &per_32k_alwon_fck,
- &gpio6_dbck,
- &gpio5_dbck,
- &gpio4_dbck,
- &gpio3_dbck,
- &gpio2_dbck,
- &wdt3_fck,
- &per_l4_ick,
- &gpio6_ick,
- &gpio5_ick,
- &gpio4_ick,
- &gpio3_ick,
- &gpio2_ick,
- &wdt3_ick,
- &uart3_ick,
- &gpt9_ick,
- &gpt8_ick,
- &gpt7_ick,
- &gpt6_ick,
- &gpt5_ick,
- &gpt4_ick,
- &gpt3_ick,
- &gpt2_ick,
- &mcbsp2_ick,
- &mcbsp3_ick,
- &mcbsp4_ick,
- &mcbsp2_src_fck,
- &mcbsp2_fck,
- &mcbsp3_src_fck,
- &mcbsp3_fck,
- &mcbsp4_src_fck,
- &mcbsp4_fck,
- &emu_src_ck,
- &pclk_fck,
- &pclkx2_fck,
- &atclk_fck,
- &traceclk_src_fck,
- &traceclk_fck,
- &sr1_fck,
- &sr2_fck,
- &sr_l4_ick,
- &secure_32k_fck,
- &gpt12_fck,
- &wdt1_fck,
+ .recalc = &followparent_recalc,
};
#endif
projects / linux-2.6-omap-h63xx.git / blobdiff