OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c files

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock24xx.h

diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index b2442475fb47f6b8856cf47d3e93fb6222c54310..72003f743efdbb29c173f4b72844af3c8e2a1edd 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -24,13 +24,13 @@
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 
-static void omap2_table_mpu_recalc(struct clk *clk);
+static unsigned long omap2_table_mpu_recalc(struct clk *clk);
 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
-static void omap2_sys_clk_recalc(struct clk *clk);
-static void omap2_osc_clk_recalc(struct clk *clk);
-static void omap2_sys_clk_recalc(struct clk *clk);
-static void omap2_dpllcore_recalc(struct clk *clk);
+static unsigned long omap2_sys_clk_recalc(struct clk *clk);
+static unsigned long omap2_osc_clk_recalc(struct clk *clk);
+static unsigned long omap2_sys_clk_recalc(struct clk *clk);
+static unsigned long omap2_dpllcore_recalc(struct clk *clk);
 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
 
 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
@@ -621,7 +621,15 @@ static struct clk func_32k_ck = {
        .name           = "func_32k_ck",
        .ops            = &clkops_null,
        .rate           = 32000,
-       .flags          = RATE_FIXED | RATE_PROPAGATES,
+       .flags          = RATE_FIXED,
+       .clkdm_name     = "wkup_clkdm",
+};
+
+static struct clk secure_32k_fck = {
+       .name           = "secure_32k_fck",
+       .ops            = &clkops_null,
+       .rate           = 32768,
+       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
 };
 
@@ -629,7 +637,6 @@ static struct clk func_32k_ck = {
 static struct clk osc_ck = {           /* (*12, *13, 19.2, *26, 38.4)MHz */
        .name           = "osc_ck",
        .ops            = &clkops_oscck,
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_osc_clk_recalc,
 };
@@ -639,7 +646,6 @@ static struct clk sys_ck = {                /* (*12, *13, 19.2, 26, 38.4)MHz */
        .name           = "sys_ck",             /* ~ ref_clk also */
        .ops            = &clkops_null,
        .parent         = &osc_ck,
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_sys_clk_recalc,
 };
@@ -648,7 +654,7 @@ static struct clk alt_ck = {                /* Typical 54M or 48M, may not exist */
        .name           = "alt_ck",
        .ops            = &clkops_null,
        .rate           = 54000000,
-       .flags          = RATE_FIXED | RATE_PROPAGATES,
+       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
 };
 
@@ -665,7 +671,12 @@ static struct dpll_data dpll_dd = {
        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+       .clk_bypass             = &sys_ck,
+       .clk_ref                = &sys_ck,
+       .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+       .enable_mask            = OMAP24XX_EN_DPLL_MASK,
        .max_multiplier         = 1024,
+       .min_divider            = 1,
        .max_divider            = 16,
        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
@@ -679,7 +690,6 @@ static struct clk dpll_ck = {
        .ops            = &clkops_null,
        .parent         = &sys_ck,              /* Can be func_32k also */
        .dpll_data      = &dpll_dd,
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_dpllcore_recalc,
        .set_rate       = &omap2_reprogram_dpllcore,
@@ -690,7 +700,7 @@ static struct clk apll96_ck = {
        .ops            = &clkops_fixed,
        .parent         = &sys_ck,
        .rate           = 96000000,
-       .flags          = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+       .flags          = RATE_FIXED | ENABLE_ON_INIT,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
@@ -701,7 +711,7 @@ static struct clk apll54_ck = {
        .ops            = &clkops_fixed,
        .parent         = &sys_ck,
        .rate           = 54000000,
-       .flags          = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+       .flags          = RATE_FIXED | ENABLE_ON_INIT,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
@@ -733,7 +743,6 @@ static struct clk func_54m_ck = {
        .name           = "func_54m_ck",
        .ops            = &clkops_null,
        .parent         = &apll54_ck,   /* can also be alt_clk */
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -746,7 +755,6 @@ static struct clk core_ck = {
        .name           = "core_ck",
        .ops            = &clkops_null,
        .parent         = &dpll_ck,             /* can also be 32k */
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &followparent_recalc,
 };
@@ -773,7 +781,6 @@ static struct clk func_96m_ck = {
        .name           = "func_96m_ck",
        .ops            = &clkops_null,
        .parent         = &apll96_ck,
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -806,7 +813,6 @@ static struct clk func_48m_ck = {
        .name           = "func_48m_ck",
        .ops            = &clkops_null,
        .parent         = &apll96_ck,    /* 96M or Alt */
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -822,7 +828,6 @@ static struct clk func_12m_ck = {
        .ops            = &clkops_null,
        .parent         = &func_48m_ck,
        .fixed_div      = 4,
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_fixed_divisor_recalc,
 };
@@ -875,7 +880,6 @@ static struct clk sys_clkout_src = {
        .name           = "sys_clkout_src",
        .ops            = &clkops_omap2_dflt,
        .parent         = &func_54m_ck,
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
@@ -920,7 +924,6 @@ static struct clk sys_clkout2_src = {
        .name           = "sys_clkout2_src",
        .ops            = &clkops_omap2_dflt,
        .parent         = &func_54m_ck,
-       .flags          = RATE_PROPAGATES,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
@@ -991,7 +994,7 @@ static struct clk mpu_ck = {        /* Control cpu */
        .name           = "mpu_ck",
        .ops            = &clkops_null,
        .parent         = &core_ck,
-       .flags          = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm_name     = "mpu_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -1033,7 +1036,7 @@ static struct clk dsp_fck = {
        .name           = "dsp_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_ck,
-       .flags          = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm_name     = "dsp_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -1101,7 +1104,7 @@ static struct clk iva1_ifck = {
        .name           = "iva1_ifck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_ck,
-       .flags          = CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
+       .flags          = CONFIG_PARTICIPANT | DELAYED_APP,
        .clkdm_name     = "iva1_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
@@ -1164,7 +1167,7 @@ static struct clk core_l3_ck = {  /* Used for ick and fck, interconnect */
        .name           = "core_l3_ck",
        .ops            = &clkops_null,
        .parent         = &core_ck,
-       .flags          = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
+       .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
        .clkdm_name     = "core_l3_clkdm",
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
@@ -1226,7 +1229,7 @@ static struct clk l4_ck = {               /* used both as an ick and fck */
        .name           = "l4_ck",
        .ops            = &clkops_null,
        .parent         = &core_l3_ck,
-       .flags          = DELAYED_APP | RATE_PROPAGATES,
+       .flags          = DELAYED_APP,
        .clkdm_name     = "core_l4_clkdm",
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
@@ -1276,6 +1279,20 @@ static struct clk ssi_ssr_sst_fck = {
        .set_rate       = &omap2_clksel_set_rate
 };
 
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+       .name           = "ssi_l4_ick",
+       .ops            = &clkops_omap2_dflt_wait,
+       .parent         = &l4_ck,
+       .clkdm_name     = "core_l4_clkdm",
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+       .recalc         = &followparent_recalc,
+};
+
 
 /*
  * GFX clock domain
@@ -1781,7 +1798,7 @@ static struct clk gpt12_ick = {
 static struct clk gpt12_fck = {
        .name           = "gpt12_fck",
        .ops            = &clkops_omap2_dflt_wait,
-       .parent         = &func_32k_ck,
+       .parent         = &secure_32k_ck,
        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,