OMAP2xxx clock: fix broken cpu_mask code

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock24xx.c

diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index f2b74e9b7d8d5dfd6581f5525201765f79ccebc5..4306392733bfb14cb8022d4519509ebfc7d28504 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -60,8 +60,8 @@ struct omap_clk {
                },                      \
        }
 
-#define CK_243X        (1 << 0)
-#define CK_242X        (1 << 1)
+#define CK_243X                        RATE_IN_243X
+#define CK_242X                        RATE_IN_242X
 
 static struct omap_clk omap24xx_clks[] = {
        /* external root sources */
@@ -236,19 +236,32 @@ static struct clk *sclk;
  * Omap24xx specific clock functions
  *-------------------------------------------------------------------------*/
 
-/* This actually returns the rate of core_ck, not dpll_ck. */
-static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
+/**
+ * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
+ * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
+ *
+ * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
+ * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
+ * (the latter is unusual).  This currently should be called with
+ * struct clk *dpll_ck, which is a composite clock of dpll_ck and
+ * core_ck.
+ */
+static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
 {
-       long long dpll_clk;
-       u8 amult;
+       long long core_clk;
+       u32 v;
 
-       dpll_clk = omap2_get_dpll_rate(tclk);
+       core_clk = omap2_get_dpll_rate(clk);
 
-       amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-       amult &= OMAP24XX_CORE_CLK_SRC_MASK;
-       dpll_clk *= amult;
+       v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+       v &= OMAP24XX_CORE_CLK_SRC_MASK;
 
-       return dpll_clk;
+       if (v == CORE_CLK_SRC_32K)
+               core_clk = 32768;
+       else
+               core_clk *= v;
+
+       return core_clk;
 }
 
 static int omap2_enable_osc_ck(struct clk *clk)
@@ -371,7 +384,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
 
 static unsigned long omap2_dpllcore_recalc(struct clk *clk)
 {
-       return omap2_get_dpll_rate_24xx(clk);
+       return omap2xxx_clk_get_core_rate(clk);
 }
 
 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
@@ -381,7 +394,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
        struct prcm_config tmpset;
        const struct dpll_data *dd;
 
-       cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+       cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
@@ -516,7 +529,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
        }
 
        curr_prcm_set = prcm;
-       cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+       cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
 
        if (prcm->dpll_speed == cur_rate / 2) {
                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
@@ -698,7 +711,7 @@ int __init omap2_clk_init(void)
 {
        struct prcm_config *prcm;
        struct omap_clk *c;
-       u32 clkrate, cpu_mask;
+       u32 clkrate;
 
        if (cpu_is_omap242x())
                cpu_mask = RATE_IN_242X;
@@ -707,6 +720,8 @@ int __init omap2_clk_init(void)
 
        clk_init(&omap2_clk_functions);
 
+       clk_init_one(&osc_ck);
+       clk_init_one(&sys_ck);
        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
        propagate_rate(&osc_ck);
        sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
@@ -715,12 +730,6 @@ int __init omap2_clk_init(void)
        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
                clk_init_one(c->lk.clk);
 
-       cpu_mask = 0;
-       if (cpu_is_omap2420())
-               cpu_mask |= CK_242X;
-       if (cpu_is_omap2430())
-               cpu_mask |= CK_243X;
-
        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
                if (c->cpu & cpu_mask) {
                        clkdev_add(&c->lk);
@@ -728,7 +737,7 @@ int __init omap2_clk_init(void)
                }
 
        /* Check the MPU rate set by bootloader */
-       clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+       clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                if (!(prcm->flags & cpu_mask))
                        continue;