[ARM] OMAP: Fix sparse, checkpatch warnings in OMAP2/3 PRCM/PM code

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock.c

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 53fda9977d55b599d88e761fbd6e29070e584de0..886f73f3933afb8e8d2630af7cbf7db841cecf97 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,7 +26,6 @@
 
 #include <mach/clock.h>
 #include <mach/clockdomain.h>
-#include <mach/sram.h>
 #include <mach/cpu.h>
 #include <asm/div64.h>
 
@@ -187,11 +186,10 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
         * 34xx reverses this, just to keep us on our toes
         */
-       if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
+       if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
                ena = mask;
-       } else if (cpu_mask & RATE_IN_343X) {
+       else if (cpu_mask & RATE_IN_343X)
                ena = 0;
-       }
 
        /* Wait for lock */
        while (((__raw_readl(reg) & mask) != ena) &&
@@ -267,7 +265,7 @@ static int omap2_dflt_clk_enable_wait(struct clk *clk)
 {
        int ret;
 
-       if (unlikely(clk->enable_reg == NULL)) {
+       if (!clk->enable_reg) {
                printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
                       clk->name);
                return 0; /* REVISIT: -EINVAL */
@@ -283,7 +281,7 @@ static void omap2_dflt_clk_disable(struct clk *clk)
 {
        u32 regval32;
 
-       if (clk->enable_reg == NULL) {
+       if (!clk->enable_reg) {
                /*
                 * 'Independent' here refers to a clock which is not
                 * controlled by its parent.
@@ -330,7 +328,7 @@ void omap2_clk_disable(struct clk *clk)
 {
        if (clk->usecount > 0 && !(--clk->usecount)) {
                _omap2_clk_disable(clk);
-               if (likely((u32)clk->parent))
+               if (clk->parent)
                        omap2_clk_disable(clk->parent);
                if (clk->clkdm)
                        omap2_clkdm_clk_disable(clk->clkdm, clk);
@@ -343,10 +341,10 @@ int omap2_clk_enable(struct clk *clk)
        int ret = 0;
 
        if (clk->usecount++ == 0) {
-               if (likely((u32)clk->parent))
+               if (clk->parent)
                        ret = omap2_clk_enable(clk->parent);
 
-               if (unlikely(ret != 0)) {
+               if (ret != 0) {
                        clk->usecount--;
                        return ret;
                }
@@ -356,7 +354,7 @@ int omap2_clk_enable(struct clk *clk)
 
                ret = _omap2_clk_enable(clk);
 
-               if (unlikely(ret != 0)) {
+               if (ret != 0) {
                        if (clk->clkdm)
                                omap2_clkdm_clk_disable(clk->clkdm, clk);
 
@@ -384,7 +382,7 @@ void omap2_clksel_recalc(struct clk *clk)
        if (div == 0)
                return;
 
-       if (unlikely(clk->rate == clk->parent->rate / div))
+       if (clk->rate == (clk->parent->rate / div))
                return;
        clk->rate = clk->parent->rate / div;
 
@@ -400,8 +398,8 @@ void omap2_clksel_recalc(struct clk *clk)
  * the element associated with the supplied parent clock address.
  * Returns a pointer to the struct clksel on success or NULL on error.
  */
-const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
-                                               struct clk *src_clk)
+static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
+                                                      struct clk *src_clk)
 {
        const struct clksel *clks;
 
@@ -450,7 +448,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        *new_div = 1;
 
        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-       if (clks == NULL)
+       if (!clks)
                return ~0;
 
        for (clkr = clks->rates; clkr->div; clkr++) {
@@ -509,7 +507,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
 /* Given a clock and a rate apply a clock specific rounding function */
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 {
-       if (clk->round_rate != NULL)
+       if (clk->round_rate)
                return clk->round_rate(clk, rate);
 
        if (clk->flags & RATE_FIXED)
@@ -535,7 +533,7 @@ u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
        const struct clksel_rate *clkr;
 
        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-       if (clks == NULL)
+       if (!clks)
                return 0;
 
        for (clkr = clks->rates; clkr->div; clkr++) {
@@ -571,7 +569,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
        WARN_ON(div == 0);
 
        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-       if (clks == NULL)
+       if (!clks)
                return 0;
 
        for (clkr = clks->rates; clkr->div; clkr++) {
@@ -596,9 +594,9 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
  *
  * Returns the address of the clksel register upon success or NULL on error.
  */
-void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
+static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
 {
-       if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
+       if (!clk->clksel_reg || (clk->clksel_mask == 0))
                return NULL;
 
        *field_mask = clk->clksel_mask;
@@ -618,7 +616,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
        void __iomem *div_addr;
 
        div_addr = omap2_get_clksel(clk, &field_mask);
-       if (div_addr == NULL)
+       if (!div_addr)
                return 0;
 
        field_val = __raw_readl(div_addr) & field_mask;
@@ -637,7 +635,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
                return -EINVAL;
 
        div_addr = omap2_get_clksel(clk, &field_mask);
-       if (div_addr == NULL)
+       if (!div_addr)
                return -EINVAL;
 
        field_val = omap2_divisor_to_clksel(clk, new_div);
@@ -675,7 +673,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
                return -EINVAL;
 
        /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
-       if (clk->set_rate != NULL)
+       if (clk->set_rate)
                ret = clk->set_rate(clk, rate);
 
        return ret;
@@ -696,7 +694,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
        *src_addr = NULL;
 
        clks = omap2_get_clksel_by_parent(clk, src_clk);
-       if (clks == NULL)
+       if (!clks)
                return 0;
 
        for (clkr = clks->rates; clkr->div; clkr++) {
@@ -726,7 +724,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
        void __iomem *src_addr;
        u32 field_val, field_mask, reg_val, parent_div;
 
-       if (unlikely(clk->flags & CONFIG_PARTICIPANT))
+       if (clk->flags & CONFIG_PARTICIPANT)
                return -EINVAL;
 
        if (!clk->clksel)
@@ -734,7 +732,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 
        field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
                                               &field_mask, clk, &parent_div);
-       if (src_addr == NULL)
+       if (!src_addr)
                return -EINVAL;
 
        if (clk->usecount > 0)
@@ -794,7 +792,8 @@ int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
        return 0;
 }
 
-static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
+static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
+                                           unsigned int m, unsigned int n)
 {
        unsigned long long num;