OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock.c

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index bd3be45917d6a0ceaa35321bd011964468e5eb9e..42af2865cbdd689048f4dbca222451e71ff419fd 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -61,6 +61,16 @@
 #define DPLL_ROUNDING_VAL              ((DPLL_SCALE_BASE / 2) * \
                                         (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
 
+/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
+#define DPLL_FINT_BAND1_MIN            750000
+#define DPLL_FINT_BAND1_MAX            2100000
+#define DPLL_FINT_BAND2_MIN            7500000
+#define DPLL_FINT_BAND2_MAX            21000000
+
+/* _dpll_test_fint() return codes */
+#define DPLL_FINT_UNDERFLOW            -1
+#define DPLL_FINT_INVALID              -2
+
 /* Some OMAP2xxx CM_CLKSEL_PLL.ST_CORE_CLK bits - for omap2_get_dpll_rate() */
 #define ST_CORE_CLK_REF                        0x1
 #define ST_CORE_CLK_32K                        0x3
@@ -114,6 +124,51 @@ static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
                cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
 }
 
+/*
+ * _dpll_test_fint - test whether an Fint value is valid for the DPLL
+ * @clk: DPLL struct clk to test
+ * @n: divider value (N) to test
+ *
+ * Tests whether a particular divider @n will result in a valid DPLL
+ * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
+ * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
+ * (assuming that it is counting N upwards), or -2 if the enclosing loop
+ * should skip to the next iteration (again assuming N is increasing).
+ */
+static int _dpll_test_fint(struct clk *clk, u8 n)
+{
+       struct dpll_data *dd;
+       long fint;
+       int ret = 0;
+
+       dd = clk->dpll_data;
+
+       /* DPLL divider must result in a valid jitter correction val */
+       fint = clk->parent->rate / (n + 1);
+       if (fint < DPLL_FINT_BAND1_MIN) {
+
+               pr_debug("rejecting n=%d due to Fint failure, "
+                        "lowering max_divider\n", n);
+               dd->max_divider = n;
+               ret = DPLL_FINT_UNDERFLOW;
+
+       } else if (fint > DPLL_FINT_BAND1_MAX &&
+                  fint < DPLL_FINT_BAND2_MIN) {
+
+               pr_debug("rejecting n=%d due to Fint failure\n", n);
+               ret = DPLL_FINT_INVALID;
+
+       } else if (fint > DPLL_FINT_BAND2_MAX) {
+
+               pr_debug("rejecting n=%d due to Fint failure, "
+                        "boosting min_divider\n", n);
+               dd->min_divider = n;
+               ret = DPLL_FINT_INVALID;
+
+       }
+
+       return ret;
+}
 
 /**
  * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
@@ -943,7 +998,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
 
        dd->last_rounded_rate = 0;
 
-       for (n = DPLL_MIN_DIVIDER; n <= dd->max_divider; n++) {
+       for (n = dd->min_divider; n <= dd->max_divider; n++) {
+
+               /* Is the (input clk, divider) pair valid for the DPLL? */
+               r = _dpll_test_fint(clk, n);
+               if (r == DPLL_FINT_UNDERFLOW)
+                       break;
+               else if (r == DPLL_FINT_INVALID)
+                       continue;
 
                /* Compute the scaled DPLL multiplier, based on the divider */
                m = scaled_rt_rp * n;
@@ -977,7 +1039,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                        pr_debug("clock: found new least error %d\n", min_e);
 
                        /* We found good settings -- bail out now */
-                       if (min_e <= clk->dpll_data->rate_tolerance)
+                       if (min_e <= dd->rate_tolerance)
                                break;
                }
        }