From 0e5194e1a84c219bebbb78f305b7a8eabc4a3656 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 18 Jul 2008 02:22:54 -0600 Subject: [PATCH] OMAP2/3 clock: combine clkdm, clkdm_name into union in struct clk struct clk contains a struct clockdomain *clkdm and const char *clkdm_name. The clkdm_name is only used at initialization to look up the appropriate clkdm pointer. Combining these into a union saves about 850 bytes on 3430SDP. This patch should not cause any change in kernel function. Boot-tested on 3430SDP ES2; compile-tested with n800_defconfig. Signed-off-by: Paul Walmsley size: text data bss dec hex filename 3391555 157032 107136 3655723 37c82b vmlinux.3430sdp.orig 3391555 156176 107136 3654867 37c4d3 vmlinux.3430sdp Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock.c | 22 +-- arch/arm/mach-omap2/clock24xx.h | 264 +++++++++++++++--------------- arch/arm/mach-omap2/clock34xx.h | 256 ++++++++++++++--------------- include/asm-arm/arch-omap/clock.h | 6 +- 4 files changed, 275 insertions(+), 273 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index df85f696e0e..3e15681cd29 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -78,17 +78,17 @@ void omap2_init_clk_clkdm(struct clk *clk) { struct clockdomain *clkdm; - if (!clk->clkdm_name) + if (!clk->clkdm.name) return; - clkdm = clkdm_lookup(clk->clkdm_name); + clkdm = clkdm_lookup(clk->clkdm.name); if (clkdm) { pr_debug("clock: associated clk %s to clkdm %s\n", - clk->name, clk->clkdm_name); - clk->clkdm = clkdm; + clk->name, clk->clkdm.name); + clk->clkdm.ptr = clkdm; } else { pr_debug("clock: could not associate clk %s to " - "clkdm %s\n", clk->name, clk->clkdm_name); + "clkdm %s\n", clk->name, clk->clkdm.name); } } @@ -381,8 +381,8 @@ void omap2_clk_disable(struct clk *clk) _omap2_clk_disable(clk); if (clk->parent) omap2_clk_disable(clk->parent); - if (clk->clkdm) - omap2_clkdm_clk_disable(clk->clkdm, clk); + if (clk->clkdm.ptr) + omap2_clkdm_clk_disable(clk->clkdm.ptr, clk); } } @@ -400,14 +400,14 @@ int omap2_clk_enable(struct clk *clk) return ret; } - if (clk->clkdm) - omap2_clkdm_clk_enable(clk->clkdm, clk); + if (clk->clkdm.ptr) + omap2_clkdm_clk_enable(clk->clkdm.ptr, clk); ret = _omap2_clk_enable(clk); if (ret != 0) { - if (clk->clkdm) - omap2_clkdm_clk_disable(clk->clkdm, clk); + if (clk->clkdm.ptr) + omap2_clkdm_clk_disable(clk->clkdm.ptr, clk); if (clk->parent) { omap2_clk_disable(clk->parent); diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 41d8d263680..4de6d9b6886 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -635,7 +635,7 @@ static struct clk func_32k_ck = { .rate = 32000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &propagate_rate, }; @@ -644,7 +644,7 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ .name = "osc_ck", .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .enable = &omap2_enable_osc_ck, .disable = &omap2_disable_osc_ck, .recalc = &omap2_osc_clk_recalc, @@ -656,7 +656,7 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ .parent = &osc_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED | RATE_PROPAGATES, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &omap2_sys_clk_recalc, }; @@ -665,7 +665,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .rate = 54000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &propagate_rate, }; @@ -697,7 +697,7 @@ static struct clk dpll_ck = { .dpll_data = &dpll_dd, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | ALWAYS_ENABLED, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &omap2_dpllcore_recalc, .set_rate = &omap2_reprogram_dpllcore, }; @@ -708,7 +708,7 @@ static struct clk apll96_ck = { .rate = 96000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, .enable = &omap2_clk_fixed_enable, @@ -722,7 +722,7 @@ static struct clk apll54_ck = { .rate = 54000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, .enable = &omap2_clk_fixed_enable, @@ -757,7 +757,7 @@ static struct clk func_54m_ck = { .parent = &apll54_ck, /* can also be alt_clk */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .init = &omap2_init_clksel_parent, .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_54M_SOURCE, @@ -770,7 +770,7 @@ static struct clk core_ck = { .parent = &dpll_ck, /* can also be 32k */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED | RATE_PROPAGATES, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -797,7 +797,7 @@ static struct clk func_96m_ck = { .parent = &apll96_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .init = &omap2_init_clksel_parent, .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP2430_96M_SOURCE, @@ -830,7 +830,7 @@ static struct clk func_48m_ck = { .parent = &apll96_ck, /* 96M or Alt */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .init = &omap2_init_clksel_parent, .clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_48M_SOURCE, @@ -846,7 +846,7 @@ static struct clk func_12m_ck = { .fixed_div = 4, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &omap2_fixed_divisor_recalc, }; @@ -899,7 +899,7 @@ static struct clk sys_clkout_src = { .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES | OFFSET_GR_MOD, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, .init = &omap2_init_clksel_parent, @@ -930,7 +930,7 @@ static struct clk sys_clkout = { .parent = &sys_clkout_src, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, .clksel = sys_clkout_clksel, @@ -944,7 +944,7 @@ static struct clk sys_clkout2_src = { .name = "sys_clkout2_src", .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, .init = &omap2_init_clksel_parent, @@ -967,7 +967,7 @@ static struct clk sys_clkout2 = { .parent = &sys_clkout2_src, .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET), .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, @@ -980,7 +980,7 @@ static struct clk emul_ck = { .name = "emul_ck", .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | OFFSET_GR_MOD, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET), .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, .recalc = &followparent_recalc, @@ -1017,7 +1017,7 @@ static struct clk mpu_ck = { /* Control cpu */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, - .clkdm_name = "mpu_clkdm", + .clkdm = { .name = "mpu_clkdm" }, .init = &omap2_init_clksel_parent, .clksel_reg = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, @@ -1059,7 +1059,7 @@ static struct clk dsp_fck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, - .clkdm_name = "dsp_clkdm", + .clkdm = { .name = "dsp_clkdm" }, .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, .clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL), @@ -1125,7 +1125,7 @@ static struct clk iva1_ifck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, - .clkdm_name = "iva1_clkdm", + .clkdm = { .name = "iva1_clkdm" }, .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, .clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL), @@ -1141,7 +1141,7 @@ static struct clk iva1_mpu_int_ifck = { .name = "iva1_mpu_int_ifck", .parent = &iva1_ifck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "iva1_clkdm", + .clkdm = { .name = "iva1_clkdm" }, .enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .fixed_div = 2, @@ -1189,7 +1189,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, .clksel = core_l3_clksel, @@ -1217,7 +1217,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_USB_SHIFT, .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), @@ -1251,7 +1251,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */ .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, .clksel = l4_clksel, @@ -1289,7 +1289,7 @@ static struct clk ssi_ssr_sst_fck = { .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_SSI_SHIFT, .clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1), @@ -1307,7 +1307,7 @@ static struct clk ssi_ssr_sst_fck = { static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_SSI_SHIFT, @@ -1338,7 +1338,7 @@ static struct clk gfx_3d_fck = { .name = "gfx_3d_fck", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "gfx_clkdm", + .clkdm = { .name = "gfx_clkdm" }, .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_3D_SHIFT, .clksel_reg = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL), @@ -1353,7 +1353,7 @@ static struct clk gfx_2d_fck = { .name = "gfx_2d_fck", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "gfx_clkdm", + .clkdm = { .name = "gfx_clkdm" }, .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_2D_SHIFT, .clksel_reg = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL), @@ -1368,7 +1368,7 @@ static struct clk gfx_ick = { .name = "gfx_ick", /* From l3 */ .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "gfx_clkdm", + .clkdm = { .name = "gfx_clkdm" }, .enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, .recalc = &followparent_recalc, @@ -1398,7 +1398,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ .name = "mdm_ick", .parent = &core_ck, .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, - .clkdm_name = "mdm_clkdm", + .clkdm = { .name = "mdm_clkdm" }, .enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN), .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, .clksel_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL), @@ -1413,7 +1413,7 @@ static struct clk mdm_osc_ck = { .name = "mdm_osc_ck", .parent = &osc_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "mdm_clkdm", + .clkdm = { .name = "mdm_clkdm" }, .enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN), .enable_bit = OMAP2430_EN_OSC_SHIFT, .recalc = &followparent_recalc, @@ -1458,7 +1458,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ .name = "dss_ick", .parent = &l4_ck, /* really both l3 and l4 */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_DSS1_SHIFT, .recalc = &followparent_recalc, @@ -1469,7 +1469,7 @@ static struct clk dss1_fck = { .parent = &core_ck, /* Core or sys */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_DSS1_SHIFT, .init = &omap2_init_clksel_parent, @@ -1502,7 +1502,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_DSS2_SHIFT, .init = &omap2_init_clksel_parent, @@ -1516,7 +1516,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ .name = "dss_54m_fck", /* 54m tv clk */ .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_TV_SHIFT, .recalc = &followparent_recalc, @@ -1544,7 +1544,7 @@ static struct clk gpt1_ick = { .name = "gpt1_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, .recalc = &followparent_recalc, @@ -1554,7 +1554,7 @@ static struct clk gpt1_fck = { .name = "gpt1_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, .init = &omap2_init_clksel_parent, @@ -1570,7 +1570,7 @@ static struct clk gpt2_ick = { .name = "gpt2_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT2_SHIFT, .recalc = &followparent_recalc, @@ -1580,7 +1580,7 @@ static struct clk gpt2_fck = { .name = "gpt2_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT2_SHIFT, .init = &omap2_init_clksel_parent, @@ -1594,7 +1594,7 @@ static struct clk gpt3_ick = { .name = "gpt3_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT3_SHIFT, .recalc = &followparent_recalc, @@ -1604,7 +1604,7 @@ static struct clk gpt3_fck = { .name = "gpt3_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT3_SHIFT, .init = &omap2_init_clksel_parent, @@ -1618,7 +1618,7 @@ static struct clk gpt4_ick = { .name = "gpt4_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT4_SHIFT, .recalc = &followparent_recalc, @@ -1628,7 +1628,7 @@ static struct clk gpt4_fck = { .name = "gpt4_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT4_SHIFT, .init = &omap2_init_clksel_parent, @@ -1642,7 +1642,7 @@ static struct clk gpt5_ick = { .name = "gpt5_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT5_SHIFT, .recalc = &followparent_recalc, @@ -1652,7 +1652,7 @@ static struct clk gpt5_fck = { .name = "gpt5_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT5_SHIFT, .init = &omap2_init_clksel_parent, @@ -1666,7 +1666,7 @@ static struct clk gpt6_ick = { .name = "gpt6_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT6_SHIFT, .recalc = &followparent_recalc, @@ -1676,7 +1676,7 @@ static struct clk gpt6_fck = { .name = "gpt6_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT6_SHIFT, .init = &omap2_init_clksel_parent, @@ -1699,7 +1699,7 @@ static struct clk gpt7_fck = { .name = "gpt7_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, .init = &omap2_init_clksel_parent, @@ -1713,7 +1713,7 @@ static struct clk gpt8_ick = { .name = "gpt8_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT8_SHIFT, .recalc = &followparent_recalc, @@ -1723,7 +1723,7 @@ static struct clk gpt8_fck = { .name = "gpt8_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT8_SHIFT, .init = &omap2_init_clksel_parent, @@ -1737,7 +1737,7 @@ static struct clk gpt9_ick = { .name = "gpt9_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT9_SHIFT, .recalc = &followparent_recalc, @@ -1747,7 +1747,7 @@ static struct clk gpt9_fck = { .name = "gpt9_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT9_SHIFT, .init = &omap2_init_clksel_parent, @@ -1761,7 +1761,7 @@ static struct clk gpt10_ick = { .name = "gpt10_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT10_SHIFT, .recalc = &followparent_recalc, @@ -1771,7 +1771,7 @@ static struct clk gpt10_fck = { .name = "gpt10_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT10_SHIFT, .init = &omap2_init_clksel_parent, @@ -1785,7 +1785,7 @@ static struct clk gpt11_ick = { .name = "gpt11_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT11_SHIFT, .recalc = &followparent_recalc, @@ -1795,7 +1795,7 @@ static struct clk gpt11_fck = { .name = "gpt11_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT11_SHIFT, .init = &omap2_init_clksel_parent, @@ -1809,7 +1809,7 @@ static struct clk gpt12_ick = { .name = "gpt12_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, .recalc = &followparent_recalc, @@ -1819,7 +1819,7 @@ static struct clk gpt12_fck = { .name = "gpt12_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_GPT12_SHIFT, .init = &omap2_init_clksel_parent, @@ -1834,7 +1834,7 @@ static struct clk mcbsp1_ick = { .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, .recalc = &followparent_recalc, @@ -1845,7 +1845,7 @@ static struct clk mcbsp1_fck = { .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, .recalc = &followparent_recalc, @@ -1856,7 +1856,7 @@ static struct clk mcbsp2_ick = { .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, .recalc = &followparent_recalc, @@ -1867,7 +1867,7 @@ static struct clk mcbsp2_fck = { .id = 2, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, .recalc = &followparent_recalc, @@ -1878,7 +1878,7 @@ static struct clk mcbsp3_ick = { .id = 3, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, .recalc = &followparent_recalc, @@ -1889,7 +1889,7 @@ static struct clk mcbsp3_fck = { .id = 3, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, .recalc = &followparent_recalc, @@ -1900,7 +1900,7 @@ static struct clk mcbsp4_ick = { .id = 4, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, .recalc = &followparent_recalc, @@ -1911,7 +1911,7 @@ static struct clk mcbsp4_fck = { .id = 4, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, .recalc = &followparent_recalc, @@ -1922,7 +1922,7 @@ static struct clk mcbsp5_ick = { .id = 5, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, .recalc = &followparent_recalc, @@ -1933,7 +1933,7 @@ static struct clk mcbsp5_fck = { .id = 5, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, .recalc = &followparent_recalc, @@ -1943,7 +1943,7 @@ static struct clk mcspi1_ick = { .name = "mcspi_ick", .id = 1, .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, @@ -1955,7 +1955,7 @@ static struct clk mcspi1_fck = { .id = 1, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, .recalc = &followparent_recalc, @@ -1966,7 +1966,7 @@ static struct clk mcspi2_ick = { .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, .recalc = &followparent_recalc, @@ -1977,7 +1977,7 @@ static struct clk mcspi2_fck = { .id = 2, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, .recalc = &followparent_recalc, @@ -1988,7 +1988,7 @@ static struct clk mcspi3_ick = { .id = 3, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, .recalc = &followparent_recalc, @@ -1999,7 +1999,7 @@ static struct clk mcspi3_fck = { .id = 3, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, .recalc = &followparent_recalc, @@ -2009,7 +2009,7 @@ static struct clk uart1_ick = { .name = "uart1_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_UART1_SHIFT, .recalc = &followparent_recalc, @@ -2019,7 +2019,7 @@ static struct clk uart1_fck = { .name = "uart1_fck", .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_UART1_SHIFT, .recalc = &followparent_recalc, @@ -2029,7 +2029,7 @@ static struct clk uart2_ick = { .name = "uart2_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_UART2_SHIFT, .recalc = &followparent_recalc, @@ -2039,7 +2039,7 @@ static struct clk uart2_fck = { .name = "uart2_fck", .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_UART2_SHIFT, .recalc = &followparent_recalc, @@ -2049,7 +2049,7 @@ static struct clk uart3_ick = { .name = "uart3_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP24XX_EN_UART3_SHIFT, .recalc = &followparent_recalc, @@ -2059,7 +2059,7 @@ static struct clk uart3_fck = { .name = "uart3_fck", .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_UART3_SHIFT, .recalc = &followparent_recalc, @@ -2069,7 +2069,7 @@ static struct clk gpios_ick = { .name = "gpios_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .recalc = &followparent_recalc, @@ -2079,7 +2079,7 @@ static struct clk gpios_fck = { .name = "gpios_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .recalc = &followparent_recalc, @@ -2089,7 +2089,7 @@ static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .recalc = &followparent_recalc, @@ -2099,7 +2099,7 @@ static struct clk mpu_wdt_fck = { .name = "mpu_wdt_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .recalc = &followparent_recalc, @@ -2110,7 +2110,7 @@ static struct clk sync_32k_ick = { .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, .recalc = &followparent_recalc, @@ -2120,7 +2120,7 @@ static struct clk wdt1_ick = { .name = "wdt1_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_WDT1_SHIFT, .recalc = &followparent_recalc, @@ -2131,7 +2131,7 @@ static struct clk omapctrl_ick = { .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, .recalc = &followparent_recalc, @@ -2141,7 +2141,7 @@ static struct clk icr_ick = { .name = "icr_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP2430_EN_ICR_SHIFT, .recalc = &followparent_recalc, @@ -2151,7 +2151,7 @@ static struct clk cam_ick = { .name = "cam_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_CAM_SHIFT, .recalc = &followparent_recalc, @@ -2166,7 +2166,7 @@ static struct clk cam_fck = { .name = "cam_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_CAM_SHIFT, .recalc = &followparent_recalc, @@ -2176,7 +2176,7 @@ static struct clk mailboxes_ick = { .name = "mailboxes_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, .recalc = &followparent_recalc, @@ -2186,7 +2186,7 @@ static struct clk wdt4_ick = { .name = "wdt4_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_WDT4_SHIFT, .recalc = &followparent_recalc, @@ -2196,7 +2196,7 @@ static struct clk wdt4_fck = { .name = "wdt4_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_WDT4_SHIFT, .recalc = &followparent_recalc, @@ -2206,7 +2206,7 @@ static struct clk wdt3_ick = { .name = "wdt3_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_WDT3_SHIFT, .recalc = &followparent_recalc, @@ -2216,7 +2216,7 @@ static struct clk wdt3_fck = { .name = "wdt3_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_WDT3_SHIFT, .recalc = &followparent_recalc, @@ -2226,7 +2226,7 @@ static struct clk mspro_ick = { .name = "mspro_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, .recalc = &followparent_recalc, @@ -2236,7 +2236,7 @@ static struct clk mspro_fck = { .name = "mspro_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, .recalc = &followparent_recalc, @@ -2246,7 +2246,7 @@ static struct clk mmc_ick = { .name = "mmc_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_MMC_SHIFT, .recalc = &followparent_recalc, @@ -2256,7 +2256,7 @@ static struct clk mmc_fck = { .name = "mmc_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_MMC_SHIFT, .recalc = &followparent_recalc, @@ -2266,7 +2266,7 @@ static struct clk fac_ick = { .name = "fac_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_FAC_SHIFT, .recalc = &followparent_recalc, @@ -2276,7 +2276,7 @@ static struct clk fac_fck = { .name = "fac_fck", .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_FAC_SHIFT, .recalc = &followparent_recalc, @@ -2286,7 +2286,7 @@ static struct clk eac_ick = { .name = "eac_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_EAC_SHIFT, .recalc = &followparent_recalc, @@ -2296,7 +2296,7 @@ static struct clk eac_fck = { .name = "eac_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_EAC_SHIFT, .recalc = &followparent_recalc, @@ -2306,7 +2306,7 @@ static struct clk hdq_ick = { .name = "hdq_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_HDQ_SHIFT, .recalc = &followparent_recalc, @@ -2316,7 +2316,7 @@ static struct clk hdq_fck = { .name = "hdq_fck", .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_HDQ_SHIFT, .recalc = &followparent_recalc, @@ -2327,7 +2327,7 @@ static struct clk i2c2_ick = { .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_I2C2_SHIFT, .recalc = &followparent_recalc, @@ -2338,7 +2338,7 @@ static struct clk i2c2_fck = { .id = 2, .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_I2C2_SHIFT, .recalc = &followparent_recalc, @@ -2349,7 +2349,7 @@ static struct clk i2chs2_fck = { .id = 2, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, .recalc = &followparent_recalc, @@ -2360,7 +2360,7 @@ static struct clk i2c1_ick = { .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_I2C1_SHIFT, .recalc = &followparent_recalc, @@ -2371,7 +2371,7 @@ static struct clk i2c1_fck = { .id = 1, .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_I2C1_SHIFT, .recalc = &followparent_recalc, @@ -2382,7 +2382,7 @@ static struct clk i2chs1_fck = { .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, .recalc = &followparent_recalc, @@ -2393,7 +2393,7 @@ static struct clk gpmc_fck = { .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; @@ -2401,7 +2401,7 @@ static struct clk sdma_fck = { .name = "sdma_fck", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; @@ -2409,7 +2409,7 @@ static struct clk sdma_ick = { .name = "sdma_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; @@ -2417,7 +2417,7 @@ static struct clk vlynq_ick = { .name = "vlynq_ick", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, .recalc = &followparent_recalc, @@ -2452,7 +2452,7 @@ static struct clk vlynq_fck = { .name = "vlynq_fck", .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | DELAYED_APP, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, .init = &omap2_init_clksel_parent, @@ -2468,7 +2468,7 @@ static struct clk sdrc_ick = { .name = "sdrc_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP2430_EN_SDRC_SHIFT, .recalc = &followparent_recalc, @@ -2478,7 +2478,7 @@ static struct clk des_ick = { .name = "des_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_DES_SHIFT, .recalc = &followparent_recalc, @@ -2488,7 +2488,7 @@ static struct clk sha_ick = { .name = "sha_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_SHA_SHIFT, .recalc = &followparent_recalc, @@ -2498,7 +2498,7 @@ static struct clk rng_ick = { .name = "rng_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_RNG_SHIFT, .recalc = &followparent_recalc, @@ -2508,7 +2508,7 @@ static struct clk aes_ick = { .name = "aes_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_AES_SHIFT, .recalc = &followparent_recalc, @@ -2518,7 +2518,7 @@ static struct clk pka_ick = { .name = "pka_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4), .enable_bit = OMAP24XX_EN_PKA_SHIFT, .recalc = &followparent_recalc, @@ -2528,7 +2528,7 @@ static struct clk usb_fck = { .name = "usb_fck", .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP24XX_EN_USB_SHIFT, .recalc = &followparent_recalc, @@ -2538,7 +2538,7 @@ static struct clk usbhs_ick = { .name = "usbhs_ick", .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_USBHS_SHIFT, .recalc = &followparent_recalc, @@ -2549,7 +2549,7 @@ static struct clk mmchs1_ick = { .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, .recalc = &followparent_recalc, @@ -2560,7 +2560,7 @@ static struct clk mmchs1_fck = { .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, .recalc = &followparent_recalc, @@ -2571,7 +2571,7 @@ static struct clk mmchs2_ick = { .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, .recalc = &followparent_recalc, @@ -2591,7 +2591,7 @@ static struct clk gpio5_ick = { .name = "gpio5_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_GPIO5_SHIFT, .recalc = &followparent_recalc, @@ -2601,7 +2601,7 @@ static struct clk gpio5_fck = { .name = "gpio5_fck", .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_GPIO5_SHIFT, .recalc = &followparent_recalc, @@ -2611,7 +2611,7 @@ static struct clk mdm_intc_ick = { .name = "mdm_intc_ick", .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, .recalc = &followparent_recalc, @@ -2622,7 +2622,7 @@ static struct clk mmchsdb1_fck = { .id = 1, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, .recalc = &followparent_recalc, @@ -2633,7 +2633,7 @@ static struct clk mmchsdb2_fck = { .id = 2, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, .recalc = &followparent_recalc, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 0eebbdffab0..d7d6ffd185d 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -1010,7 +1010,7 @@ static struct clk clkout2_src_ck = { .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, .clksel = clkout2_src_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .clkdm_name = "core_clkdm", + .clkdm = { .name = "core_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1099,7 +1099,7 @@ static struct clk mpu_ck = { .clksel = mpu_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "mpu_clkdm", + .clkdm = { .name = "mpu_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1177,7 +1177,7 @@ static struct clk iva2_ck = { .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, .clksel = iva2_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .clkdm_name = "iva2_clkdm", + .clkdm = { .name = "iva2_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1197,7 +1197,7 @@ static struct clk l3_ick = { .clksel = div2_core_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1215,7 +1215,7 @@ static struct clk l4_ick = { .clksel = div2_l3_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1265,7 +1265,7 @@ static struct clk gfx_l3_fck = { .clksel = gfx_l3_clksel, .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "gfx_3430es1_clkdm", + .clkdm = { .name = "gfx_3430es1_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1273,7 +1273,7 @@ static struct clk gfx_l3_ick = { .name = "gfx_l3_ick", .parent = &gfx_l3_ck, .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, - .clkdm_name = "gfx_3430es1_clkdm", + .clkdm = { .name = "gfx_3430es1_clkdm" }, .recalc = &followparent_recalc, }; @@ -1284,7 +1284,7 @@ static struct clk gfx_cg1_ck = { .enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_2D_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, - .clkdm_name = "gfx_3430es1_clkdm", + .clkdm = { .name = "gfx_3430es1_clkdm" }, .recalc = &followparent_recalc, }; @@ -1295,7 +1295,7 @@ static struct clk gfx_cg2_ck = { .enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_3D_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, - .clkdm_name = "gfx_3430es1_clkdm", + .clkdm = { .name = "gfx_3430es1_clkdm" }, .recalc = &followparent_recalc, }; @@ -1328,7 +1328,7 @@ static struct clk sgx_fck = { .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, .clksel = sgx_clksel, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "sgx_clkdm", + .clkdm = { .name = "sgx_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1339,7 +1339,7 @@ static struct clk sgx_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "sgx_clkdm", + .clkdm = { .name = "sgx_clkdm" }, .recalc = &followparent_recalc, }; @@ -1352,7 +1352,7 @@ static struct clk d2d_26m_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, - .clkdm_name = "d2d_clkdm", + .clkdm = { .name = "d2d_clkdm" }, .recalc = &followparent_recalc, }; @@ -1372,7 +1372,7 @@ static struct clk gpt10_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1386,7 +1386,7 @@ static struct clk gpt11_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1424,7 +1424,7 @@ static struct clk core_96m_fck = { .parent = &omap_96m_fck, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1435,7 +1435,7 @@ static struct clk mmchs3_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1446,7 +1446,7 @@ static struct clk mmchs2_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1456,7 +1456,7 @@ static struct clk mspro_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1467,7 +1467,7 @@ static struct clk mmchs1_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1478,7 +1478,7 @@ static struct clk i2c3_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1489,7 +1489,7 @@ static struct clk i2c2_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1500,7 +1500,7 @@ static struct clk i2c1_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1534,7 +1534,7 @@ static struct clk mcbsp5_fck = { .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, .clksel = mcbsp_15_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1548,7 +1548,7 @@ static struct clk mcbsp1_fck = { .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, .clksel = mcbsp_15_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1559,7 +1559,7 @@ static struct clk core_48m_fck = { .parent = &omap_48m_fck, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1637,7 +1637,7 @@ static struct clk core_12m_fck = { .parent = &omap_12m_fck, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1676,7 +1676,7 @@ static struct clk ssi_ssr_fck = { .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, .clksel = ssi_ssr_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -1702,7 +1702,7 @@ static struct clk core_l3_ick = { .init = &omap2_init_clk_clkdm, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; @@ -1712,7 +1712,7 @@ static struct clk hsotgusb_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; @@ -1722,7 +1722,7 @@ static struct clk sdrc_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SDRC_SHIFT, .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; @@ -1731,7 +1731,7 @@ static struct clk gpmc_fck = { .parent = &core_l3_ick, .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", + .clkdm = { .name = "core_l3_clkdm" }, .recalc = &followparent_recalc, }; @@ -1762,7 +1762,7 @@ static struct clk core_l4_ick = { .init = &omap2_init_clk_clkdm, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1772,7 +1772,7 @@ static struct clk usbtll_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1783,7 +1783,7 @@ static struct clk mmchs3_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1794,7 +1794,7 @@ static struct clk icr_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_ICR_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1804,7 +1804,7 @@ static struct clk aes2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_AES2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1814,7 +1814,7 @@ static struct clk sha12_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SHA12_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1824,7 +1824,7 @@ static struct clk des2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_DES2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1835,7 +1835,7 @@ static struct clk mmchs2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1846,7 +1846,7 @@ static struct clk mmchs1_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1856,7 +1856,7 @@ static struct clk mspro_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1866,7 +1866,7 @@ static struct clk hdq_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1877,7 +1877,7 @@ static struct clk mcspi4_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1888,7 +1888,7 @@ static struct clk mcspi3_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1899,7 +1899,7 @@ static struct clk mcspi2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1910,7 +1910,7 @@ static struct clk mcspi1_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1921,7 +1921,7 @@ static struct clk i2c3_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1932,7 +1932,7 @@ static struct clk i2c2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1943,7 +1943,7 @@ static struct clk i2c1_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1953,7 +1953,7 @@ static struct clk uart2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1963,7 +1963,7 @@ static struct clk uart1_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1973,7 +1973,7 @@ static struct clk gpt11_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1983,7 +1983,7 @@ static struct clk gpt10_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -1994,7 +1994,7 @@ static struct clk mcbsp5_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -2005,7 +2005,7 @@ static struct clk mcbsp1_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -2015,7 +2015,7 @@ static struct clk fac_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, .flags = CLOCK_IN_OMAP3430ES1, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -2025,7 +2025,7 @@ static struct clk mailboxes_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -2045,7 +2045,7 @@ static struct clk ssi_l4_ick = { .parent = &l4_ick, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -2055,7 +2055,7 @@ static struct clk ssi_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; @@ -2145,7 +2145,7 @@ static struct clk dss1_alwon_fck = { .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = dss1_alwon_fck_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2156,7 +2156,7 @@ static struct clk dss_tv_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .recalc = &followparent_recalc, }; @@ -2167,7 +2167,7 @@ static struct clk dss_96m_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .recalc = &followparent_recalc, }; @@ -2178,7 +2178,7 @@ static struct clk dss2_alwon_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .recalc = &followparent_recalc, }; @@ -2190,7 +2190,7 @@ static struct clk dss_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "dss_clkdm", + .clkdm = { .name = "dss_clkdm" }, .recalc = &followparent_recalc, }; @@ -2212,7 +2212,7 @@ static struct clk cam_mclk = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "cam_clkdm", + .clkdm = { .name = "cam_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2224,7 +2224,7 @@ static struct clk cam_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "cam_clkdm", + .clkdm = { .name = "cam_clkdm" }, .recalc = &followparent_recalc, }; @@ -2237,7 +2237,7 @@ static struct clk usbhost_120m_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "usbhost_clkdm", + .clkdm = { .name = "usbhost_clkdm" }, .recalc = &followparent_recalc, }; @@ -2248,7 +2248,7 @@ static struct clk usbhost_48m_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "usbhost_clkdm", + .clkdm = { .name = "usbhost_clkdm" }, .recalc = &followparent_recalc, }; @@ -2260,7 +2260,7 @@ static struct clk usbhost_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "usbhost_clkdm", + .clkdm = { .name = "usbhost_clkdm" }, .recalc = &followparent_recalc, }; @@ -2312,7 +2312,7 @@ static struct clk gpt1_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2321,7 +2321,7 @@ static struct clk wkup_32k_fck = { .init = &omap2_init_clk_clkdm, .parent = &omap_32k_fck, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2331,7 +2331,7 @@ static struct clk gpio1_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2341,7 +2341,7 @@ static struct clk wdt2_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2349,7 +2349,7 @@ static struct clk wkup_l4_ick = { .name = "wkup_l4_ick", .parent = &sys_ck, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2361,7 +2361,7 @@ static struct clk usim_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2371,7 +2371,7 @@ static struct clk wdt2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2381,7 +2381,7 @@ static struct clk wdt1_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2391,7 +2391,7 @@ static struct clk gpio1_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2401,7 +2401,7 @@ static struct clk omap_32ksync_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2412,7 +2412,7 @@ static struct clk gpt12_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT12_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2422,7 +2422,7 @@ static struct clk gpt1_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "wkup_clkdm", + .clkdm = { .name = "wkup_clkdm" }, .recalc = &followparent_recalc, }; @@ -2436,7 +2436,7 @@ static struct clk per_96m_fck = { .init = &omap2_init_clk_clkdm, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2446,7 +2446,7 @@ static struct clk per_48m_fck = { .init = &omap2_init_clk_clkdm, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2456,7 +2456,7 @@ static struct clk uart3_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2469,7 +2469,7 @@ static struct clk gpt2_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2482,7 +2482,7 @@ static struct clk gpt3_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2495,7 +2495,7 @@ static struct clk gpt4_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2508,7 +2508,7 @@ static struct clk gpt5_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2521,7 +2521,7 @@ static struct clk gpt6_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2534,7 +2534,7 @@ static struct clk gpt7_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2547,7 +2547,7 @@ static struct clk gpt8_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2560,14 +2560,14 @@ static struct clk gpt9_fck = { .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, .clksel = omap343x_gpt_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; static struct clk per_32k_alwon_fck = { .name = "per_32k_alwon_fck", .parent = &omap_32k_fck, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, .recalc = &followparent_recalc, }; @@ -2578,7 +2578,7 @@ static struct clk gpio6_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2588,7 +2588,7 @@ static struct clk gpio5_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2598,7 +2598,7 @@ static struct clk gpio4_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2608,7 +2608,7 @@ static struct clk gpio3_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2618,7 +2618,7 @@ static struct clk gpio2_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2628,7 +2628,7 @@ static struct clk wdt3_fck = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2637,7 +2637,7 @@ static struct clk per_l4_ick = { .parent = &l4_ick, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2647,7 +2647,7 @@ static struct clk gpio6_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2657,7 +2657,7 @@ static struct clk gpio5_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2667,7 +2667,7 @@ static struct clk gpio4_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2677,7 +2677,7 @@ static struct clk gpio3_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2687,7 +2687,7 @@ static struct clk gpio2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2697,7 +2697,7 @@ static struct clk wdt3_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2707,7 +2707,7 @@ static struct clk uart3_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2717,7 +2717,7 @@ static struct clk gpt9_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2727,7 +2727,7 @@ static struct clk gpt8_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2737,7 +2737,7 @@ static struct clk gpt7_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2747,7 +2747,7 @@ static struct clk gpt6_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2757,7 +2757,7 @@ static struct clk gpt5_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2767,7 +2767,7 @@ static struct clk gpt4_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2777,7 +2777,7 @@ static struct clk gpt3_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2787,7 +2787,7 @@ static struct clk gpt2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2798,7 +2798,7 @@ static struct clk mcbsp2_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2809,7 +2809,7 @@ static struct clk mcbsp3_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2820,7 +2820,7 @@ static struct clk mcbsp4_ick = { .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &followparent_recalc, }; @@ -2840,7 +2840,7 @@ static struct clk mcbsp2_fck = { .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, .clksel = mcbsp_234_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2854,7 +2854,7 @@ static struct clk mcbsp3_fck = { .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, .clksel = mcbsp_234_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2868,7 +2868,7 @@ static struct clk mcbsp4_fck = { .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, .clksel = mcbsp_234_clksel, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "per_clkdm", + .clkdm = { .name = "per_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2916,7 +2916,7 @@ static struct clk emu_src_ck = { .clksel_mask = OMAP3430_MUX_CTRL_MASK, .clksel = emu_src_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, - .clkdm_name = "emu_clkdm", + .clkdm = { .name = "emu_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2940,7 +2940,7 @@ static struct clk pclk_fck = { .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel = pclk_emu_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, - .clkdm_name = "emu_clkdm", + .clkdm = { .name = "emu_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2963,7 +2963,7 @@ static struct clk pclkx2_fck = { .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel = pclkx2_emu_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, - .clkdm_name = "emu_clkdm", + .clkdm = { .name = "emu_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2979,7 +2979,7 @@ static struct clk atclk_fck = { .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel = atclk_emu_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, - .clkdm_name = "emu_clkdm", + .clkdm = { .name = "emu_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -2990,7 +2990,7 @@ static struct clk traceclk_src_fck = { .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel = emu_src_clksel, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, - .clkdm_name = "emu_clkdm", + .clkdm = { .name = "emu_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -3013,7 +3013,7 @@ static struct clk traceclk_fck = { .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, .clksel = traceclk_clksel, .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, - .clkdm_name = "emu_clkdm", + .clkdm = { .name = "emu_clkdm" }, .recalc = &omap2_clksel_recalc, }; @@ -3043,7 +3043,7 @@ static struct clk sr_l4_ick = { .name = "sr_l4_ick", .parent = &l4_ick, .flags = CLOCK_IN_OMAP343X, - .clkdm_name = "core_l4_clkdm", + .clkdm = { .name = "core_l4_clkdm" }, .recalc = &followparent_recalc, }; diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index bfaf7b6be48..34f122c0a3c 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -81,8 +81,10 @@ struct clk { u32 clksel_mask; const struct clksel *clksel; struct dpll_data *dpll_data; - const char *clkdm_name; - struct clockdomain *clkdm; + union { + const char *name; + struct clockdomain *ptr; + } clkdm; #else __u8 rate_offset; __u8 src_offset; -- 2.41.1