ASoC: Move headset jack registration to device initialization for SDP3430
Move headset jack registration to the codec/machine specific
initialization. Having the jack registration in machine init
causes that the jack device gets initialized but not registered
since the sound card is registered before the jack. Moving jack
registration to device initialization will register the jack
device along with all other devices associated to the card when
the card is registed. As a consequence of jack device registered
properly, the jack is detected as an input device.
Signed-off-by: Misael Lopez Cruz <x0052729@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Ingo Molnar [Fri, 13 Mar 2009 09:54:24 +0000 (10:54 +0100)]
panic: decrease oops_in_progress only after having done the panic
Impact: eliminate secondary warnings during panic()
We can panic() in a number of difficult, atomic contexts, hence
we use bust_spinlocks(1) in panic() to increase oops_in_progress,
which prevents various debug checks we have in place.
But in practice this protection only covers the first few printk's
done by panic() - it does not cover the later attempt to stop all
other CPUs and kexec(). If a secondary warning triggers in one of
those facilities that can make the panic message scroll off.
So do bust_spinlocks(0) only much later in panic(). (which code
is only reached if panic policy is relaxed that it can return
after a warning message)
Reported-by: Jan Beulich <jbeulich@novell.com>
LKML-Reference: <49B91A7E.76E4.0078.0@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Ilya Yanok [Wed, 11 Mar 2009 00:22:00 +0000 (03:22 +0300)]
qong: basic support for Dave/DENX QongEVB-LITE board
This patch adds basic support for Dave/DENX QongEVB-LITE i.MX31-based
board. It includes support for clocks initialization, UART1, NOR-flash,
FPGA-attached NAND flash and DNET ethernet controller (inside FPGA).
Sascha Hauer [Fri, 6 Feb 2009 16:48:59 +0000 (17:48 +0100)]
[ARM] MX35: add clock support
This patch adds clock support for i.MX35 SoCs. We do not support setting
of clock rates yet, but most interesting clock rates should be reported.
I couldn't test all clock rates and the datasheet contains some obvious
bugs, so expect some bugs in this code.
Sascha Hauer [Fri, 6 Feb 2009 14:38:22 +0000 (15:38 +0100)]
[ARM] MXC: add cpu_is_ macros
We had hardcoded cpu_is_ macros for mxc architectures till now. As we
want to run the same kernel on i.MX31 and i.MX35 this patch adds cpu_is_
macros which expand to 0 or 1 if only one architecture is compiled in and
only check for the cpu type if more than one architecture is compiled
in.
Sascha Hauer [Mon, 2 Feb 2009 13:11:54 +0000 (14:11 +0100)]
[ARM] MX35: Add register definitions for the i.MX35
This patch moves the stuff common to i.MX31 and i.MX35 to mx3x.h and the
specifics to mx31.h/mx35.h. We can build a kernel which runs on i.MX31 and
i.MX35, so always include mx31.h and mx35.h
mx31moboard: initial support for various baseboards
This enables our mx31moboard to be used on the different baseboards that
we are developping according to the application needs. There are not
many differences between the boards for now, but when other peripherals
are available for mx31 the differences are going to grow.
Sascha Hauer [Mon, 26 Jan 2009 16:31:02 +0000 (17:31 +0100)]
imxfb: add 18 bit support
v2: As pointed out by Hans J. Koch we have to claim we can do 24bit to
make software like X work. We are lucky on i.MX that 18bit support
has the necessary gaps in the fields to do so.
Mark Brown [Thu, 15 Jan 2009 16:14:30 +0000 (16:14 +0000)]
mx31ads: Initial support for Wolfson Microelectronics 1133-EV1 module
The i.MX31ADS supports pluggable PMU modules, including the WM835x based
Wolfson Microelectronics 1133-EV1. These boards provide power, audio,
RTC and watchdiog services to the system. This patch adds initial support
for those boards in I2C mode.
Currently support is limited by the available support for the features
of the i.MX31 in the mainline kernel. Some further work will be needed
once other PMU modules are supported and once there is SPI support.
Many of the regulator constraints will be sharable with other PMU
boards.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This example takes advantage of the possibility to use tables of iomux
configs.
This is inspired from mx1-mx2 iomux code. It allows a better code
readability.
This new implemenatation avoids that two physical pins are claimed by
the same driver (also with the the gpr hardware modes).
The gpio kernel lib is also called when a capable gpio pin is assigned
its gpio function.
The mxc_iomux_mode function is still here for backward compatibility but
should not be used anymore.
V2:
In the precendent revision, the iomux code was claiming a pin when its
hardware mode was changed. This was uncorrect: when the hardware mode is
changed, the pin must still be claimed through the iomux.
In order to have a pin working in mode hw2, we must fist issue the
mxc_iomux_set_gpr call and then the corresponding mxc_iomux_mode calls
with the FUNC mode (usually done with mxc_iomux_setup_multiple_pins).
The reverse calls must be done to fee the pins.
Mark Brown [Thu, 15 Jan 2009 16:14:28 +0000 (16:14 +0000)]
mx31ads: Fix build for missing mx31.h
Several of the macros in mx31ads.h depend on mx31.h which is no longer
included in quite so many standard headers as it once was. Include it
directly so we can build.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Mark Brown [Thu, 15 Jan 2009 16:14:27 +0000 (16:14 +0000)]
mx31: Add device definitions for the i.MX3x I2C controllers
The i.MX I2C driver has not yet been merged into mainline but it is
near to that and the device defintions don't depend directly on it
so we can add the devices now.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Holger Schurig [Mon, 26 Jan 2009 15:34:56 +0000 (16:34 +0100)]
arm/imx21: Framebuffer support for i.MX21
This patch mimicks what Martin wrote on the mailing list:
* move arch/arm/mach-imx/include/mach/imxfb.h into
arch/arm/mach-mxc/include/mach/imxfb.h
* changes Kconfig so that CONFIG_FB_IMX is selectable
* adds a platform device (copied from some pengutronix
patches)
* define new CONFIG_ARCH_MX21 (this one is currently mutually exclusive to
CONFIG_ARCH_MX27, but this might change)
* splits one header file. Memory definitions, interrupt sources,
DMA channels are split into common part, i.MX27 specific and i.MX21
specific.
* guard access to UART5/UART6, which don't exist on i.MX21
Holger Schurig [Mon, 26 Jan 2009 15:34:51 +0000 (16:34 +0100)]
arm/imx2x: removes a bunch of sparse-warnings
Here are some of the warnings that get fixed by this:
> 200 times: warning: cast adds address space to expression (<asn:2>)
twelve times: warning: symbol 'xxx' was not declared. Should it be static
two times: warning: symbol 'clock' shadows an earlier one
five times: warning: incorrect type in initializer (different address spaces)
Sascha Hauer [Mon, 16 Feb 2009 13:29:10 +0000 (14:29 +0100)]
[ARM] MXC: remove _clk suffix from clock names
The context makes it clear already that these are clocks, so there's
no need for such a suffix. This patch only changes the clocks actually
used in the tree. The remaining clocks are renamed in the subsequent
architecture specific patches.
Sascha Hauer [Mon, 16 Feb 2009 13:36:49 +0000 (14:36 +0100)]
[ARM] MXC: rework timer/clock initialisation
- rename mxc_clocks_init to architecture specific versions. This
allows us to have more than one architecture compiled in.
- call mxc_timer_init from clock initialisation instead from board
code
Sascha Hauer [Mon, 26 Jan 2009 14:41:16 +0000 (15:41 +0100)]
[ARM] MXC: Use a single function for decoding a PLL
We had 3 versions of this function in clock support for MX1/2/3
Use a single one instead. I picked the one from the MX3 as it seems
to calculate more accurate as the other ones. Also, on MX27 and MX31 mfn
can be negative, this hasn't been handled correctly on MX27 since now.
This patch has been tested on MX27 and MX31 and produces the same clock
frequencies for me.
Holger Schurig [Mon, 26 Jan 2009 15:34:52 +0000 (16:34 +0100)]
arm/imx21: add kbuild support for the Freescale i.MX21
* adds Kconfig variables
* specifies different physical address for i.MX21 because of the
different memory layouts
* disables support for UART5/UART6 in the i.MX serial driver
(the i.MX21 doesn't have those modules)
Based on code from "Martin Fuzzey" <mfuzzey@gmail.com>
Holger Schurig [Thu, 29 Jan 2009 09:07:50 +0000 (10:07 +0100)]
arm/imx2x: new IOMUX definitions
* removed iomux-mx1-mx2.h completely
* distributes the former contents to four different files (iomux-mx1.h,
iomux-mx21.h, iomux-mx27.h and the file iomux-mx2x.h, which is common to
both i.MX21 and i.MX27).
* adds all documented IOMUX definitions for i.MX21 and i.MX27
* fixes a few that were wrong (PD14_AOUT_FEC_CLR, PE16_AF_RTCK).
* don't silenly include <linux/io.h>
* and fixes all collateral damage from above
Andreas Herrmann [Thu, 12 Mar 2009 16:39:37 +0000 (17:39 +0100)]
x86: mtrr: don't modify RdDram/WrDram bits of fixed MTRRs
Impact: bug fix + BIOS workaround
BIOS is expected to clear the SYSCFG[MtrrFixDramModEn] on AMD CPUs
after fixed MTRRs are configured.
Some BIOSes do not clear SYSCFG[MtrrFixDramModEn] on BP (and on APs).
This can lead to obfuscation in Linux when this bit is not cleared on
BP but cleared on APs. A consequence of this is that the saved
fixed-MTRR state (from BP) differs from the fixed-MTRRs of APs --
because RdDram/WrDram bits are read as zero when
SYSCFG[MtrrFixDramModEn] is cleared -- and Linux tries to sync
fixed-MTRR state from BP to AP. This implies that Linux sets
SYSCFG[MtrrFixDramEn] and activates those bits.
More important is that (some) systems change these bits in SMM when
ACPI is enabled. Hence it is racy if Linux modifies RdMem/WrMem bits,
too.
(1) The patch modifies an old fix from Bernhard Kaindl to get
suspend/resume working on some Acer Laptops. Bernhard's patch
tried to sync RdMem/WrMem bits of fixed MTRR registers and that
helped on those old Laptops. (Don't ask me why -- can't test it
myself). But this old problem was not the motivation for the
patch. (See http://lkml.org/lkml/2007/4/3/110)
(2) The more important effect is to fix issues on some more current systems.
On those systems Linux panics or just freezes, see
http://bugzilla.kernel.org/show_bug.cgi?id=11541
(and also duplicates of this bug:
http://bugzilla.kernel.org/show_bug.cgi?id=11737
http://bugzilla.kernel.org/show_bug.cgi?id=11714)
The affected systems boot only using acpi=ht, acpi=off or
when the kernel is built with CONFIG_MTRR=n.
The acpi options prevent full enablement of ACPI. Obviously when
ACPI is enabled the BIOS/SMM modfies RdMem/WrMem bits. When
CONFIG_MTRR=y Linux also accesses and modifies those bits when it
needs to sync fixed-MTRRs across cores (Bernhard's fix, see (1)).
How do you synchronize that? You can't. As a consequence Linux
shouldn't touch those bits at all (Rationale are AMD's BKDGs which
recommend to clear the bit that makes RdMem/WrMem accessible).
This is the purpose of this patch. And (so far) this suffices to
fix (1) and (2).
I suggest not to touch RdDram/WrDram bits of fixed-MTRRs and
SYSCFG[MtrrFixDramEn] and to clear SYSCFG[MtrrFixDramModEn] as
suggested by AMD K8, and AMD family 10h/11h BKDGs.
BIOS is expected to do this anyway. This should avoid that
Linux and SMM tread on each other's toes ...
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: trenn@suse.de Cc: Yinghai Lu <yinghai@kernel.org>
LKML-Reference: <20090312163937.GH20716@alberich.amd.com> Cc: <stable@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Acked-by: Steven Rostedt <rostedt@goodmis.org> Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
LKML-Reference: <1236401580-5758-2-git-send-email-fweisbec@gmail.com>
[ simplified it to a trace_printk() for now. ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
Grant Grundler [Thu, 29 Jan 2009 05:30:55 +0000 (22:30 -0700)]
parisc: fix wrong assumption about bus->self
Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> posted a patch series
to linux-pci to fix a wrong assumption about pci_bus->self==NULL for
all PCI host bus controllers. While PARISC platforms to not behave
this way, I prefer to have the code consistent across architectures.
The following patch replaces pci_bus->self with pci_bus->parent when
used as a test to check for "root bus controller".
Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
Helge Deller [Tue, 13 Jan 2009 20:14:51 +0000 (21:14 +0100)]
parisc: fix dev_printk() compile warnings for accessing a device struct
Fix compile warnings:
drivers/scsi/zalon.c: In function `zalon_probe':
drivers/scsi/zalon.c:140: warning: passing arg 1 of `dev_driver_string' from incompatible pointer type
drivers/scsi/zalon.c:140: warning: passing arg 1 of `dev_name' from incompatible pointer type
Helge Deller [Tue, 13 Jan 2009 19:52:46 +0000 (20:52 +0100)]
parisc: fix `struct pt_regs' declared inside parameter list warning
Fix those compile warnings:
uaccess.h:244: warning: `struct pt_regs' declared inside parameter list
uaccess.h:244: warning: its scope is only this definition or declaration, which is probably not what you want
driver core: move klist_children into private structure
Broke our parisc build pretty badly because we touch the klists directly
in three cases (AGP, SBA and GSC). Although GregKH will revert this
patch, there's no reason we should be using the iterators directly, we
can just move to the standard device_for_each_child() API.
Convert the PS3 Video RAM Storage Driver from an MTD driver to a plain block
device driver.
The ps3vram driver exposes unused video RAM on the PS3 as a block device
suitable for storage or swap. Fast data transfer is achieved using a local
cache in system RAM and DMA transfers via the GPU.
The new driver is ca. 50% faster for reading, and ca. 10% for writing.
projects / linux-2.6-omap-h63xx.git / log