From: Daniel Stone Date: Wed, 27 Aug 2008 01:31:59 +0000 (+0300) Subject: ARM: OMAP2: Fix definition of SGX clock register bits X-Git-Tag: v2.6.27-omap1~178 X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=de1121fdb899f762b9e717f44eaf3fae7c00cd3e;p=linux-2.6-omap-h63xx.git ARM: OMAP2: Fix definition of SGX clock register bits The GFX/SGX functional and interface clocks have different masks, for some unknown reason, so split EN_SGX_SHIFT into one each for fclk and iclk. Correct according to the TRM and the far more important 'does this actually work at all?' metric. Signed-off-by: Daniel Stone Signed-off-by: Tony Lindgren --- diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 56ae83f7932..41f91f8cd5d 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -1378,7 +1378,7 @@ static struct clk sgx_fck = { .name = "sgx_fck", .init = &omap2_init_clksel_parent, .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, + .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, .clksel = sgx_clksel, @@ -1391,7 +1391,7 @@ static struct clk sgx_ick = { .name = "sgx_ick", .parent = &l3_ick, .enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), - .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, + .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, .flags = CLOCK_IN_OMAP3430ES2, .clkdm = { .name = "sgx_clkdm" }, .recalc = &followparent_recalc, diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 1b5d1230b80..3df3a1cae31 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -340,8 +340,12 @@ #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) /* CM_FCLKEN_SGX */ -#define OMAP3430ES2_EN_SGX_SHIFT 1 -#define OMAP3430ES2_EN_SGX_MASK (1 << 1) +#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 +#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) + +/* CM_ICLKEN_SGX */ +#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 +#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) /* CM_CLKSEL_SGX */ #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0