From: Tony Lindgren <tony@atomide.com>
Date: Wed, 4 Jun 2008 18:35:12 +0000 (-0700)
Subject: ARM: OMAP: Remove cm_rmw_reg_bits()
X-Git-Tag: v2.6.26-omap1~123^2~18
X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=9e29f46cdc66ea306f2e98dba57bc08fb21eae48;p=linux-2.6-omap-h63xx.git

ARM: OMAP: Remove cm_rmw_reg_bits()

If done, rmw() should be implemented in a generic way and
discussed on LKML.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 963c259a63c..d3ab537ee85 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -633,6 +633,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 field_mask, field_val, validrate, new_div = 0;
 	void __iomem *div_addr;
+	u32 v;
 
 	validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
 	if (validrate != rate)
@@ -646,7 +647,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 	if (field_val == ~0)
 		return -EINVAL;
 
-	cm_rmw_reg_bits(field_mask, field_val << __ffs(field_mask), div_addr);
+	v = __raw_readl(div_addr);
+	v &= ~field_mask;
+	v |= field_val << __ffs(field_mask);
+	__raw_writel(v, div_addr);
 
 	wmb();
 
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 2aa411deb0c..408b51a15c2 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 {
 	const struct dpll_data *dd;
+	u32 v;
 
 	dd = clk->dpll_data;
 
-	cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
-			dd->control_reg);
+	v = __raw_readl(dd->control_reg);
+	v &= ~dd->enable_mask;
+	v |= clken_bits << __ffs(dd->enable_mask);
+	__raw_writel(v, dd->control_reg);
 }
 
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -443,6 +446,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
 static void omap3_dpll_allow_idle(struct clk *clk)
 {
 	const struct dpll_data *dd;
+	u32 v;
 
 	if (!clk || !clk->dpll_data)
 		return;
@@ -454,9 +458,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
 	 * by writing 0x5 instead of 0x1.  Add some mechanism to
 	 * optionally enter this mode.
 	 */
-	cm_rmw_reg_bits(dd->autoidle_mask,
-			DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
-			dd->autoidle_reg);
+	v = __raw_readl(dd->autoidle_reg);
+	v &= ~dd->autoidle_mask;
+	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
+	__raw_writel(v, dd->autoidle_reg);
 }
 
 /**
@@ -468,15 +473,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
 static void omap3_dpll_deny_idle(struct clk *clk)
 {
 	const struct dpll_data *dd;
+	u32 v;
 
 	if (!clk || !clk->dpll_data)
 		return;
 
 	dd = clk->dpll_data;
 
-	cm_rmw_reg_bits(dd->autoidle_mask,
-			DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
-			dd->autoidle_reg);
+	v = __raw_readl(dd->autoidle_reg);
+	v &= ~dd->autoidle_mask;
+	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
+	__raw_writel(v, dd->autoidle_reg);
 }
 
 /* Clock control for DPLL outputs */
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index bd7bd6eb898..bacadcb0851 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -36,23 +36,6 @@
 #define OMAP3430_CM_CLKOUT_CTRL						\
 				OMAP34XX_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 
-#ifndef __ASSEMBLER__
-
-/* Read-modify-write bits in a CM register */
-static inline u32 cm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *va)
-{
-	u32 v;
-
-	v = __raw_readl(va);
-	v &= ~mask;
-	v |= bits;
-	__raw_writel(v, va);
-
-	return v;
-}
-
-#endif
-
 /*
  * Module specific CM registers from CM_BASE + domain offset
  * Use cm_{read,write}_mod_reg() with these registers.