From: David Gibson <david@gibson.dropbear.id.au>
Date: Tue, 14 Aug 2007 03:52:42 +0000 (+1000)
Subject: [POWERPC] Improve robustness of the UIC cascade handler
X-Git-Tag: v2.6.24-rc1~1450^2~340
X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=553fdff633b1cb8cfccf554768444c5580a8d7f7;p=linux-2.6-omap-h63xx.git

[POWERPC] Improve robustness of the UIC cascade handler

At present the cascade interrupt handler for the UIC (interrupt
controller on 4xx embedded chips) will misbehave badly if it is called
spuriously - that is if the handler is invoked when no interrupts are
asserted in the child UIC.

Although spurious interrupts shouldn't happen, it's good to behave
robustly if they do.  This patch does so by checking for and ignoring
spurious interrupts.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
---

diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index 22c219e448d..47180b3fca5 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -266,6 +266,9 @@ irqreturn_t uic_cascade(int virq, void *data)
 	int subvirq;
 
 	msr = mfdcr(uic->dcrbase + UIC_MSR);
+	if (!msr) /* spurious interrupt */
+		return IRQ_HANDLED;
+
 	src = 32 - ffs(msr);
 
 	subvirq = irq_linear_revmap(uic->irqhost, src);