From: Russell King Date: Thu, 26 Mar 2009 23:10:11 +0000 (+0000) Subject: Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainline into devel X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=542f869f1826f092606efd0c4c771f070d1314f5;hp=-c;p=linux-2.6-omap-h63xx.git Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainline into devel Conflicts: arch/arm/mm/Kconfig Signed-off-by: Russell King --- 542f869f1826f092606efd0c4c771f070d1314f5 diff --combined MAINTAINERS index 50725d026da,52e95780bd8..03b9fb95754 --- a/MAINTAINERS +++ b/MAINTAINERS @@@ -502,6 -502,13 +502,13 @@@ P: Richard Purdi M: rpurdie@rpsys.net S: Maintained + ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE + P: Paulius Zaleckas + M: paulius.zaleckas@teltonika.lt + L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) + T: git gitorious.org/linux-gemini/mainline.git + S: Maintained + ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6) P: Daniel Ribeiro M: drwyrm@gmail.com @@@ -513,6 -520,12 +520,12 @@@ L: openezx-devel@lists.openezx.org (sub W: http://www.openezx.org/ S: Maintained + ARM/FARADAY FA526 PORT + P: Paulius Zaleckas + M: paulius.zaleckas@teltonika.lt + L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) + S: Maintained + ARM/FREESCALE IMX / MXC ARM ARCHITECTURE P: Sascha Hauer M: kernel@pengutronix.de @@@ -622,7 -635,7 +635,7 @@@ P: Dirk Opfe M: dirk@opfer-online.de S: Maintained -ARM/PALMTX SUPPORT +ARM/PALMTX,PALMT5,PALMLD SUPPORT P: Marek Vasut M: marek.vasut@gmail.com W: http://hackndev.com @@@ -3539,22 -3552,6 +3552,22 @@@ M: linux@arm.linux.org.u L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) S: Maintained +PXA168 SUPPORT +P: Eric Miao +M: eric.miao@marvell.com +P: Jason Chagas +M: jason.chagas@marvell.com +L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) +T: git kernel.org:/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git +S: Supported + +PXA910 SUPPORT +P: Eric Miao +M: eric.miao@marvell.com +L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) +T: git kernel.org:/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git +S: Supported + PXA MMCI DRIVER S: Orphan diff --combined arch/arm/Kconfig index e62b37a15a1,5b0204083e0..e02b893fb90 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@@ -241,7 -241,6 +241,7 @@@ config ARCH_VERSATIL config ARCH_AT91 bool "Atmel AT91" select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB select HAVE_CLK help This enables support for systems based on the Atmel AT91RM9200, @@@ -276,6 -275,14 +276,14 @@@ config ARCH_EP93X help This enables support for the Cirrus EP93xx series of CPUs. + config ARCH_GEMINI + bool "Cortina Systems Gemini" + select CPU_FA526 + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Support for the Cortina Systems Gemini family SoCs + config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 @@@ -478,29 -485,12 +486,29 @@@ config ARCH_PX select HAVE_CLK select COMMON_CLKDEV select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK + select COMMON_CLKDEV select GENERIC_TIME select GENERIC_CLOCKEVENTS select TICK_ONESHOT + select PLAT_PXA help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. +config ARCH_MMP + bool "Marvell PXA168/910" + depends on MMU + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select TICK_ONESHOT + select PLAT_PXA + help + Support for Marvell's PXA168/910 processor line. + config ARCH_RPC bool "RiscPC" select ARCH_ACORN @@@ -616,6 -606,8 +624,8 @@@ source "arch/arm/mach-ep93xx/Kconfig source "arch/arm/mach-footbridge/Kconfig" + source "arch/arm/mach-gemini/Kconfig" + source "arch/arm/mach-integrator/Kconfig" source "arch/arm/mach-iop32x/Kconfig" @@@ -635,9 -627,6 +645,9 @@@ source "arch/arm/mach-loki/Kconfig source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-pxa/Kconfig" +source "arch/arm/plat-pxa/Kconfig" + +source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-sa1100/Kconfig" @@@ -707,15 -696,12 +717,15 @@@ config PLAT_IO config PLAT_ORION bool +config PLAT_PXA + bool + source arch/arm/mm/Kconfig config IWMMXT bool "Enable iWMMXt support" - depends on CPU_XSCALE || CPU_XSC3 - default y if PXA27x || PXA3xx + depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK + default y if PXA27x || PXA3xx || ARCH_MMP help Enable support for iWMMXt context switching at run time if running on a CPU that supports it. @@@ -939,23 -925,6 +949,23 @@@ config NODES_SHIF default "2" depends on NEED_MULTIPLE_NODES +config HIGHMEM + bool "High Memory Support (EXPERIMENTAL)" + depends on MMU && EXPERIMENTAL + help + The address space of ARM processors is only 4 Gigabytes large + and it has to accommodate user address space, kernel address + space as well as some memory mapped IO. That means that, if you + have a large amount of physical memory and/or IO, not all of the + memory can be "permanently mapped" by the kernel. The physical + memory that is not permanently mapped is called "high memory". + + Depending on the selected kernel/user memory split, minimum + vmalloc space and actual amount of RAM, you may not need this + option which should result in a slightly faster kernel. + + If unsure, say n. + source "mm/Kconfig" config LEDS @@@ -1133,7 -1102,7 +1143,7 @@@ source "drivers/cpufreq/Kconfig config CPU_FREQ_SA1100 bool - depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_H3800 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT) + depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT) default y config CPU_FREQ_SA1110 diff --combined arch/arm/Makefile index 95186ef17e1,56e13bf2202..e84729bf13d --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@@ -72,6 -72,7 +72,7 @@@ tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi + tune-$(CONFIG_CPU_FA526) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale @@@ -85,10 -86,6 +86,10 @@@ els CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,) endif +ifeq ($(CONFIG_ARM_UNWIND),y) +CFLAGS_ABI +=-funwind-tables +endif + # Need -Uarm for gcc < 3.x KBUILD_CFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm KBUILD_AFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float @@@ -109,10 -106,9 +110,11 @@@ ifeq ($(CONFIG_ARCH_SA1100),y textofs-$(CONFIG_SA1111) := 0x00208000 endif machine-$(CONFIG_ARCH_PXA) := pxa + machine-$(CONFIG_ARCH_MMP) := mmp + plat-$(CONFIG_PLAT_PXA) := pxa machine-$(CONFIG_ARCH_L7200) := l7200 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator + machine-$(CONFIG_ARCH_GEMINI) := gemini textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 machine-$(CONFIG_ARCH_CLPS711X) := clps711x machine-$(CONFIG_ARCH_IOP32X) := iop32x diff --combined arch/arm/boot/compressed/head.S index d14b827adcd,def02483286..b371fba1b95 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@@ -27,12 -27,6 +27,12 @@@ .macro writeb, ch, rb mcr p14, 0, \ch, c0, c5, 0 .endm +#elif defined(CONFIG_CPU_XSCALE) + .macro loadsp, rb + .endm + .macro writeb, ch, rb + mcr p14, 0, \ch, c8, c0, 0 + .endm #else .macro loadsp, rb .endm @@@ -465,6 -459,20 +465,20 @@@ __armv7_mmu_cache_on mcr p15, 0, r0, c7, c5, 4 @ ISB mov pc, r12 + __fa526_cache_on: + mov r12, lr + bl __setup_mmu + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + mcr p15, 0, r0, c8, c7, 0 @ flush UTLB + mrc p15, 0, r0, c1, c0, 0 @ read control reg + orr r0, r0, #0x1000 @ I-cache enable + bl __common_mmu_cache_on + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ flush UTLB + mov pc, r12 + __arm6_mmu_cache_on: mov r12, lr bl __setup_mmu @@@ -636,24 -644,18 +650,30 @@@ proc_types b __armv4_mmu_cache_off b __armv4_mmu_cache_flush + .word 0x56158000 @ PXA168 + .word 0xfffff000 + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv5tej_mmu_cache_flush + + .word 0x56056930 + .word 0xff0ffff0 @ PXA935 + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv4_mmu_cache_flush + .word 0x56050000 @ Feroceon .word 0xff0f0000 b __armv4_mmu_cache_on b __armv4_mmu_cache_off b __armv5tej_mmu_cache_flush + .word 0x66015261 @ FA526 + .word 0xff01fff1 + b __fa526_cache_on + b __armv4_mmu_cache_off + b __fa526_cache_flush + @ These match on the architecture ID .word 0x00020000 @ ARMv4T @@@ -793,6 -795,12 +813,12 @@@ __armv4_mpu_cache_flush mcr p15, 0, ip, c7, c10, 4 @ drain WB mov pc, lr + __fa526_cache_flush: + mov r1, #0 + mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache + mcr p15, 0, r1, c7, c5, 0 @ flush I cache + mcr p15, 0, r1, c7, c10, 4 @ drain WB + mov pc, lr __armv6_mmu_cache_flush: mov r1, #0 diff --combined arch/arm/include/asm/cacheflush.h index bfb0cb9aaa9,a6b8b90ed57..bb7d695f390 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@@ -46,6 -46,14 +46,14 @@@ # define MULTI_CACHE 1 #endif + #if defined(CONFIG_CPU_FA526) + # ifdef _CACHE + # define MULTI_CACHE 1 + # else + # define _CACHE fa + # endif + #endif + #if defined(CONFIG_CPU_ARM926T) # ifdef _CACHE # define MULTI_CACHE 1 @@@ -94,14 -102,6 +102,14 @@@ # endif #endif +#if defined(CONFIG_CPU_MOHAWK) +# ifdef _CACHE +# define MULTI_CACHE 1 +# else +# define _CACHE mohawk +# endif +#endif + #if defined(CONFIG_CPU_FEROCEON) # define MULTI_CACHE 1 #endif diff --combined arch/arm/include/asm/proc-fns.h index c6250311550,00949281d3e..3976412685f --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h @@@ -89,6 -89,14 +89,14 @@@ # define CPU_NAME cpu_arm922 # endif # endif + # ifdef CONFIG_CPU_FA526 + # ifdef CPU_NAME + # undef MULTI_CPU + # define MULTI_CPU + # else + # define CPU_NAME cpu_fa526 + # endif + # endif # ifdef CONFIG_CPU_ARM925T # ifdef CPU_NAME # undef MULTI_CPU @@@ -185,14 -193,6 +193,14 @@@ # define CPU_NAME cpu_xsc3 # endif # endif +# ifdef CONFIG_CPU_MOHAWK +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_mohawk +# endif +# endif # ifdef CONFIG_CPU_FEROCEON # ifdef CPU_NAME # undef MULTI_CPU diff --combined arch/arm/include/asm/system.h index 0a0d49ae1e6,d6a4dad99c9..bd4dc8ed53d --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@@ -97,8 -97,8 +97,8 @@@ extern void __show_regs(struct pt_regs extern int cpu_architecture(void); extern void cpu_init(void); -void arm_machine_restart(char mode); -extern void (*arm_pm_restart)(char str); +void arm_machine_restart(char mode, const char *cmd); +extern void (*arm_pm_restart)(char str, const char *cmd); #define UDBG_UNDEFINED (1 << 0) #define UDBG_SYSCALL (1 << 1) @@@ -125,6 -125,12 +125,12 @@@ extern unsigned int user_debug : : "r" (0) : "memory") #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ : : "r" (0) : "memory") + #elif defined(CONFIG_CPU_FA526) + #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ + : : "r" (0) : "memory") + #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ + : : "r" (0) : "memory") + #define dmb() __asm__ __volatile__ ("" : : : "memory") #else #define isb() __asm__ __volatile__ ("" : : : "memory") #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ diff --combined arch/arm/mm/Kconfig index a6230f7a24c,bc3331863d9..20979564e7e --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@@ -186,6 -186,24 +186,24 @@@ config CPU_ARM926 Say Y if you want support for the ARM926T processor. Otherwise, say N. + # FA526 + config CPU_FA526 + bool + select CPU_32v4 + select CPU_ABRT_EV4 + select CPU_PABRT_NOIFAR + select CPU_CACHE_VIVT + select CPU_CP15_MMU + select CPU_CACHE_FA + select CPU_COPY_FA if MMU + select CPU_TLB_FA if MMU + help + The FA526 is a version of the ARMv4 compatible processor with + Branch Target Buffer, Unified TLB and cache line size 16. + + Say Y if you want support for the FA526 processor. + Otherwise, say N. + # ARM940T config CPU_ARM940T bool "Support ARM940T processor" if ARCH_INTEGRATOR @@@ -340,17 -358,6 +358,17 @@@ config CPU_XSC select CPU_TLB_V4WBI if MMU select IO_36 +# Marvell PJ1 (Mohawk) +config CPU_MOHAWK + bool + select CPU_32v5 + select CPU_ABRT_EV5T + select CPU_PABRT_NOIFAR + select CPU_CACHE_VIVT + select CPU_CP15_MMU + select CPU_TLB_V4WBI if MMU + select CPU_COPY_V4WB if MMU + # Feroceon config CPU_FEROCEON bool @@@ -495,6 -502,9 +513,9 @@@ config CPU_CACHE_VIV config CPU_CACHE_VIPT bool + config CPU_CACHE_FA + bool + if MMU # The copy-page model config CPU_COPY_V3 @@@ -509,6 -519,9 +530,9 @@@ config CPU_COPY_V4W config CPU_COPY_FEROCEON bool + config CPU_COPY_FA + bool + config CPU_COPY_V6 bool @@@ -539,6 -552,13 +563,13 @@@ config CPU_TLB_FEROCEO help Feroceon TLB (v4wbi with non-outer-cachable page table walks). + config CPU_TLB_FA + bool + help + Faraday ARM FA526 architecture, unified TLB with writeback cache + and invalidate instruction cache entry. Branch target buffer is + also supported. + config CPU_TLB_V6 bool @@@ -580,7 -600,7 +611,7 @@@ comment "Processor Features config ARM_THUMB bool "Support Thumb user binaries" - depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON + depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON default y help Say Y if you want to include kernel support for running user space @@@ -649,7 -669,7 +680,7 @@@ config CPU_DCACHE_SIZ config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you @@@ -664,7 -684,7 +695,7 @@@ config CPU_CACHE_ROUND_ROBI config CPU_BPREDICT_DISABLE bool "Disable branch prediction" - depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 - depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 || CPU_FA526 ++ depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 help Say Y here to disable branch prediction. If unsure, say N. @@@ -715,8 -735,7 +746,8 @@@ config CACHE_FEROCEON_L2_WRITETHROUG config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" - depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP + depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ + REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 default y select OUTER_CACHE help diff --combined arch/arm/mm/Makefile index c264683538b,40f941c2245..63e3f6dd0e2 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@@ -16,7 -16,6 +16,7 @@@ obj-$(CONFIG_MODULES) += proc-syms. obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o obj-$(CONFIG_DISCONTIGMEM) += discontig.o +obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o @@@ -33,6 -32,7 +33,7 @@@ obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o + obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o @@@ -42,6 -42,7 +43,7 @@@ obj-$(CONFIG_CPU_COPY_V6) += copypage-v obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o + obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o @@@ -50,6 -51,7 +52,7 @@@ obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wb obj-$(CONFIG_CPU_TLB_FEROCEON) += tlb-v4wbi.o # reuse v4wbi TLB functions obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o + obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o @@@ -63,6 -65,7 +66,7 @@@ obj-$(CONFIG_CPU_ARM925T) += proc-arm92 obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o obj-$(CONFIG_CPU_ARM946E) += proc-arm946.o + obj-$(CONFIG_CPU_FA526) += proc-fa526.o obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o @@@ -71,7 -74,6 +75,7 @@@ obj-$(CONFIG_CPU_SA110) += proc-sa110. obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o +obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V7) += proc-v7.o