From: Sergei Shtylyov Date: Tue, 30 Jan 2007 17:40:30 +0000 (+0300) Subject: pata_sl82c105: wrong assumptions about compatible PIO modes X-Git-Tag: v2.6.21-rc1~274^2~495 X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=24a01453892e0a4a6ad38460541bd0dae9b1837f;p=linux-2.6-omap-h63xx.git pata_sl82c105: wrong assumptions about compatible PIO modes Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1 only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly. Signed-off-by: Jeff Garzik --- diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c index a4034567437..f2fa158d07c 100644 --- a/drivers/ata/pata_sl82c105.c +++ b/drivers/ata/pata_sl82c105.c @@ -139,13 +139,13 @@ static void sl82c105_set_dmamode(struct ata_port *ap, struct ata_device *adev) { switch(adev->dma_mode) { case XFER_MW_DMA_0: - sl82c105_configure_piomode(ap, adev, 1); + sl82c105_configure_piomode(ap, adev, 0); break; case XFER_MW_DMA_1: sl82c105_configure_piomode(ap, adev, 3); break; case XFER_MW_DMA_2: - sl82c105_configure_piomode(ap, adev, 3); + sl82c105_configure_piomode(ap, adev, 4); break; default: BUG();