From: Tony Lindgren Date: Mon, 29 Oct 2007 11:50:40 +0000 (-0700) Subject: Merge current mainline tree into linux-omap tree X-Git-Tag: v2.6.24-omap1~260 X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=19ea3371abfff6bbfa8ef72b50aba042fd26be6b;p=linux-2.6-omap-h63xx.git Merge current mainline tree into linux-omap tree Merge branches 'master' and 'linus' Conflicts: arch/arm/configs/omap_h2_1610_defconfig arch/arm/configs/omap_osk_5912_defconfig arch/arm/mach-omap1/board-h2.c arch/arm/mach-omap1/board-h3.c arch/arm/mach-omap1/board-nokia770.c arch/arm/mach-omap1/board-palmte.c arch/arm/mach-omap1/board-palmtt.c arch/arm/mach-omap1/board-palmz71.c arch/arm/mach-omap1/board-sx1.c arch/arm/mach-omap2/Kconfig arch/arm/mach-omap2/Makefile arch/arm/mach-omap2/board-2430sdp.c arch/arm/mach-omap2/board-apollon.c arch/arm/mach-omap2/board-h4.c arch/arm/mach-omap2/devices.c arch/arm/mach-omap2/gpmc.c arch/arm/mach-omap2/id.c arch/arm/mach-omap2/io.c arch/arm/mach-omap2/irq.c arch/arm/mach-omap2/memory.c arch/arm/mach-omap2/mux.c arch/arm/mach-omap2/pm.c arch/arm/nwfpe/entry.S arch/arm/plat-omap/Makefile drivers/char/watchdog/omap_wdt.c drivers/char/watchdog/omap_wdt.h drivers/i2c/busses/i2c-omap.c drivers/i2c/chips/menelaus.c drivers/input/keyboard/Kconfig drivers/input/keyboard/Makefile drivers/media/video/Kconfig drivers/media/video/Makefile drivers/media/video/tcm825x.c drivers/media/video/v4l2-int-device.c drivers/mtd/onenand/onenand_base.c drivers/usb/gadget/Kconfig drivers/video/Makefile include/asm-arm/arch-omap/board-2430sdp.h include/asm-arm/arch-omap/hardware.h include/asm-arm/arch-omap/io.h include/asm-arm/arch-omap/omap24xx.h include/linux/connector.h --- 19ea3371abfff6bbfa8ef72b50aba042fd26be6b diff --cc Makefile index 49ed72e6eeb,264f37b8b26..e4b927657e8 --- a/Makefile +++ b/Makefile @@@ -188,10 -190,11 +195,11 @@@ SUBARCH := ar # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile ARCH ?= $(SUBARCH) -CROSS_COMPILE ?= +CROSS_COMPILE ?= arm-linux- # Architecture as present in compile.h - UTS_MACHINE := $(ARCH) + UTS_MACHINE := $(ARCH) + SRCARCH := $(ARCH) KCONFIG_CONFIG ?= .config diff --cc arch/arm/mach-omap2/pm.c index daf0b2da784,baf7d82b458..b0a95d774b0 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@@ -39,582 -34,294 +39,572 @@@ #include #include #include +#include #include +#include +#include +#include +#include -#include "prcm-regs.h" +#include "prm.h" +#include "prm_regbits_24xx.h" +#include "cm.h" +#include "cm_regbits_24xx.h" +#include "sdrc.h" -static struct clk *vclk; static void (*omap2_sram_idle)(void); -static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); +static void (*omap2_sram_suspend)(void __iomem *dllctrl); static void (*saved_idle)(void); -extern void __init pmdomain_init(void); -extern void pmdomain_set_autoidle(void); +static u32 omap2_read_32k_sync_counter(void) +{ + return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010); +} + +#ifdef CONFIG_PM_DEBUG +int omap2_pm_debug = 0; -static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE]; +static int serial_console_clock_disabled; +static int serial_console_uart; +static unsigned int serial_console_next_disable; -void omap2_pm_idle(void) +static struct clk *console_iclk, *console_fclk; + +static void serial_console_kick(void) { - local_irq_disable(); - local_fiq_disable(); - if (need_resched()) { - local_fiq_enable(); - local_irq_enable(); + serial_console_next_disable = omap2_read_32k_sync_counter(); + /* Keep the clocks on for 4 secs */ + serial_console_next_disable += 4 * 32768; +} + +static void serial_wait_tx(void) +{ + static const unsigned long uart_bases[3] = { + 0x4806a000, 0x4806c000, 0x4806e000 + }; + unsigned long lsr_reg; + int looped = 0; + + /* Wait for TX FIFO and THR to get empty */ + lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2)); + while ((__raw_readb(lsr_reg) & 0x60) != 0x60) + looped = 1; + if (looped) + serial_console_kick(); +} + +static void serial_console_fclk_mask(u32 *f1, u32 *f2) +{ + switch (serial_console_uart) { + case 1: + *f1 &= ~(1 << 21); + break; + case 2: + *f1 &= ~(1 << 22); + break; + case 3: + *f2 &= ~(1 << 2); + break; + } +} + +static void serial_console_sleep(int enable) +{ + if (console_iclk == NULL || console_fclk == NULL) return; + + if (enable) { + BUG_ON(serial_console_clock_disabled); + if (clk_get_usecount(console_fclk) == 0) + return; + if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0) + return; + serial_wait_tx(); + clk_disable(console_iclk); + clk_disable(console_fclk); + serial_console_clock_disabled = 1; + } else { + int serial_wakeup = 0; + u32 l; + + switch (serial_console_uart) { + case 1: + l = prm_read_mod_reg(CORE_MOD, PM_WKST1); + if (l & OMAP24XX_ST_UART1) + serial_wakeup = 1; + break; + case 2: + l = prm_read_mod_reg(CORE_MOD, PM_WKST1); + if (l & OMAP24XX_ST_UART2) + serial_wakeup = 1; + break; + case 3: + l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2); + if (l & OMAP24XX_ST_UART3) + serial_wakeup = 1; + break; + } + if (serial_wakeup) + serial_console_kick(); + if (!serial_console_clock_disabled) + return; + clk_enable(console_iclk); + clk_enable(console_fclk); + serial_console_clock_disabled = 0; } +} - /* - * Since an interrupt may set up a timer, we don't want to - * reprogram the hardware timer with interrupts enabled. - * Re-enable interrupts only after returning from idle. - */ - timer_dyn_reprogram(); +static void pm_init_serial_console(void) +{ + const struct omap_serial_console_config *conf; + char name[16]; + u32 l; - omap2_sram_idle(); - local_fiq_enable(); - local_irq_enable(); + conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE, + struct omap_serial_console_config); + if (conf == NULL) + return; + if (conf->console_uart > 3 || conf->console_uart < 1) + return; + serial_console_uart = conf->console_uart; + sprintf(name, "uart%d_fck", conf->console_uart); + console_fclk = clk_get(NULL, name); + if (IS_ERR(console_fclk)) + console_fclk = NULL; + name[6] = 'i'; + console_iclk = clk_get(NULL, name); + if (IS_ERR(console_fclk)) + console_iclk = NULL; + if (console_fclk == NULL || console_iclk == NULL) { + serial_console_uart = 0; + return; + } + switch (serial_console_uart) { + case 1: + l = prm_read_mod_reg(CORE_MOD, PM_WKEN1); + l |= OMAP24XX_ST_UART1; + prm_write_mod_reg(l, CORE_MOD, PM_WKEN1); + break; + case 2: + l = prm_read_mod_reg(CORE_MOD, PM_WKEN1); + l |= OMAP24XX_ST_UART2; + prm_write_mod_reg(l, CORE_MOD, PM_WKEN1); + break; + case 3: + l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2); + l |= OMAP24XX_ST_UART3; + prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2); + break; + } } -static int omap2_pm_prepare(void) +#define DUMP_PRM_MOD_REG(mod, reg) \ + regs[reg_count].name = #mod "." #reg; \ + regs[reg_count++].val = prm_read_mod_reg(mod, reg) +#define DUMP_CM_MOD_REG(mod, reg) \ + regs[reg_count].name = #mod "." #reg; \ + regs[reg_count++].val = cm_read_mod_reg(mod, reg) +#define DUMP_PRM_REG(reg) \ + regs[reg_count].name = #reg; \ + regs[reg_count++].val = prm_read_reg(reg) +#define DUMP_CM_REG(reg) \ + regs[reg_count].name = #reg; \ + regs[reg_count++].val = cm_read_reg(reg) +#define DUMP_INTC_REG(reg, off) \ + regs[reg_count].name = #reg; \ + regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off))) + +static void omap2_pm_dump(int mode, int resume, unsigned int us) { - /* We cannot sleep in idle until we have resumed */ - saved_idle = pm_idle; - pm_idle = NULL; - return 0; + struct reg { + const char *name; + u32 val; + } regs[32]; + int reg_count = 0, i; + const char *s1 = NULL, *s2 = NULL; + + if (!resume) { +#if 0 + /* MPU */ + DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU); + DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); + DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL); + DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST); + DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); +#endif +#if 0 + /* INTC */ + DUMP_INTC_REG(INTC_MIR0, 0x0084); + DUMP_INTC_REG(INTC_MIR1, 0x00a4); + DUMP_INTC_REG(INTC_MIR2, 0x00c4); +#endif +#if 0 + DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1); + DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN2); + DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN); + DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1); + DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2); + DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN); + DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN_PLL); + DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL); + DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE); + DUMP_PRM_MOD_REG(CORE_REG, PM_PWSTST); + DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL); +#endif +#if 0 + /* DSP */ + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); + DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL); + DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST); +#endif + } else { + DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1); + DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2); + DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST); + DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU); +#if 1 + DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098); + DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8); + DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8); +#endif + } + + switch (mode) { + case 0: + s1 = "full"; + s2 = "retention"; + break; + case 1: + s1 = "MPU"; + s2 = "retention"; + break; + case 2: + s1 = "MPU"; + s2 = "idle"; + break; + } + + if (!resume) +#if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ) + printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2, + jiffies_to_msecs(get_next_timer_interrupt(jiffies) - + jiffies)); +#else + printk("--- Going to %s %s\n", s1, s2); +#endif + else + printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000); + for (i = 0; i < reg_count; i++) + printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val); } -#define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \ - OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \ - OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3)) +#else +static inline void serial_console_sleep(int enable) {} +static inline void pm_init_serial_console(void) {} +static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {} +static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {} -#define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4)) +#define omap2_pm_debug 0 -#define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \ - OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \ - OMAP_IRQ_BIT(INT_24XX_UART3_IRQ)) +#endif -#define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, ®, reg); +static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */ -static void omap2_pm_debug(char * desc) +static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf) { - printk("%s:\n", desc); - - preg(CM_CLKSTCTRL_MPU); - preg(CM_CLKSTCTRL_CORE); - preg(CM_CLKSTCTRL_GFX); - preg(CM_CLKSTCTRL_DSP); - preg(CM_CLKSTCTRL_MDM); - - preg(PM_PWSTCTRL_MPU); - preg(PM_PWSTCTRL_CORE); - preg(PM_PWSTCTRL_GFX); - preg(PM_PWSTCTRL_DSP); - preg(PM_PWSTCTRL_MDM); - - preg(PM_PWSTST_MPU); - preg(PM_PWSTST_CORE); - preg(PM_PWSTST_GFX); - preg(PM_PWSTST_DSP); - preg(PM_PWSTST_MDM); - - preg(CM_AUTOIDLE1_CORE); - preg(CM_AUTOIDLE2_CORE); - preg(CM_AUTOIDLE3_CORE); - preg(CM_AUTOIDLE4_CORE); - preg(CM_AUTOIDLE_WKUP); - preg(CM_AUTOIDLE_PLL); - preg(CM_AUTOIDLE_DSP); - preg(CM_AUTOIDLE_MDM); - - preg(CM_ICLKEN1_CORE); - preg(CM_ICLKEN2_CORE); - preg(CM_ICLKEN3_CORE); - preg(CM_ICLKEN4_CORE); - preg(CM_ICLKEN_GFX); - preg(CM_ICLKEN_WKUP); - preg(CM_ICLKEN_DSP); - preg(CM_ICLKEN_MDM); - - preg(CM_IDLEST1_CORE); - preg(CM_IDLEST2_CORE); - preg(CM_IDLEST3_CORE); - preg(CM_IDLEST4_CORE); - preg(CM_IDLEST_GFX); - preg(CM_IDLEST_WKUP); - preg(CM_IDLEST_CKGEN); - preg(CM_IDLEST_DSP); - preg(CM_IDLEST_MDM); - - preg(RM_RSTST_MPU); - preg(RM_RSTST_GFX); - preg(RM_RSTST_WKUP); - preg(RM_RSTST_DSP); - preg(RM_RSTST_MDM); - - preg(PM_WKDEP_MPU); - preg(PM_WKDEP_CORE); - preg(PM_WKDEP_GFX); - preg(PM_WKDEP_DSP); - preg(PM_WKDEP_MDM); - - preg(CM_FCLKEN_WKUP); - preg(CM_ICLKEN_WKUP); - preg(CM_IDLEST_WKUP); - preg(CM_AUTOIDLE_WKUP); - preg(CM_CLKSEL_WKUP); - - preg(PM_WKEN_WKUP); - preg(PM_WKST_WKUP); + return sprintf(buf, "%hu\n", enable_dyn_sleep); } -static inline void omap2_pm_save_registers(void) +static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys, + const char * buf, + size_t n) { - /* Save interrupt registers */ - OMAP24XX_SAVE(INTC_MIR0); - OMAP24XX_SAVE(INTC_MIR1); - OMAP24XX_SAVE(INTC_MIR2); - - /* Save power control registers */ - OMAP24XX_SAVE(CM_CLKSTCTRL_MPU); - OMAP24XX_SAVE(CM_CLKSTCTRL_CORE); - OMAP24XX_SAVE(CM_CLKSTCTRL_GFX); - OMAP24XX_SAVE(CM_CLKSTCTRL_DSP); - OMAP24XX_SAVE(CM_CLKSTCTRL_MDM); - - /* Save power state registers */ - OMAP24XX_SAVE(PM_PWSTCTRL_MPU); - OMAP24XX_SAVE(PM_PWSTCTRL_CORE); - OMAP24XX_SAVE(PM_PWSTCTRL_GFX); - OMAP24XX_SAVE(PM_PWSTCTRL_DSP); - OMAP24XX_SAVE(PM_PWSTCTRL_MDM); - - /* Save autoidle registers */ - OMAP24XX_SAVE(CM_AUTOIDLE1_CORE); - OMAP24XX_SAVE(CM_AUTOIDLE2_CORE); - OMAP24XX_SAVE(CM_AUTOIDLE3_CORE); - OMAP24XX_SAVE(CM_AUTOIDLE4_CORE); - OMAP24XX_SAVE(CM_AUTOIDLE_WKUP); - OMAP24XX_SAVE(CM_AUTOIDLE_PLL); - OMAP24XX_SAVE(CM_AUTOIDLE_DSP); - OMAP24XX_SAVE(CM_AUTOIDLE_MDM); - - /* Save idle state registers */ - OMAP24XX_SAVE(CM_IDLEST1_CORE); - OMAP24XX_SAVE(CM_IDLEST2_CORE); - OMAP24XX_SAVE(CM_IDLEST3_CORE); - OMAP24XX_SAVE(CM_IDLEST4_CORE); - OMAP24XX_SAVE(CM_IDLEST_GFX); - OMAP24XX_SAVE(CM_IDLEST_WKUP); - OMAP24XX_SAVE(CM_IDLEST_CKGEN); - OMAP24XX_SAVE(CM_IDLEST_DSP); - OMAP24XX_SAVE(CM_IDLEST_MDM); - - /* Save clock registers */ - OMAP24XX_SAVE(CM_FCLKEN1_CORE); - OMAP24XX_SAVE(CM_FCLKEN2_CORE); - OMAP24XX_SAVE(CM_ICLKEN1_CORE); - OMAP24XX_SAVE(CM_ICLKEN2_CORE); - OMAP24XX_SAVE(CM_ICLKEN3_CORE); - OMAP24XX_SAVE(CM_ICLKEN4_CORE); + unsigned short value; + if (sscanf(buf, "%hu", &value) != 1 || + (value != 0 && value != 1)) { + printk(KERN_ERR "idle_sleep_store: Invalid value\n"); + return -EINVAL; + } + enable_dyn_sleep = value; + return n; } -static inline void omap2_pm_restore_registers(void) +static struct subsys_attribute sleep_while_idle_attr = { + .attr = { + .name = __stringify(sleep_while_idle), + .mode = 0644, + }, + .show = omap_pm_sleep_while_idle_show, + .store = omap_pm_sleep_while_idle_store, +}; + +static struct clk *osc_ck, *emul_ck; + +#define CONTROL_DEVCONF __REG32(OMAP2_CTRL_BASE + 0x274) + +static int omap2_fclks_active(void) { - /* Restore clock state registers */ - OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU); - OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE); - OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX); - OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP); - OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM); - - /* Restore power state registers */ - OMAP24XX_RESTORE(PM_PWSTCTRL_MPU); - OMAP24XX_RESTORE(PM_PWSTCTRL_CORE); - OMAP24XX_RESTORE(PM_PWSTCTRL_GFX); - OMAP24XX_RESTORE(PM_PWSTCTRL_DSP); - OMAP24XX_RESTORE(PM_PWSTCTRL_MDM); - - /* Restore idle state registers */ - OMAP24XX_RESTORE(CM_IDLEST1_CORE); - OMAP24XX_RESTORE(CM_IDLEST2_CORE); - OMAP24XX_RESTORE(CM_IDLEST3_CORE); - OMAP24XX_RESTORE(CM_IDLEST4_CORE); - OMAP24XX_RESTORE(CM_IDLEST_GFX); - OMAP24XX_RESTORE(CM_IDLEST_WKUP); - OMAP24XX_RESTORE(CM_IDLEST_CKGEN); - OMAP24XX_RESTORE(CM_IDLEST_DSP); - OMAP24XX_RESTORE(CM_IDLEST_MDM); - - /* Restore autoidle registers */ - OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE); - OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE); - OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE); - OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE); - OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP); - OMAP24XX_RESTORE(CM_AUTOIDLE_PLL); - OMAP24XX_RESTORE(CM_AUTOIDLE_DSP); - OMAP24XX_RESTORE(CM_AUTOIDLE_MDM); - - /* Restore clock registers */ - OMAP24XX_RESTORE(CM_FCLKEN1_CORE); - OMAP24XX_RESTORE(CM_FCLKEN2_CORE); - OMAP24XX_RESTORE(CM_ICLKEN1_CORE); - OMAP24XX_RESTORE(CM_ICLKEN2_CORE); - OMAP24XX_RESTORE(CM_ICLKEN3_CORE); - OMAP24XX_RESTORE(CM_ICLKEN4_CORE); - - /* REVISIT: Clear interrupts here */ - - /* Restore interrupt registers */ - OMAP24XX_RESTORE(INTC_MIR0); - OMAP24XX_RESTORE(INTC_MIR1); - OMAP24XX_RESTORE(INTC_MIR2); + u32 f1, f2; + + f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + serial_console_fclk_mask(&f1, &f2); + if (f1 | f2) + return 1; + return 0; } -static int omap2_pm_suspend(void) +static int omap2_irq_pending(void) { - int processor_type = 0; + u32 pending_reg = IO_ADDRESS(0x480fe098); + int i; - /* REVISIT: 0x21 or 0x26? */ - if (cpu_is_omap2420()) - processor_type = 0x21; + for (i = 0; i < 4; i++) { + if (__raw_readl(pending_reg)) + return 1; + pending_reg += 0x20; + } + return 0; +} - if (!processor_type) - return -ENOTSUPP; +static atomic_t sleep_block = ATOMIC_INIT(0); - local_irq_disable(); - local_fiq_disable(); +void omap2_block_sleep(void) +{ + atomic_inc(&sleep_block); +} - omap2_pm_save_registers(); +void omap2_allow_sleep(void) +{ + int i; - /* Disable interrupts except for the wake events */ - INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK; - INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK; - INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK; + i = atomic_dec_return(&sleep_block); + BUG_ON(i < 0); +} - pmdomain_set_autoidle(); +static void omap2_enter_full_retention(void) +{ + u32 sleep_time = 0; + + /* There is 1 reference hold for all children of the oscillator + * clock, the following will remove it. If no one else uses the + * oscillator itself it will be disabled if/when we enter retention + * mode. + */ + clk_disable(osc_ck); /* Clear old wake-up events */ - PM_WKST1_CORE = 0; - PM_WKST2_CORE = 0; - PM_WKST_WKUP = 0; + /* REVISIT: These write to reserved bits? */ + prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); - /* Enable wake-up events */ - PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */ - PM_WKEN2_CORE = (1 << 2); /* UART3 */ - PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */ + /* Try to enter retention */ + prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE, + MPU_MOD, PM_PWSTCTRL); + + /* Workaround to kill USB */ + CONTROL_DEVCONF |= 0x00008000; - /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled - * in the SRAM suspend code */ - CM_FCLKEN1_CORE = 0; - CM_FCLKEN2_CORE = 0; - CM_ICLKEN1_CORE = 0; - CM_ICLKEN3_CORE = 0; - CM_ICLKEN4_CORE = 0; + omap2_gpio_prepare_for_retention(); - omap2_pm_debug("Status before suspend"); + if (omap2_pm_debug) { + omap2_pm_dump(0, 0, 0); + sleep_time = omap2_read_32k_sync_counter(); + } + + /* One last check for pending IRQs to avoid extra latency due + * to sleeping unnecessarily. */ + if (omap2_irq_pending()) + goto no_sleep; + + serial_console_sleep(1); + /* Jump to SRAM suspend code */ + omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL)); +no_sleep: + serial_console_sleep(0); + + if (omap2_pm_debug) { + unsigned long long tmp; + u32 resume_time; + + resume_time = omap2_read_32k_sync_counter(); + tmp = resume_time - sleep_time; + tmp *= 1000000; + omap2_pm_dump(0, 1, tmp / 32768); + } + omap2_gpio_resume_after_retention(); + + clk_enable(osc_ck); + +} + +static int omap2_i2c_active(void) +{ + u32 l; + + l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1); +} + +static int sti_console_enabled; + +static int omap2_allow_mpu_retention(void) +{ + u32 l; + + if (atomic_read(&sleep_block)) + return 0; + + /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ + l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 | + OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 | + OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1)) + return 0; + /* Check for UART3. */ + l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + if (l & OMAP24XX_EN_UART3) + return 0; + if (sti_console_enabled) + return 0; + + return 1; +} + +static void omap2_enter_mpu_retention(void) +{ + u32 sleep_time = 0; + int only_idle = 0; + + /* Putting MPU into the WFI state while a transfer is active + * seems to cause the I2C block to timeout. Why? Good question. */ + if (omap2_i2c_active()) + return; + + /* The peripherals seem not to be able to wake up the MPU when + * it is in retention mode. */ + if (omap2_allow_mpu_retention()) { + /* REVISIT: These write to reserved bits? */ + prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + + /* Try to enter MPU retention */ + prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | + OMAP_LOGICRETSTATE, + MPU_MOD, PM_PWSTCTRL); + } else { + /* Block MPU retention */ + + prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL); + only_idle = 1; + } + + if (omap2_pm_debug) { + omap2_pm_dump(only_idle ? 2 : 1, 0, 0); + sleep_time = omap2_read_32k_sync_counter(); + } + + omap2_sram_idle(); - /* Must wait for serial buffers to clear */ - mdelay(200); + if (omap2_pm_debug) { + unsigned long long tmp; + u32 resume_time; - /* Jump to SRAM suspend code - * REVISIT: When is this SDRC_DLLB_CTRL? + resume_time = omap2_read_32k_sync_counter(); + tmp = resume_time - sleep_time; + tmp *= 1000000; + omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768); + } +} + +static int omap2_can_sleep(void) +{ + if (!enable_dyn_sleep) + return 0; + if (omap2_fclks_active()) + return 0; + if (atomic_read(&sleep_block) > 0) + return 0; + if (clk_get_usecount(osc_ck) > 1) + return 0; + if (omap_dma_running()) + return 0; + + return 1; +} + +static void omap2_pm_idle(void) +{ + local_irq_disable(); + local_fiq_disable(); + + if (!omap2_can_sleep()) { + /* timer_dyn_reprogram() takes about 100-200 us to complete. + * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA + * transfer to complete), the increased latency is too much. + * + * omap2_block_sleep() and omap2_allow_sleep() can be used + * to indicate this. + */ + if (atomic_read(&sleep_block) == 0) { + timer_dyn_reprogram(); + if (omap2_irq_pending()) + goto out; + } + omap2_enter_mpu_retention(); + goto out; + } + + /* + * Since an interrupt may set up a timer, we don't want to + * reprogram the hardware timer with interrupts enabled. + * Re-enable interrupts only after returning from idle. */ - omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type); + timer_dyn_reprogram(); - /* Back from sleep */ - omap2_pm_restore_registers(); + if (omap2_irq_pending()) + goto out; + omap2_enter_full_retention(); + +out: local_fiq_enable(); local_irq_enable(); +} + - static int omap2_pm_prepare(suspend_state_t state) ++static int omap2_pm_prepare(void) +{ - int error = 0; - + /* We cannot sleep in idle until we have resumed */ + saved_idle = pm_idle; + pm_idle = NULL; + - switch (state) { - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: - break; - default: - return -EINVAL; - } - - return error; ++ return 0; +} + +static int omap2_pm_suspend(void) +{ + u32 wken_wkup, mir1; + + wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); + prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN); + + /* Mask GPT1 */ + mir1 = omap_readl(0x480fe0a4); + omap_writel(1 << 5, 0x480fe0ac); + + omap2_enter_full_retention(); + + omap_writel(mir1, 0x480fe0a4); + prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); return 0; } @@@ -645,142 -352,16 +634,142 @@@ static struct platform_suspend_ops omap .prepare = omap2_pm_prepare, .enter = omap2_pm_enter, .finish = omap2_pm_finish, - .valid = pm_valid_only_mem, + .valid = suspend_valid_only_mem, }; +static void __init prcm_setup_regs(void) +{ + u32 l; + + /* Enable autoidle */ + prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG); + + /* Set all domain wakeup dependencies */ + prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP); + prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP); + prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); + + l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL); + /* Enable retention for all memory blocks */ + l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE | + OMAP24XX_MEM1RETSTATE; + + /* Set power state to RETENTION */ + l &= ~OMAP_POWERSTATE_MASK; + l |= 0x01 << OMAP_POWERSTATE_SHIFT; + prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL); + + prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | + OMAP_LOGICRETSTATE, + MPU_MOD, PM_PWSTCTRL); + + /* Power down DSP and GFX */ + prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT), + OMAP24XX_DSP_MOD, PM_PWSTCTRL); + prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT), + GFX_MOD, PM_PWSTCTRL); + + /* Enable clock auto control for all domains */ + cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL); + cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 | + OMAP24XX_AUTOSTATE_L3, + CORE_MOD, CM_CLKSTCTRL); + cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL); + cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP, + OMAP24XX_DSP_MOD, CM_CLKSTCTRL); + + /* Enable clock autoidle for all domains */ + cm_write_mod_reg(OMAP24XX_AUTO_CAM | + OMAP24XX_AUTO_MAILBOXES | + OMAP24XX_AUTO_WDT4 | + OMAP2420_AUTO_WDT3 | + OMAP24XX_AUTO_MSPRO | + OMAP2420_AUTO_MMC | + OMAP24XX_AUTO_FAC | + OMAP2420_AUTO_EAC | + OMAP24XX_AUTO_HDQ | + OMAP24XX_AUTO_UART2 | + OMAP24XX_AUTO_UART1 | + OMAP24XX_AUTO_I2C2 | + OMAP24XX_AUTO_I2C1 | + OMAP24XX_AUTO_MCSPI2 | + OMAP24XX_AUTO_MCSPI1 | + OMAP24XX_AUTO_MCBSP2 | + OMAP24XX_AUTO_MCBSP1 | + OMAP24XX_AUTO_GPT12 | + OMAP24XX_AUTO_GPT11 | + OMAP24XX_AUTO_GPT10 | + OMAP24XX_AUTO_GPT9 | + OMAP24XX_AUTO_GPT8 | + OMAP24XX_AUTO_GPT7 | + OMAP24XX_AUTO_GPT6 | + OMAP24XX_AUTO_GPT5 | + OMAP24XX_AUTO_GPT4 | + OMAP24XX_AUTO_GPT3 | + OMAP24XX_AUTO_GPT2 | + OMAP2420_AUTO_VLYNQ | + OMAP24XX_AUTO_DSS, + CORE_MOD, CM_AUTOIDLE1); + cm_write_mod_reg(OMAP24XX_AUTO_UART3 | + OMAP24XX_AUTO_SSI | + OMAP24XX_AUTO_USB, + CORE_MOD, CM_AUTOIDLE2); + cm_write_mod_reg(OMAP24XX_AUTO_SDRC | + OMAP24XX_AUTO_GPMC | + OMAP24XX_AUTO_SDMA, + CORE_MOD, OMAP24XX_CM_AUTOIDLE3); + cm_write_mod_reg(OMAP24XX_AUTO_PKA | + OMAP24XX_AUTO_AES | + OMAP24XX_AUTO_RNG | + OMAP24XX_AUTO_SHA | + OMAP24XX_AUTO_DES, + CORE_MOD, OMAP24XX_CM_AUTOIDLE4); + + cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE); + + /* Put DPLL and both APLLs into autoidle mode */ + cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | + (0x03 << OMAP24XX_AUTO_96M_SHIFT) | + (0x03 << OMAP24XX_AUTO_54M_SHIFT), + PLL_MOD, CM_AUTOIDLE); + + cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL | + OMAP24XX_AUTO_WDT1 | + OMAP24XX_AUTO_MPU_WDT | + OMAP24XX_AUTO_GPIOS | + OMAP24XX_AUTO_32KSYNC | + OMAP24XX_AUTO_GPT1, + WKUP_MOD, CM_AUTOIDLE); + + /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk + * stabilisation */ + prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP); + + /* Configure automatic voltage transition */ + prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP); + prm_write_reg(OMAP24XX_AUTO_EXTVOLT | + (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | + OMAP24XX_MEMRETCTRL | + (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | + (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), + OMAP24XX_PRCM_VOLTCTRL); + + /* Enable wake-up events */ + prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1, + WKUP_MOD, PM_WKEN); +} + int __init omap2_pm_init(void) { - printk("Power Management for TI OMAP.\n"); + u32 l; + + printk(KERN_INFO "Power Management for OMAP2 initializing\n"); + l = prm_read_reg(OMAP24XX_PRCM_REVISION); + printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); - vclk = clk_get(NULL, "virt_prcm_set"); - if (IS_ERR(vclk)) { - printk(KERN_ERR "Could not get PM vclk\n"); + osc_ck = clk_get(NULL, "osc_ck"); + if (IS_ERR(osc_ck)) { + printk(KERN_ERR "could not get osc_ck\n"); return -ENODEV; } @@@ -817,12 -375,11 +806,12 @@@ omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, omap24xx_cpu_suspend_sz); - pm_set_ops(&omap_pm_ops); + suspend_set_ops(&omap_pm_ops); pm_idle = omap2_pm_idle; - pmdomain_init(); + l = subsys_create_file(&power_subsys, &sleep_while_idle_attr); + if (l) + printk(KERN_ERR "subsys_create_file failed: %d\n", l); return 0; } diff --cc arch/arm/mach-omap2/timer-gp.c index 2246435b029,8d322c20cca..c377d830a1d --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@@ -3,14 -3,9 +3,14 @@@ * * OMAP2 GP timer support. * + * Update to use new clocksource/clockevent layers + * Author: Kevin Hilman, MontaVista Software, Inc. + * Copyright (C) 2007 MontaVista Software, Inc. + * + * Original driver: * Copyright (C) 2005 Nokia Corporation * Author: Paul Mundt - * Juha Yrjölä + * Juha Yrjölä * OMAP Dual-mode timer framework support by Timo Teras * * Some parts based off of TI's 24xx code: diff --cc drivers/bluetooth/Makefile index d5a449d0c36,77444afbf10..0fab1f0318d --- a/drivers/bluetooth/Makefile +++ b/drivers/bluetooth/Makefile @@@ -12,9 -12,10 +12,12 @@@ obj-$(CONFIG_BT_HCIDTL1) += dtl1_cs. obj-$(CONFIG_BT_HCIBT3C) += bt3c_cs.o obj-$(CONFIG_BT_HCIBLUECARD) += bluecard_cs.o obj-$(CONFIG_BT_HCIBTUART) += btuart_cs.o +obj-$(CONFIG_BT_HCIBRF6150) += brf6150.o +obj-$(CONFIG_BT_HCIH4P) += hci_h4p/ + obj-$(CONFIG_BT_HCIBTUSB) += btusb.o + obj-$(CONFIG_BT_HCIBTSDIO) += btsdio.o + hci_uart-y := hci_ldisc.o hci_uart-$(CONFIG_BT_HCIUART_H4) += hci_h4.o hci_uart-$(CONFIG_BT_HCIUART_BCSP) += hci_bcsp.o diff --cc drivers/input/keyboard/Kconfig index 0dddbb04868,2316a018fae..54395433219 --- a/drivers/input/keyboard/Kconfig +++ b/drivers/input/keyboard/Kconfig @@@ -217,26 -238,6 +238,32 @@@ config KEYBOARD_OMA To compile this driver as a module, choose M here: the module will be called omap-keypad. +config KEYBOARD_TWL4030 + tristate "TI TWL4030 keypad support" + depends on TWL4030_CORE && MACH_OMAP_2430SDP + help + Say Y here if you want to use the OMAP TWL4030 keypad. + + To compile this driver as a module, choose M here: the + module will be called omap-twl4030keypad. This driver depends on + TWL4030 Core and TWL4030 GPIO I2C client driver + +config OMAP_PS2 + tristate "TI OMAP Innovator 1510 PS/2 keyboard & mouse support" + depends on ARCH_OMAP15XX && MACH_OMAP_INNOVATOR + help + Say Y here if you want to use the OMAP Innovator 1510 PS/2 + keyboard and mouse. + + To compile this driver as a module, choose M here: the + module will be called innovator_ps2. + ++config KEYBOARD_TSC2301 ++ tristate "TSC2301 keypad support" ++ depends on SPI_TSC2301 ++ help ++ Say Y here for if you are using the keypad features of TSC2301. ++ config KEYBOARD_PXA27x tristate "PXA27x keyboard support" depends on PXA27x diff --cc drivers/input/keyboard/Makefile index 4cad7f107fc,e97455fdcc8..06956ba66d5 --- a/drivers/input/keyboard/Makefile +++ b/drivers/input/keyboard/Makefile @@@ -17,10 -17,11 +17,14 @@@ obj-$(CONFIG_KEYBOARD_CORGI) += corgik obj-$(CONFIG_KEYBOARD_SPITZ) += spitzkbd.o obj-$(CONFIG_KEYBOARD_HIL) += hil_kbd.o obj-$(CONFIG_KEYBOARD_HIL_OLD) += hilkbd.o - obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o + obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o +obj-$(CONFIG_OMAP_PS2) += innovator_ps2.o ++obj-$(CONFIG_KEYBOARD_TSC2301) += tsc2301_kp.o ++obj-$(CONFIG_KEYBOARD_TWL4030) += omap-twl4030keypad.o obj-$(CONFIG_KEYBOARD_PXA27x) += pxa27x_keyboard.o - obj-$(CONFIG_KEYBOARD_AAED2000) += aaed2000_kbd.o + obj-$(CONFIG_KEYBOARD_AAED2000) += aaed2000_kbd.o obj-$(CONFIG_KEYBOARD_GPIO) += gpio_keys.o - obj-$(CONFIG_KEYBOARD_TSC2301) += tsc2301_kp.o - obj-$(CONFIG_KEYBOARD_TWL4030) += omap-twl4030keypad.o + obj-$(CONFIG_KEYBOARD_HP6XX) += jornada680_kbd.o + obj-$(CONFIG_KEYBOARD_HP7XX) += jornada720_kbd.o + obj-$(CONFIG_KEYBOARD_MAPLE) += maple_keyb.o + obj-$(CONFIG_KEYBOARD_BFIN) += bf54x-keys.o diff --cc drivers/leds/Kconfig index 9f44d47530f,ec568fa1c6c..b82b67d025b --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@@ -81,30 -81,9 +81,30 @@@ config LEDS_WRA help This option enables support for the PCEngines WRAP programmable LEDs. +config LEDS_OMAP_DEBUG + boolean "LED Support for OMAP debug board LEDs" + depends on LEDS_CLASS=y && ARCH_OMAP + help + Enables support for the LEDs on the debug board used with OMAP + reference boards like H2/H3/H4 and Perseus2. Up to six of these + may be claimed by the original ARM debug LED API. + +config LEDS_OMAP + tristate "LED Support for OMAP GPIO LEDs" + depends on LEDS_CLASS && ARCH_OMAP + help + This option enables support for the LEDs on OMAP processors. + +config LEDS_OMAP_PWM + tristate "LED Support for OMAP PWM-controlled LEDs" + depends on LEDS_CLASS && ARCH_OMAP && OMAP_DM_TIMER + help + This options enables support for LEDs connected to GPIO lines + controlled by a PWM timer on OMAP CPUs. + config LEDS_H1940 tristate "LED Support for iPAQ H1940 device" - depends LEDS_CLASS && ARCH_H1940 + depends on LEDS_CLASS && ARCH_H1940 help This option enables support for the LEDs on the h1940. diff --cc drivers/leds/Makefile index a322855dd9a,a60de1b46c2..806a9d4c731 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@@ -14,11 -14,11 +14,13 @@@ obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c obj-$(CONFIG_LEDS_AMS_DELTA) += leds-ams-delta.o obj-$(CONFIG_LEDS_NET48XX) += leds-net48xx.o obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o +obj-$(CONFIG_LEDS_OMAP) += leds-omap.o +obj-$(CONFIG_LEDS_OMAP_PWM) += leds-omap-pwm.o obj-$(CONFIG_LEDS_H1940) += leds-h1940.o - obj-$(CONFIG_LEDS_COBALT) += leds-cobalt.o + obj-$(CONFIG_LEDS_COBALT_QUBE) += leds-cobalt-qube.o + obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o + obj-$(CONFIG_LEDS_CM_X270) += leds-cm-x270.o # LED Triggers obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o diff --cc drivers/media/video/Kconfig index c374a9b621b,2e571eb9313..7285f088be3 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@@ -676,10 -668,10 +676,12 @@@ config VIDEO_HEXIUM_GEMIN source "drivers/media/video/cx88/Kconfig" + source "drivers/media/video/cx23885/Kconfig" + source "drivers/media/video/ivtv/Kconfig" +source drivers/media/video/omap/Kconfig + config VIDEO_M32R_AR tristate "AR devices" depends on M32R && VIDEO_V4L1 diff --cc drivers/mtd/onenand/Makefile index ce11f7c3b78,4d2eacfd7e1..64b6cc61a52 --- a/drivers/mtd/onenand/Makefile +++ b/drivers/mtd/onenand/Makefile @@@ -7,6 -7,8 +7,9 @@@ obj-$(CONFIG_MTD_ONENAND) += onenand. # Board specific. obj-$(CONFIG_MTD_ONENAND_GENERIC) += generic.o +obj-$(CONFIG_MTD_ONENAND_OMAP2) += omap2.o + # Simulator + obj-$(CONFIG_MTD_ONENAND_SIM) += onenand_sim.o + onenand-objs = onenand_base.o onenand_bbt.o diff --cc drivers/mtd/onenand/onenand_base.c index 7daeb161bec,dd283556909..1b0b3201141 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@@ -342,7 -359,7 +359,7 @@@ static int onenand_wait(struct mtd_inf */ static irqreturn_t onenand_interrupt(int irq, void *data) { -- struct onenand_chip *this = (struct onenand_chip *) data; ++ struct onenand_chip *this = data; /* To handle shared interrupt */ if (!this->complete.done) diff --cc drivers/usb/gadget/Kconfig index 5b73ddf3cf2,f81d08d6538..0933eef2fa1 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@@ -228,17 -253,6 +253,16 @@@ config USB_LH7A40 default USB_GADGET select USB_GADGET_SELECTED - +# built in ../musb along with host support +config USB_GADGET_MUSB_HDRC + boolean "Inventra HDRC USB Peripheral (TI, ...)" + depends on USB_MUSB_HDRC && (USB_MUSB_PERIPHERAL || USB_MUSB_OTG) + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + help + This OTG-capable silicon IP is used in dual designs including + the TI DaVinci, OMAP 243x, OMAP 343x, and TUSB 6010. + config USB_GADGET_OMAP boolean "OMAP USB Device Controller" depends on ARCH_OMAP diff --cc drivers/video/omap/Kconfig index f12193b2ddb,f4fcf11b290..9418047e684 --- a/drivers/video/omap/Kconfig +++ b/drivers/video/omap/Kconfig @@@ -1,49 -1,14 +1,49 @@@ config FB_OMAP tristate "OMAP frame buffer support (EXPERIMENTAL)" - depends on FB - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help + depends on FB + help Frame buffer driver for OMAP based boards. +config FB_OMAP_LCDC_EXTERNAL + bool "External LCD controller support" + depends on FB_OMAP + help + Say Y here, if you want to have support for boards with an + external LCD controller connected to the SoSSI/RFBI interface. + +config FB_OMAP_LCDC_HWA742 + bool "Epson HWA742 LCD controller support" + depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL + help + Say Y here if you want to have support for the external + Epson HWA742 LCD controller. + +config FB_OMAP_LCDC_BLIZZARD + bool "Epson Blizzard LCD controller support" + depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL + help + Say Y here if you want to have support for the external + Epson Blizzard LCD controller. + +config FB_OMAP_MANUAL_UPDATE + bool "Default to manual update mode" + depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL + help + Say Y here, if your user-space applications are capable of + notifying the frame buffer driver when a change has occured in + the frame buffer content and thus a reload of the image data to + the external frame buffer is required. If unsure, say N. + +config FB_OMAP_LCD_MIPID + bool "MIPI DBI-C/DCS compatible LCD support" + depends on FB_OMAP && SPI_MASTER && CBUS_TAHVO + help + Say Y here if you want to have support for LCDs compatible with + the Mobile Industry Processor Interface DBI-C/DCS + specification. (Supported LCDs: Philips LPH8923, Sharp LS041Y3) + config FB_OMAP_BOOTLOADER_INIT - bool "Check bootloader initializaion" + bool "Check bootloader initialization" depends on FB_OMAP help Say Y here if you want to enable checking if the bootloader has diff --cc include/linux/i2c-id.h index e0c59ae60cd,88c81403eb3..7463833d647 --- a/include/linux/i2c-id.h +++ b/include/linux/i2c-id.h @@@ -119,9 -119,9 +119,11 @@@ #define I2C_DRIVERID_WM8750 90 /* Wolfson WM8750 audio codec */ #define I2C_DRIVERID_WM8753 91 /* Wolfson WM8753 audio codec */ #define I2C_DRIVERID_LM4857 92 /* LM4857 Audio Amplifier */ + #define I2C_DRIVERID_VP27SMPX 93 /* Panasonic VP27s tuner internal MPX */ + #define I2C_DRIVERID_CS4270 94 /* Cirrus Logic 4270 audio codec */ +#define I2C_DRIVERID_MISC 99 /* Whatever until sorted out */ + #define I2C_DRIVERID_I2CDEV 900 #define I2C_DRIVERID_ARP 902 /* SMBus ARP Client */ #define I2C_DRIVERID_ALERT 903 /* SMBus Alert Responder Client */