From: Dmitri Vorobiev Date: Mon, 14 Jan 2008 21:27:46 +0000 (+0300) Subject: [MIPS] Malta: Fix reading the PCI clock frequency on big-endian X-Git-Tag: v2.6.24~27^2~1 X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=commitdiff_plain;h=0487de91427925e7c43debeb948bdf53b10ef32c;p=linux-2.6-omap-h63xx.git [MIPS] Malta: Fix reading the PCI clock frequency on big-endian The JMPRS register on Malta boards keeps a 32-bit CPU-endian value. The readw() function assumes that the value it reads is a little-endian 16-bit number. Therefore, using readw() to obtain the value of the JMPRS register is a mistake. This error leads to incorrect reading of the PCI clock frequency on big-endian during board start-up. Change readw() to __raw_readl(). This was tested by injecting a call to printk() and verifying that the value of the jmpr variable was consistent with current setting of the JP4 "PCI CLK" jumper. Signed-off-by: Dmitri Vorobiev Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index 9a2636e5624..bc43a5c2224 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -149,7 +149,7 @@ void __init plat_mem_setup(void) /* Check PCI clock */ { unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); - int jmpr = (readw(jmpr_p) >> 2) & 0x07; + int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; static const int pciclocks[] __initdata = { 33, 20, 25, 30, 12, 16, 37, 10 };