#endif
+ /* --------------------------------------------------------------------
+ * USB HS Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+ #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
+
+ static struct resource usba_udc_resources[] = {
+ [0] = {
+ .start = AT91CAP9_UDPHS_FIFO,
+ .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91CAP9_BASE_UDPHS,
+ .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = AT91CAP9_ID_UDPHS,
+ .end = AT91CAP9_ID_UDPHS,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
+ [idx] = { \
+ .name = nam, \
+ .index = idx, \
+ .fifo_size = maxpkt, \
+ .nr_banks = maxbk, \
+ .can_dma = dma, \
+ .can_isoc = isoc, \
+ }
+
+ static struct usba_ep_data usba_udc_ep[] = {
+ EP("ep0", 0, 64, 1, 0, 0),
+ EP("ep1", 1, 1024, 3, 1, 1),
+ EP("ep2", 2, 1024, 3, 1, 1),
+ EP("ep3", 3, 1024, 2, 1, 1),
+ EP("ep4", 4, 1024, 2, 1, 1),
+ EP("ep5", 5, 1024, 2, 1, 0),
+ EP("ep6", 6, 1024, 2, 1, 0),
+ EP("ep7", 7, 1024, 2, 0, 0),
+ };
+
+ #undef EP
+
+ /*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+ static struct {
+ struct usba_platform_data pdata;
+ struct usba_ep_data ep[8];
+ } usba_udc_data;
+
+ static struct platform_device at91_usba_udc_device = {
+ .name = "atmel_usba_udc",
+ .id = -1,
+ .dev = {
+ .platform_data = &usba_udc_data.pdata,
+ },
+ .resource = usba_udc_resources,
+ .num_resources = ARRAY_SIZE(usba_udc_resources),
+ };
+
+ void __init at91_add_device_usba(struct usba_platform_data *data)
+ {
+ at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
+ AT91_MATRIX_UDPHS_BYPASS_LOCK);
+
+ /*
+ * Invalid pins are 0 on AT91, but the usba driver is shared
+ * with AVR32, which use negative values instead. Once/if
+ * gpio_is_valid() is ported to AT91, revisit this code.
+ */
+ usba_udc_data.pdata.vbus_pin = -EINVAL;
+ usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
+ memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
+
+ if (data && data->vbus_pin > 0) {
+ at91_set_gpio_input(data->vbus_pin, 0);
+ at91_set_deglitch(data->vbus_pin, 1);
+ usba_udc_data.pdata.vbus_pin = data->vbus_pin;
+ }
+
+ /* Pullup pin is handled internally by USB device peripheral */
+
+ /* Clocks */
+ at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
+ at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
+
+ platform_device_register(&at91_usba_udc_device);
+ }
+ #else
+ void __init at91_add_device_usba(struct usba_platform_data *data) {}
+ #endif
+
+
/* --------------------------------------------------------------------
* Ethernet
* -------------------------------------------------------------------- */
* -------------------------------------------------------------------- */
#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
-static struct at91_nand_data nand_data;
+static struct atmel_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
};
static struct platform_device at91cap9_nand_device = {
- .name = "at91_nand",
+ .name = "atmel_nand",
.id = -1,
.dev = {
.platform_data = &nand_data,
.num_resources = ARRAY_SIZE(nand_resources),
};
-void __init at91_add_device_nand(struct at91_nand_data *data)
+void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa, mode;
platform_device_register(&at91cap9_nand_device);
}
#else
-void __init at91_add_device_nand(struct at91_nand_data *data) {}
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
+ #include <asm/arch/cpu.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
* -------------------------------------------------------------------- */
#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
-static struct at91_nand_data nand_data;
+static struct atmel_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
};
static struct platform_device at91sam9260_nand_device = {
- .name = "at91_nand",
+ .name = "atmel_nand",
.id = -1,
.dev = {
.platform_data = &nand_data,
.num_resources = ARRAY_SIZE(nand_resources),
};
-void __init at91_add_device_nand(struct at91_nand_data *data)
+void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa, mode;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
- /* set the bus interface characteristics */
- at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
- | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ if (cpu_is_at91sam9260()) {
+ /* Timing for sam9260 */
+ /* set the bus interface characteristics */
+ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+ | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
- | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+ | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- if (data->bus_width_16)
- mode = AT91_SMC_DBW_16;
- else
- mode = AT91_SMC_DBW_8;
- at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
+ if (data->bus_width_16)
+ mode = AT91_SMC_DBW_16;
+ else
+ mode = AT91_SMC_DBW_8;
+ at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
+ }
+
+ if (cpu_is_at91sam9g20()) {
+ /* Timing for sam9g20 */
+ /* set the bus interface characteristics */
+ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0)
+ | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+
+ at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4)
+ | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
+
+ at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+
+ if (data->bus_width_16)
+ mode = AT91_SMC_DBW_16;
+ else
+ mode = AT91_SMC_DBW_8;
+ at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(3));
+ }
/* enable pin */
if (data->enable_pin)
platform_device_register(&at91sam9260_nand_device);
}
#else
-void __init at91_add_device_nand(struct at91_nand_data *data) {}
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
* -------------------------------------------------------------------- */
#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
-static struct at91_nand_data nand_data;
+static struct atmel_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
}
};
-static struct platform_device at91_nand_device = {
- .name = "at91_nand",
+static struct platform_device atmel_nand_device = {
+ .name = "atmel_nand",
.id = -1,
.dev = {
.platform_data = &nand_data,
.num_resources = ARRAY_SIZE(nand_resources),
};
-void __init at91_add_device_nand(struct at91_nand_data *data)
+void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa, mode;
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* set the bus interface characteristics */
- at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
- | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+ | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
- | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+ at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+ | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+ at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
if (data->bus_width_16)
mode = AT91_SMC_DBW_16;
else
mode = AT91_SMC_DBW_8;
- at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+ at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
/* enable pin */
if (data->enable_pin)
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
nand_data = *data;
- platform_device_register(&at91_nand_device);
+ platform_device_register(&atmel_nand_device);
}
#else
-void __init at91_add_device_nand(struct at91_nand_data *data) {}
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
* -------------------------------------------------------------------- */
#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
-static struct at91_nand_data nand_data;
+static struct atmel_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
};
static struct platform_device at91sam9263_nand_device = {
- .name = "at91_nand",
+ .name = "atmel_nand",
.id = -1,
.dev = {
.platform_data = &nand_data,
.num_resources = ARRAY_SIZE(nand_resources),
};
-void __init at91_add_device_nand(struct at91_nand_data *data)
+void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa, mode;
at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
/* set the bus interface characteristics */
- at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
- | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+ | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
| AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
platform_device_register(&at91sam9263_nand_device);
}
#else
-void __init at91_add_device_nand(struct at91_nand_data *data) {}
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
#include "generic.h"
+ /* --------------------------------------------------------------------
+ * USB HS Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+ #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
+
+ static struct resource usba_udc_resources[] = {
+ [0] = {
+ .start = AT91SAM9RL_UDPHS_FIFO,
+ .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9RL_BASE_UDPHS,
+ .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = AT91SAM9RL_ID_UDPHS,
+ .end = AT91SAM9RL_ID_UDPHS,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
+ [idx] = { \
+ .name = nam, \
+ .index = idx, \
+ .fifo_size = maxpkt, \
+ .nr_banks = maxbk, \
+ .can_dma = dma, \
+ .can_isoc = isoc, \
+ }
+
+ static struct usba_ep_data usba_udc_ep[] __initdata = {
+ EP("ep0", 0, 64, 1, 0, 0),
+ EP("ep1", 1, 1024, 2, 1, 1),
+ EP("ep2", 2, 1024, 2, 1, 1),
+ EP("ep3", 3, 1024, 3, 1, 0),
+ EP("ep4", 4, 1024, 3, 1, 0),
+ EP("ep5", 5, 1024, 3, 1, 1),
+ EP("ep6", 6, 1024, 3, 1, 1),
+ };
+
+ #undef EP
+
+ /*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+ static struct {
+ struct usba_platform_data pdata;
+ struct usba_ep_data ep[7];
+ } usba_udc_data;
+
+ static struct platform_device at91_usba_udc_device = {
+ .name = "atmel_usba_udc",
+ .id = -1,
+ .dev = {
+ .platform_data = &usba_udc_data.pdata,
+ },
+ .resource = usba_udc_resources,
+ .num_resources = ARRAY_SIZE(usba_udc_resources),
+ };
+
+ void __init at91_add_device_usba(struct usba_platform_data *data)
+ {
+ /*
+ * Invalid pins are 0 on AT91, but the usba driver is shared
+ * with AVR32, which use negative values instead. Once/if
+ * gpio_is_valid() is ported to AT91, revisit this code.
+ */
+ usba_udc_data.pdata.vbus_pin = -EINVAL;
+ usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
+ memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
+
+ if (data && data->vbus_pin > 0) {
+ at91_set_gpio_input(data->vbus_pin, 0);
+ at91_set_deglitch(data->vbus_pin, 1);
+ usba_udc_data.pdata.vbus_pin = data->vbus_pin;
+ }
+
+ /* Pullup pin is handled internally by USB device peripheral */
+
+ /* Clocks */
+ at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
+ at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
+
+ platform_device_register(&at91_usba_udc_device);
+ }
+ #else
+ void __init at91_add_device_usba(struct usba_platform_data *data) {}
+ #endif
+
+
/* --------------------------------------------------------------------
* MMC / SD
* -------------------------------------------------------------------- */
* -------------------------------------------------------------------- */
#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
-static struct at91_nand_data nand_data;
+static struct atmel_nand_data nand_data;
#define NAND_BASE AT91_CHIPSELECT_3
}
};
-static struct platform_device at91_nand_device = {
- .name = "at91_nand",
+static struct platform_device atmel_nand_device = {
+ .name = "atmel_nand",
.id = -1,
.dev = {
.platform_data = &nand_data,
.num_resources = ARRAY_SIZE(nand_resources),
};
-void __init at91_add_device_nand(struct at91_nand_data *data)
+void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
/* set the bus interface characteristics */
- at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
- | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
+ | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
- | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
+ at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
+ | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
+ at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
+ at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
/* enable pin */
if (data->enable_pin)
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
nand_data = *data;
- platform_device_register(&at91_nand_device);
+ platform_device_register(&atmel_nand_device);
}
#else
-void __init at91_add_device_nand(struct at91_nand_data *data) {}
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
.ports = 2,
};
+ /*
+ * USB HS Device port
+ */
+ static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
+ .vbus_pin = AT91_PIN_PB31,
+ };
/*
* ADS7846 Touchscreen
return cap9adk_nand_partitions;
}
-static struct at91_nand_data __initdata cap9adk_nand_data = {
+static struct atmel_nand_data __initdata cap9adk_nand_data = {
.ale = 21,
.cle = 22,
// .det_pin = ... not connected
/* USB Host */
set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH);
at91_add_device_usbh(&cap9adk_usbh_data);
+ /* USB HS */
+ set_irq_type(AT91CAP9_ID_UDPHS, IRQT_HIGH);
+ at91_add_device_usba(&cap9adk_usba_udc_data);
/* SPI */
at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
/* Touchscreen */
#include "generic.h"
- /*
- * Serial port configuration.
- * 0 .. 3 = USART0 .. USART3
- * 4 = DBGU
- */
- static struct at91_uart_config __initdata dk_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 2,
- .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
- };
-
static void __init dk_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
- /* Setup the serial ports and console */
- at91_init_serial(&dk_uart_config);
+ /* DBGU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+ at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+ | ATMEL_UART_RI);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
}
static void __init dk_init_irq(void)
return dk_nand_partition;
}
-static struct at91_nand_data __initdata dk_nand_data = {
+static struct atmel_nand_data __initdata dk_nand_data = {
.ale = 22,
.cle = 21,
.det_pin = AT91_PIN_PB1,
#define DK_FLASH_SIZE 0x200000
static struct physmap_flash_data dk_flash_data = {
- .width = 2,
+ .width = 2,
};
static struct resource dk_flash_resource = {
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
- #include "generic.h"
+ #include <asm/arch/at91rm9200_mc.h>
+ #include "generic.h"
- /*
- * Serial port configuration.
- * 0 .. 3 = USART0 .. USART3
- * 4 = DBGU
- */
- static struct at91_uart_config __initdata kb9202_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 3,
- .tty_map = { 4, 0, 1, -1, -1 } /* ttyS0, ..., ttyS4 */
- };
static void __init kb9202_map_io(void)
{
/* Set up the LEDs */
at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
- /* Setup the serial ports and console */
- at91_init_serial(&kb9202_uart_config);
+ /* DBGU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
+
+ /* USART0 on ttyS1 (Rx & Tx only) */
+ at91_register_uart(AT91RM9200_ID_US0, 1, 0);
+
+ /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
+ at91_register_uart(AT91RM9200_ID_US1, 2, 0);
+
+ /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
+ at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
}
static void __init kb9202_init_irq(void)
return kb9202_nand_partition;
}
-static struct at91_nand_data __initdata kb9202_nand_data = {
+static struct atmel_nand_data __initdata kb9202_nand_data = {
.ale = 22,
.cle = 21,
// .det_pin = ... not there
}
+ /*
+ * USB HS Device port
+ */
+ static struct usba_platform_data __initdata ek_usba_udc_data = {
+ .vbus_pin = AT91_PIN_PA8,
+ };
+
+
/*
* MCI (SD/MMC)
*/
return ek_nand_partition;
}
-static struct at91_nand_data __initdata ek_nand_data = {
+static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
// .det_pin = ... not connected
{
/* Serial */
at91_add_device_serial();
+ /* USB HS */
+ at91_add_device_usba(&ek_usba_udc_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* NAND */
/*
* linux/arch/arm/mach-at91/board-yl-9200.c
*
- * Adapted from:
- *various board files in
- * /arch/arm/mach-at91
- * modifications to convert to YL-9200 platform
- * Copyright (C) 2007 S.Birtles
+ * Adapted from various board files in arch/arm/mach-at91
+ *
+ * Modifications for YL-9200 platform:
+ * Copyright (C) 2007 S. Birtles
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
+ #include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
- /*#include <linux/can_bus/candata.h>*/
#include <linux/spi/ads7846.h>
#include <linux/mtd/physmap.h>
+ #include <linux/gpio_keys.h>
+ #include <linux/input.h>
- /*#include <sound/gpio_sounder.h>*/
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/arch/board.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91rm9200_mc.h>
- #include <linux/gpio_keys.h>
- #include <linux/input.h>
#include "generic.h"
- #include <asm/arch/at91_pio.h>
- #define YL_9200_FLASH_BASE AT91_CHIPSELECT_0
- #define YL_9200_FLASH_SIZE 0x800000
- /*
- * Serial port configuration.
- * 0 .. 3 = USART0 .. USART3
- * 4 = DBGU
- *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
- *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
- *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
- *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
- *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
- * on the YL-9200 we are sitting at the following
- *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
- *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
- */
+ static void __init yl9200_map_io(void)
+ {
+ /* Initialize processor: 18.432 MHz crystal */
+ at91rm9200_initialize(18432000, AT91RM9200_PQFP);
- /* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/
+ /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
+ at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
- static struct at91_uart_config __initdata yl_9200_uart_config = {
- .console_tty = 0, /* ttyS0 */
- .nr_tty = 3,
- .tty_map = { 4, 1, 0, -1, -1 } /* ttyS0, ..., ttyS4 */
- };
+ /* DBGU on ttyS0. (Rx & Tx only) */
+ at91_register_uart(0, 0, 0);
- static void __init yl_9200_map_io(void)
- {
- /* Initialize processor: 18.432 MHz crystal */
- /*Also initialises register clocks & gpio*/
- at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
+ /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+ at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+ | ATMEL_UART_RI);
- /* Setup the serial ports and console */
- at91_init_serial(&yl_9200_uart_config);
+ /* USART0 on ttyS2. (Rx & Tx only to JP3) */
+ at91_register_uart(AT91RM9200_ID_US0, 2, 0);
- /* Setup the LEDs D2=PB17,D3=PB16 */
- at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/
+ /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
+ at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
+
+ /* set serial console to ttyS0 (ie, DBGU) */
+ at91_set_serial_console(0);
}
- static void __init yl_9200_init_irq(void)
+ static void __init yl9200_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
- static struct at91_eth_data __initdata yl_9200_eth_data = {
- .phy_irq_pin = AT91_PIN_PB28,
- .is_rmii = 1,
- };
- static struct at91_usbh_data __initdata yl_9200_usbh_data = {
- .ports = 1, /* this should be 1 not 2 for the Yl9200*/
+ /*
+ * LEDs
+ */
+ static struct gpio_led yl9200_leds[] = {
+ { /* D2 */
+ .name = "led2",
+ .gpio = AT91_PIN_PB17,
+ .active_low = 1,
+ .default_trigger = "timer",
+ },
+ { /* D3 */
+ .name = "led3",
+ .gpio = AT91_PIN_PB16,
+ .active_low = 1,
+ .default_trigger = "heartbeat",
+ },
+ { /* D4 */
+ .name = "led4",
+ .gpio = AT91_PIN_PB15,
+ .active_low = 1,
+ },
+ { /* D5 */
+ .name = "led5",
+ .gpio = AT91_PIN_PB8,
+ .active_low = 1,
+ }
};
- static struct at91_udc_data __initdata yl_9200_udc_data = {
- /*on sheet 7 Schemitic rev 1.0*/
- .pullup_pin = AT91_PIN_PC4,
- .vbus_pin= AT91_PIN_PC5,
- .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
-
- };
/*
- static struct at91_cf_data __initdata yl_9200_cf_data = {
- TODO S.BIRTLES
- .det_pin = AT91_PIN_xxx,
- .rst_pin = AT91_PIN_xxx,
- .irq_pin = ... not connected
- .vcc_pin = ... always powered
-
+ * Ethernet
+ */
+ static struct at91_eth_data __initdata yl9200_eth_data = {
+ .phy_irq_pin = AT91_PIN_PB28,
+ .is_rmii = 1,
};
- */
- static struct at91_mmc_data __initdata yl_9200_mmc_data = {
- .det_pin = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
- /* .wp_pin = ... not connected SHEET7*/
- .slot_b = 0,
- .wire4 = 1,
+ /*
+ * USB Host
+ */
+ static struct at91_usbh_data __initdata yl9200_usbh_data = {
+ .ports = 1, /* PQFP version of AT91RM9200 */
};
- /* --------------------------------------------------------------------
- * Touch screen
- * -------------------------------------------------------------------- */
- #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
- static int ads7843_pendown_state(void)
- {
- return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
- }
-
- static void __init at91_init_device_ts(void)
- {
- /*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
- THAT IS TO SAY THAT MISO,MOSI,SPCK AND CS are already configured
- we only need to enable the other datapins which are:
- PB10/RK1 BUSY
- */
- /* Touchscreen BUSY signal , pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
- at91_set_gpio_input(AT91_PIN_PB10, 1);
- }
-
- #else
- static void __init at91_init_device_ts(void) {}
- #endif
-
- static struct ads7846_platform_data ads_info = {
- .model = 7843,
- .x_min = 150,
- .x_max = 3830,
- .y_min = 190,
- .y_max = 3830,
- .vref_delay_usecs = 100,
- /* for a 8" touch screen*/
- //.x_plate_ohms = 603, //= 450, S.Birtles TODO
- //.y_plate_ohms = 332, //= 250, S.Birtles TODO
- /*for a 10.4" touch screen*/
- //.x_plate_ohms =611,
- //.y_plate_ohms =325,
-
- .x_plate_ohms = 576,
- .y_plate_ohms = 366,
- //
- .pressure_max = 15000, /*generally nonsense on the 7843*/
- /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
- .debounce_max = 1,
- .debounce_rep = 0,
- .debounce_tol = (~0),
- .get_pendown_state = ads7843_pendown_state,
- };
+ /*
+ * USB Device
+ */
+ static struct at91_udc_data __initdata yl9200_udc_data = {
+ .pullup_pin = AT91_PIN_PC4,
+ .vbus_pin = AT91_PIN_PC5,
+ .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
- /*static struct canbus_platform_data can_info = {
- .model = 2510,
};
- */
-
- static struct spi_board_info yl_9200_spi_devices[] = {
- /*this sticks it at:
- /sys/devices/platform/atmel_spi.0/spi0.0
- /sys/bus/platform/devices/
- Documentation/spi IIRC*/
- #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
- /*(this IS correct 04-NOV-2007)*/
- {
- .modalias = "ads7846", /* because the driver is called ads7846*/
- .chip_select = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */
- /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/
- /*.controller_data =AT91_PIN_PA3 ,*/
- .max_speed_hz = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
- .bus_num = 0,
- .platform_data = &ads_info,
- .irq = AT91_PIN_PB11,
- },
- #endif
- /*we need to put our CAN driver data here!!*/
- /*THIS IS ALL DUMMY DATA*/
- /* {
- .modalias = "mcp2510", //DUMMY for MCP2510 chip
- .chip_select = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */
- /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
- /* .controller_data =AT91_PIN_PA4 ,
- .max_speed_hz = 25000 * 26,
- .bus_num = 0,
- .platform_data = &can_info,
- .irq = AT91_PIN_PC0,
- },
- */
- //max SPI chip needs to go here
+ /*
+ * MMC
+ */
+ static struct at91_mmc_data __initdata yl9200_mmc_data = {
+ .det_pin = AT91_PIN_PB9,
+ // .wp_pin = ... not connected
+ .wire4 = 1,
};
- static struct mtd_partition __initdata yl_9200_nand_partition[] = {
+ /*
+ * NAND Flash
+ */
+ static struct mtd_partition __initdata yl9200_nand_partition[] = {
{
.name = "AT91 NAND partition 1, boot",
.offset = 0,
.name = "AT91 NAND partition 5, ext-fs",
.offset = 32 * SZ_1M,
.size = 32 * SZ_1M
- },
+ }
};
static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
{
- *num_partitions = ARRAY_SIZE(yl_9200_nand_partition);
- return yl_9200_nand_partition;
+ *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
+ return yl9200_nand_partition;
}
- static struct atmel_nand_data __initdata yl_9200_nand_data = {
- .ale= 6,
- .cle= 7,
- /*.det_pin = AT91_PIN_PCxx,*/ /*we don't have a det pin because NandFlash is fixed to board*/
- .rdy_pin = AT91_PIN_PC14, /*R/!B Sheet10*/
- .enable_pin = AT91_PIN_PC15, /*!CE Sheet10 */
-static struct at91_nand_data __initdata yl9200_nand_data = {
++static struct atmel_nand_data __initdata yl9200_nand_data = {
+ .ale = 6,
+ .cle = 7,
+ // .det_pin = ... not connected
+ .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
+ .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
.partition_info = nand_partitions,
};
-
-
/*
- TODO S.Birtles
- potentially a problem with the size above
- physmap platform flash device: 00800000 at 10000000
- physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
- NOR chip too large to fit in mapping. Attempting to cope...
- Intel/Sharp Extended Query Table at 0x0031
- Using buffer write method
- cfi_cmdset_0001: Erase suspend on write enabled
- Reducing visibility of 16384KiB chip to 8192KiB
- */
+ * NOR Flash
+ */
+ #define YL9200_FLASH_BASE AT91_CHIPSELECT_0
+ #define YL9200_FLASH_SIZE 0x1000000
- static struct mtd_partition yl_9200_flash_partitions[] = {
+ static struct mtd_partition yl9200_flash_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 0x00040000,
+ .offset = 0,
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
{
- .name = "Bootloader",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- },{
- .name = "Kernel",
- .size = 0x001C0000,
- .offset = 0x00040000,
- },{
- .name = "Filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x00200000
+ .name = "Kernel",
+ .size = 0x001C0000,
+ .offset = 0x00040000,
+ },
+ {
+ .name = "Filesystem",
+ .size = MTDPART_SIZ_FULL,
+ .offset = 0x00200000
}
-
};
- static struct physmap_flash_data yl_9200_flash_data = {
- .width = 2,
- .parts = yl_9200_flash_partitions,
- .nr_parts = ARRAY_SIZE(yl_9200_flash_partitions),
+ static struct physmap_flash_data yl9200_flash_data = {
+ .width = 2,
+ .parts = yl9200_flash_partitions,
+ .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
};
- static struct resource yl_9200_flash_resources[] = {
- {
- .start = YL_9200_FLASH_BASE,
- .end = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1,
- .flags = IORESOURCE_MEM,
+ static struct resource yl9200_flash_resources[] = {
+ {
+ .start = YL9200_FLASH_BASE,
+ .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
+ .flags = IORESOURCE_MEM,
}
};
- static struct platform_device yl_9200_flash = {
+ static struct platform_device yl9200_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
- .platform_data = &yl_9200_flash_data,
+ .platform_data = &yl9200_flash_data,
},
- .resource = yl_9200_flash_resources,
- .num_resources = ARRAY_SIZE(yl_9200_flash_resources),
+ .resource = yl9200_flash_resources,
+ .num_resources = ARRAY_SIZE(yl9200_flash_resources),
};
-
- static struct gpio_led yl_9200_leds[] = {
- /*D2 &D3 are passed directly in via at91_init_leds*/
- {
- .name = "led4", /*D4*/
- .gpio = AT91_PIN_PB15,
- .active_low = 1,
- .default_trigger = "heartbeat",
- /*.default_trigger = "timer",*/
- },
- {
- .name = "led5", /*D5*/
- .gpio = AT91_PIN_PB8,
- .active_low = 1,
- .default_trigger = "heartbeat",
- }
- };
-
- //static struct gpio_sounder yl_9200_sounder[] = {*/
- /*This is a simple speaker attached to a gpo line*/
-
- // {
- // .name = "Speaker", /*LS1*/
- // .gpio = AT91_PIN_PA22,
- // .active_low = 0,
- // .default_trigger = "heartbeat",
- /*.default_trigger = "timer",*/
- // },
- //};
-
-
-
- static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
- {
- /*TODO*/
- I2C_BOARD_INFO("CS4334", 0x00),
+ /*
+ * I2C (TWI)
+ */
+ static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
+ { /* EEPROM */
+ I2C_BOARD_INFO("24c128", 0x50),
}
};
-
- /*
+ /*
* GPIO Buttons
- */
+ */
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
- static struct gpio_keys_button yl_9200_buttons[] = {
+ static struct gpio_keys_button yl9200_buttons[] = {
{
.gpio = AT91_PIN_PA24,
- .code = BTN_2,
+ .code = BTN_2,
.desc = "SW2",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB1,
- .code = BTN_3,
+ .code = BTN_3,
.desc = "SW3",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB2,
- .code = BTN_4,
+ .code = BTN_4,
.desc = "SW4",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB6,
- .code = BTN_5,
+ .code = BTN_5,
.desc = "SW5",
.active_low = 1,
.wakeup = 1,
- },
-
+ }
};
- static struct gpio_keys_platform_data yl_9200_button_data = {
- .buttons = yl_9200_buttons,
- .nbuttons = ARRAY_SIZE(yl_9200_buttons),
+ static struct gpio_keys_platform_data yl9200_button_data = {
+ .buttons = yl9200_buttons,
+ .nbuttons = ARRAY_SIZE(yl9200_buttons),
};
- static struct platform_device yl_9200_button_device = {
+ static struct platform_device yl9200_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
- .platform_data = &yl_9200_button_data,
+ .platform_data = &yl9200_button_data,
}
};
- static void __init yl_9200_add_device_buttons(void)
+ static void __init yl9200_add_device_buttons(void)
{
- //SW2
- at91_set_gpio_input(AT91_PIN_PA24, 0);
+ at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
at91_set_deglitch(AT91_PIN_PA24, 1);
-
- //SW3
- at91_set_gpio_input(AT91_PIN_PB1, 0);
+ at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
at91_set_deglitch(AT91_PIN_PB1, 1);
- //SW4
- at91_set_gpio_input(AT91_PIN_PB2, 0);
+ at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
at91_set_deglitch(AT91_PIN_PB2, 1);
-
- //SW5
- at91_set_gpio_input(AT91_PIN_PB6, 0);
+ at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
at91_set_deglitch(AT91_PIN_PB6, 1);
+ /* Enable buttons (Sheet 5) */
+ at91_set_gpio_output(AT91_PIN_PB7, 1);
+
+ platform_device_register(&yl9200_button_device);
+ }
+ #else
+ static void __init yl9200_add_device_buttons(void) {}
+ #endif
+
+ /*
+ * Touchscreen
+ */
+ #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+ static int ads7843_pendown_state(void)
+ {
+ return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
+ }
+
+ static struct ads7846_platform_data ads_info = {
+ .model = 7843,
+ .x_min = 150,
+ .x_max = 3830,
+ .y_min = 190,
+ .y_max = 3830,
+ .vref_delay_usecs = 100,
+
+ /* For a 8" touch-screen */
+ // .x_plate_ohms = 603,
+ // .y_plate_ohms = 332,
+
+ /* For a 10.4" touch-screen */
+ // .x_plate_ohms = 611,
+ // .y_plate_ohms = 325,
+
+ .x_plate_ohms = 576,
+ .y_plate_ohms = 366,
+
+ .pressure_max = 15000, /* generally nonsense on the 7843 */
+ .debounce_max = 1,
+ .debounce_rep = 0,
+ .debounce_tol = (~0),
+ .get_pendown_state = ads7843_pendown_state,
+ };
- at91_set_gpio_output(AT91_PIN_PB7, 1); /* #TURN BUTTONS ON, SHEET 5 of schematics */
- platform_device_register(&yl_9200_button_device);
+ static void __init yl9200_add_device_ts(void)
+ {
+ at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
+ at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
}
#else
- static void __init yl_9200_add_device_buttons(void) {}
+ static void __init yl9200_add_device_ts(void) {}
+ #endif
+
+ /*
+ * SPI devices
+ */
+ static struct spi_board_info yl9200_spi_devices[] = {
+ #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+ { /* Touchscreen */
+ .modalias = "ads7846",
+ .chip_select = 0,
+ .max_speed_hz = 5000 * 26,
+ .platform_data = &ads_info,
+ .irq = AT91_PIN_PB11,
+ },
#endif
+ { /* CAN */
+ .modalias = "mcp2510",
+ .chip_select = 1,
+ .max_speed_hz = 25000 * 26,
+ .irq = AT91_PIN_PC0,
+ }
+ };
+ /*
+ * LCD / VGA
+ *
+ * EPSON S1D13806 FB (discontinued chip)
+ * EPSON S1D13506 FB
+ */
#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
#include <video/s1d13xxxfb.h>
- /* EPSON S1D13806 FB (discontinued chip)*/
- /* EPSON S1D13506 FB */
-
#define AT91_FB_REG_BASE 0x80000000L
#define AT91_FB_REG_SIZE 0x200
#define AT91_FB_VMEM_BASE 0x80200000L
#define AT91_FB_VMEM_SIZE 0x200000L
- /*#define S1D_DISPLAY_WIDTH 640*/
- /*#define S1D_DISPLAY_HEIGHT 480*/
-
-
- static void __init yl_9200_init_video(void)
+ static void __init yl9200_init_video(void)
{
- at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
- at91_sys_write(AT91_PIOC + PIO_BSR,0);
- at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
-
- at91_sys_write( AT91_SMC_CSR(2),
- AT91_SMC_NWS_(0x4) |
- AT91_SMC_WSEN |
- AT91_SMC_TDF_(0x100) |
- AT91_SMC_DBW
- );
-
-
+ /* NWAIT Signal */
+ at91_set_A_periph(AT91_PIN_PC6, 0);
+ /* Initialization of the Static Memory Controller for Chip Select 2 */
+ at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
+ | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
+ | AT91_SMC_TDF_(0x100) /* float time */
+ );
}
-
- static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
+ static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
{
- {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
- {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
- {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
- {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
- {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
- {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
- {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
- {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
- {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
- {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
- {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
- {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
- {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
- {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
- {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
- {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
- {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
- {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
- {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
- {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
- {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
- {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
- {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
- {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
- {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
- {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
- {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
- {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
- {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
- {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
- {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
- {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
- {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
- {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
- {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
- {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
- {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
- {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
- {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
- {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
- {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
- {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
- {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
- {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
- {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
- {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
- {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
- {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
- {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
- {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
- {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
- {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
- {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
- {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
- {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
- {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
- {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
- {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
- {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
- {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
- {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
- {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
- {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
- {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
- {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
- {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
- {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
- {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
- {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
- {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
- {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
- {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
- {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
- {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
- {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
- {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
- {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
- {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
- {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
- {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
- {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
- {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
- {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
- {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
- {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
- {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
- {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
- {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
- {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
- {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
- {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
- {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
- {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
- {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
- {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
- {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
- {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
- {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
- {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
- {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
- {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
- {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
- {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
- {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
- {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
+ {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
+ {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
+ {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
+ {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
+ {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
+ {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
+ {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
+ {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
+ {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
+ {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
+ {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
+ {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
+ {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
+ {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
+ {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
+ {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
+ {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
+ {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
+ {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
+ {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
+ {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
+ {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
+ {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
+ {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
+ {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
+ {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
+ {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
+ {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
+ {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
+ {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
+ {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
+ {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
+ {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
+ {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
+ {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
+ {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
+ {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
+ {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
+ {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
+ {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
+ {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
+ {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
+ {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
+ {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
+ {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
+ {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
+ {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
+ {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
+ {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
+ {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
+ {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
+ {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
+ {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
+ {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
+ {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
+ {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
+ {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
+ {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
+ {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
+ {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
+ {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
+ {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
+ {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
+ {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
+ {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
+ {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
+ {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
+ {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
+ {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
+ {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
+ {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
+ {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
+ {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
+ {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
+ {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
+ {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
+ {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
+ {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
+ {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
+ {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
+ {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
+ {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
+ {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
+ {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
+ {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
+ {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
+ {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
+ {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
+ {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
+ {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
+ {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
+ {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
+ {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
+ {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
+ {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
+ {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
+ {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
+ {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
+ {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
+ {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
+ {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
+ {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
+ {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
+ {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
+ {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
};
- static u64 s1dfb_dmamask = 0xffffffffUL;
+ static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
- static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = {
- .initregs = yl_9200_s1dfb_initregs,
- .initregssize = ARRAY_SIZE(yl_9200_s1dfb_initregs),
- .platform_init_video = yl_9200_init_video,
+ static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
+ .initregs = yl9200_s1dfb_initregs,
+ .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
+ .platform_init_video = yl9200_init_video,
};
- static struct resource yl_9200_s1dfb_resource[] = {
+ static struct resource yl9200_s1dfb_resource[] = {
[0] = { /* video mem */
- .name = "s1d13xxxfb memory",
- /* .name = "s1d13806 memory",*/
- .start = AT91_FB_VMEM_BASE,
- .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
- .flags = IORESOURCE_MEM,
+ .name = "s1d13xxxfb memory",
+ .start = AT91_FB_VMEM_BASE,
+ .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
+ .flags = IORESOURCE_MEM,
},
[1] = { /* video registers */
- .name = "s1d13xxxfb registers",
- /* .name = "s1d13806 registers",*/
- .start = AT91_FB_REG_BASE,
- .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
- .flags = IORESOURCE_MEM,
+ .name = "s1d13xxxfb registers",
+ .start = AT91_FB_REG_BASE,
+ .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
+ .flags = IORESOURCE_MEM,
},
};
- static struct platform_device yl_9200_s1dfb_device = {
- /*TODO S.Birtles , really we need the chip revision in here as well*/
- .name = "s1d13806fb",
- /* .name = "s1d13506fb",*/
- .id = -1,
- .dev = {
- /*TODO theres a waring here!!*/
- /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
+ static struct platform_device yl9200_s1dfb_device = {
+ .name = "s1d13806fb",
+ .id = -1,
+ .dev = {
.dma_mask = &s1dfb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &yl_9200_s1dfb_pdata,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &yl9200_s1dfb_pdata,
},
- .resource = yl_9200_s1dfb_resource,
- .num_resources = ARRAY_SIZE(yl_9200_s1dfb_resource),
+ .resource = yl9200_s1dfb_resource,
+ .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
};
- void __init yl_9200_add_device_video(void)
+ void __init yl9200_add_device_video(void)
{
- platform_device_register(&yl_9200_s1dfb_device);
+ platform_device_register(&yl9200_s1dfb_device);
}
#else
- void __init yl_9200_add_device_video(void) {}
+ void __init yl9200_add_device_video(void) {}
#endif
- /*this is not called first , yl_9200_map_io is called first*/
- static void __init yl_9200_board_init(void)
+
+ static void __init yl9200_board_init(void)
{
/* Serial */
at91_add_device_serial();
/* Ethernet */
- at91_add_device_eth(&yl_9200_eth_data);
+ at91_add_device_eth(&yl9200_eth_data);
/* USB Host */
- at91_add_device_usbh(&yl_9200_usbh_data);
+ at91_add_device_usbh(&yl9200_usbh_data);
/* USB Device */
- at91_add_device_udc(&yl_9200_udc_data);
- /* pullup_pin it is actually active low, but this is not needed, driver sets it up */
- /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
-
- /* Compact Flash */
- /*at91_add_device_cf(&yl_9200_cf_data);*/
-
+ at91_add_device_udc(&yl9200_udc_data);
/* I2C */
- at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices));
- /* SPI */
- /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/
- /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the max 485 NOT SPI*/
-
- /*touch screen and CAN*/
- at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
-
- /*Basically the TS uses PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
- /* we need this incase the board is running without a touch screen*/
- #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
- at91_init_device_ts(); /*init the touch screen device*/
- #endif
- /* DataFlash card */
- at91_add_device_mmc(0, &yl_9200_mmc_data);
+ at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
+ /* MMC */
+ at91_add_device_mmc(0, &yl9200_mmc_data);
/* NAND */
- at91_add_device_nand(&yl_9200_nand_data);
+ at91_add_device_nand(&yl9200_nand_data);
/* NOR Flash */
- platform_device_register(&yl_9200_flash);
- /* LEDs. Note!! this does not include the led's we passed for the processor status */
- at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds));
- /* VGA */
- /*this is self registered by including the s1d13xxx chip in the kernel build*/
- yl_9200_add_device_video();
+ platform_device_register(&yl9200_flash);
+ #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+ /* SPI */
+ at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
+ /* Touchscreen */
+ yl9200_add_device_ts();
+ #endif
+ /* LEDs. */
+ at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
/* Push Buttons */
- yl_9200_add_device_buttons();
- /*TODO fixup the Sounder */
- // yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder));
-
+ yl9200_add_device_buttons();
+ /* VGA */
+ yl9200_add_device_video();
}
MACHINE_START(YL9200, "uCdragon YL-9200")
- /* Maintainer: S.Birtles*/
- .phys_io = AT91_BASE_SYS,
+ /* Maintainer: S.Birtles */
+ .phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
- .timer = &at91rm9200_timer,
- .map_io = yl_9200_map_io,
- .init_irq = yl_9200_init_irq,
- .init_machine = yl_9200_board_init,
+ .timer = &at91rm9200_timer,
+ .map_io = yl9200_map_io,
+ .init_irq = yl9200_init_irq,
+ .init_machine = yl9200_board_init,
MACHINE_END
/*
- * ATSTK1002 daughterboard-specific init code
+ * ATSTK1002/ATSTK1006 daughterboard-specific init code
*
- * Copyright (C) 2005-2006 Atmel Corporation
+ * Copyright (C) 2005-2007 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#include "atstk1000.h"
+ /* Oscillator frequencies. These are board specific */
+ unsigned long at32_board_osc_rates[3] = {
+ [0] = 32768, /* 32.768 kHz on RTC osc */
+ [1] = 20000000, /* 20 MHz on osc0 */
+ [2] = 12000000, /* 12 MHz on osc1 */
+ };
+/*
+ * The ATSTK1006 daughterboard is very similar to the ATSTK1002. Both
+ * have the AT32AP7000 chip on board; the difference is that the
+ * STK1006 has 128 MB SDRAM (the STK1002 uses the 8 MB SDRAM chip on
+ * the STK1000 motherboard) and 256 MB NAND flash (the STK1002 has
+ * none.)
+ *
+ * The RAM difference is handled by the boot loader, so the only
+ * difference we end up handling here is the NAND flash.
+ */
+#ifdef CONFIG_BOARD_ATSTK1006
+#include <linux/mtd/partitions.h>
+#include <asm/arch/smc.h>
+
+static struct smc_timing nand_timing __initdata = {
+ .ncs_read_setup = 0,
+ .nrd_setup = 10,
+ .ncs_write_setup = 0,
+ .nwe_setup = 10,
+
+ .ncs_read_pulse = 30,
+ .nrd_pulse = 15,
+ .ncs_write_pulse = 30,
+ .nwe_pulse = 15,
+
+ .read_cycle = 30,
+ .write_cycle = 30,
+
+ .ncs_read_recover = 0,
+ .nrd_recover = 15,
+ .ncs_write_recover = 0,
+ /* WE# high -> RE# low min 60 ns */
+ .nwe_recover = 50,
+};
+
+static struct smc_config nand_config __initdata = {
+ .bus_width = 1,
+ .nrd_controlled = 1,
+ .nwe_controlled = 1,
+ .nwait_mode = 0,
+ .byte_write = 0,
+ .tdf_cycles = 2,
+ .tdf_mode = 0,
+};
+
+static struct mtd_partition nand_partitions[] = {
+ {
+ .name = "main",
+ .offset = 0x00000000,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct mtd_partition *nand_part_info(int size, int *num_partitions)
+{
+ *num_partitions = ARRAY_SIZE(nand_partitions);
+ return nand_partitions;
+}
+
+struct atmel_nand_data atstk1006_nand_data __initdata = {
+ .cle = 21,
+ .ale = 22,
+ .rdy_pin = GPIO_PIN_PB(30),
+ .enable_pin = GPIO_PIN_PB(29),
+ .partition_info = nand_part_info,
+};
+#endif
+
struct eth_addr {
u8 addr[6];
};
at32_add_system_devices();
+#ifdef CONFIG_BOARD_ATSTK1006
+ smc_set_timing(&nand_config, &nand_timing);
+ smc_set_configuration(3, &nand_config);
+ at32_add_device_nand(0, &atstk1006_nand_data);
+#endif
+
#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
at32_add_device_usart(1);
#else
#ifdef CONFIG_BOARD_ATSTK100X_SPI1
at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
#endif
+ #ifndef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
+ at32_add_device_mci(0, NULL);
+ #endif
#ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
set_hw_addr(at32_add_device_eth(1, ð_data[1]));
#else
at32_add_device_lcdc(0, &atstk1000_lcdc_data,
- fbmem_start, fbmem_size);
+ fbmem_start, fbmem_size, 0);
#endif
at32_add_device_usba(0, NULL);
#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
*/
#include <linux/clk.h>
#include <linux/delay.h>
+ #include <linux/dw_dmac.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/usb/atmel_usba_udc.h>
+ #include <asm/atmel-mci.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/arch/at32ap700x.h>
#include <asm/arch/board.h>
#include <asm/arch/portmux.h>
+ #include <asm/arch/sram.h>
#include <video/atmel_lcdc.h>
static DEFINE_SPINLOCK(pm_lock);
- unsigned long at32ap7000_osc_rates[3] = {
- [0] = 32768,
- /* FIXME: these are ATSTK1002-specific */
- [1] = 20000000,
- [2] = 12000000,
- };
-
static struct clk osc0;
static struct clk osc1;
static unsigned long osc_get_rate(struct clk *clk)
{
- return at32ap7000_osc_rates[clk->index];
+ return at32_board_osc_rates[clk->index];
}
static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
clk->parent = parent;
}
+ static struct dw_dma_platform_data dw_dmac0_data = {
+ .nr_channels = 3,
+ };
+
+ static struct resource dw_dmac0_resource[] = {
+ PBMEM(0xff200000),
+ IRQ(2),
+ };
+ DEFINE_DEV_DATA(dw_dmac, 0);
+ DEV_CLK(hclk, dw_dmac0, hsb, 10);
+
/* --------------------------------------------------------------------
* System peripherals
* -------------------------------------------------------------------- */
.users = 1,
.index = 3,
};
+ static struct clk sdramc_clk = {
+ .name = "sdramc_clk",
+ .parent = &pbb_clk,
+ .mode = pbb_clk_mode,
+ .get_rate = pbb_clk_get_rate,
+ .users = 1,
+ .index = 14,
+ };
static struct resource smc0_resource[] = {
PBMEM(0xfff03400),
.users = 1,
};
- static struct resource dmaca0_resource[] = {
- {
- .start = 0xff200000,
- .end = 0xff20ffff,
- .flags = IORESOURCE_MEM,
- },
- IRQ(2),
- };
- DEFINE_DEV(dmaca, 0);
- DEV_CLK(hclk, dmaca0, hsb, 10);
-
/* --------------------------------------------------------------------
* HMATRIX
* -------------------------------------------------------------------- */
platform_device_register(&at32_eic0_device);
platform_device_register(&smc0_device);
platform_device_register(&pdc_device);
- platform_device_register(&dmaca0_device);
+ platform_device_register(&dw_dmac0_device);
platform_device_register(&at32_tcb0_device);
platform_device_register(&at32_tcb1_device);
platform_device_register(&pio4_device);
}
+ /* --------------------------------------------------------------------
+ * PSIF
+ * -------------------------------------------------------------------- */
+ static struct resource atmel_psif0_resource[] __initdata = {
+ {
+ .start = 0xffe03c00,
+ .end = 0xffe03cff,
+ .flags = IORESOURCE_MEM,
+ },
+ IRQ(18),
+ };
+ static struct clk atmel_psif0_pclk = {
+ .name = "pclk",
+ .parent = &pba_clk,
+ .mode = pba_clk_mode,
+ .get_rate = pba_clk_get_rate,
+ .index = 15,
+ };
+
+ static struct resource atmel_psif1_resource[] __initdata = {
+ {
+ .start = 0xffe03d00,
+ .end = 0xffe03dff,
+ .flags = IORESOURCE_MEM,
+ },
+ IRQ(18),
+ };
+ static struct clk atmel_psif1_pclk = {
+ .name = "pclk",
+ .parent = &pba_clk,
+ .mode = pba_clk_mode,
+ .get_rate = pba_clk_get_rate,
+ .index = 15,
+ };
+
+ struct platform_device *__init at32_add_device_psif(unsigned int id)
+ {
+ struct platform_device *pdev;
+
+ if (!(id == 0 || id == 1))
+ return NULL;
+
+ pdev = platform_device_alloc("atmel_psif", id);
+ if (!pdev)
+ return NULL;
+
+ switch (id) {
+ case 0:
+ if (platform_device_add_resources(pdev, atmel_psif0_resource,
+ ARRAY_SIZE(atmel_psif0_resource)))
+ goto err_add_resources;
+ atmel_psif0_pclk.dev = &pdev->dev;
+ select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
+ select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
+ break;
+ case 1:
+ if (platform_device_add_resources(pdev, atmel_psif1_resource,
+ ARRAY_SIZE(atmel_psif1_resource)))
+ goto err_add_resources;
+ atmel_psif1_pclk.dev = &pdev->dev;
+ select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
+ select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
+ break;
+ default:
+ return NULL;
+ }
+
+ platform_device_add(pdev);
+ return pdev;
+
+ err_add_resources:
+ platform_device_put(pdev);
+ return NULL;
+ }
+
/* --------------------------------------------------------------------
* USART
* -------------------------------------------------------------------- */
switch (id) {
case 0:
pdev = &atmel_spi0_device;
- select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
+ /* pullup MISO so a level is always defined */
+ select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
at32_spi_setup_slaves(0, b, n, spi0_pins);
case 1:
pdev = &atmel_spi1_device;
- select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
+ /* pullup MISO so a level is always defined */
+ select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
at32_spi_setup_slaves(1, b, n, spi1_pins);
.index = 9,
};
- struct platform_device *__init at32_add_device_mci(unsigned int id)
+ struct platform_device *__init
+ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
{
- struct platform_device *pdev;
+ struct mci_platform_data _data;
+ struct platform_device *pdev;
+ struct dw_dma_slave *dws;
if (id != 0)
return NULL;
pdev = platform_device_alloc("atmel_mci", id);
if (!pdev)
- return NULL;
+ goto fail;
if (platform_device_add_resources(pdev, atmel_mci0_resource,
ARRAY_SIZE(atmel_mci0_resource)))
- goto err_add_resources;
+ goto fail;
+
+ if (!data) {
+ data = &_data;
+ memset(data, 0, sizeof(struct mci_platform_data));
+ }
+
+ if (platform_device_add_data(pdev, data,
+ sizeof(struct mci_platform_data)))
+ goto fail;
select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
+ if (data) {
+ if (data->detect_pin != GPIO_PIN_NONE)
+ at32_select_gpio(data->detect_pin, 0);
+ if (data->wp_pin != GPIO_PIN_NONE)
+ at32_select_gpio(data->wp_pin, 0);
+ }
+
atmel_mci0_pclk.dev = &pdev->dev;
platform_device_add(pdev);
return pdev;
- err_add_resources:
+ fail:
platform_device_put(pdev);
return NULL;
}
struct platform_device *__init
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- unsigned long fbmem_start, unsigned long fbmem_len)
+ unsigned long fbmem_start, unsigned long fbmem_len,
+ unsigned int pin_config)
{
struct platform_device *pdev;
struct atmel_lcdfb_info *info;
switch (id) {
case 0:
pdev = &atmel_lcdfb0_device;
- select_peripheral(PC(19), PERIPH_A, 0); /* CC */
- select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
- select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
- select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
- select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
- select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
- select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
- select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
- select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
- select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
- select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
- select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
- select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
- select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
- select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
- select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
- select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
- select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
- select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
- select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
- select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
- select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
- select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
- select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
- select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
- select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
- select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
- select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
- select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
- select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
- select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
+
+ switch (pin_config) {
+ case 0:
+ select_peripheral(PC(19), PERIPH_A, 0); /* CC */
+ select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
+ select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
+ select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
+ select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
+ select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
+ select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
+ select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
+ select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
+ select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
+ select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
+ select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
+ select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
+ select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
+ select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
+ select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
+ select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
+ select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
+ select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
+ select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
+ select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
+ select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
+ select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
+ select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
+ select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
+ select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
+ select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
+ select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
+ select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
+ select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
+ select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
+ break;
+ case 1:
+ select_peripheral(PE(0), PERIPH_B, 0); /* CC */
+ select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
+ select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
+ select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
+ select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
+ select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
+ select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
+ select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
+ select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
+ select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
+ select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
+ select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
+ select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
+ select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
+ select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
+ select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
+ select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
+ select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
+ select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
+ select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
+ select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
+ select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
+ select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
+ select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
+ select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
+ select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
+ select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
+ select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
+ select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
+ select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
+ select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
+ break;
+ default:
+ goto err_invalid_id;
+ }
clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
IRQ(24),
};
static struct clk atmel_pwm0_mck = {
- .name = "mck",
+ .name = "pwm_clk",
.parent = &pbb_clk,
.mode = pbb_clk_mode,
.get_rate = pbb_clk_get_rate,
}
#endif
+/* --------------------------------------------------------------------
+ * NAND Flash / SmartMedia
+ * -------------------------------------------------------------------- */
+static struct resource smc_cs3_resource[] __initdata = {
+ {
+ .start = 0x0c000000,
+ .end = 0x0fffffff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 0xfff03c00,
+ .end = 0xfff03fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device *__init
+at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
+{
+ struct platform_device *pdev;
+
+ if (id != 0 || !data)
+ return NULL;
+
+ pdev = platform_device_alloc("atmel_nand", id);
+ if (!pdev)
+ goto fail;
+
+ if (platform_device_add_resources(pdev, smc_cs3_resource,
+ ARRAY_SIZE(smc_cs3_resource)))
+ goto fail;
+
+ if (platform_device_add_data(pdev, data,
+ sizeof(struct atmel_nand_data)))
+ goto fail;
+
+ set_ebi_sfr_bits(HMATRIX_BIT(CS3A));
+ if (data->enable_pin)
+ at32_select_gpio(data->enable_pin,
+ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
+ if (data->rdy_pin)
+ at32_select_gpio(data->rdy_pin, 0);
+ if (data->det_pin)
+ at32_select_gpio(data->det_pin, 0);
+
+ platform_device_add(pdev);
+ return pdev;
+
+fail:
+ platform_device_put(pdev);
+ return NULL;
+}
+
/* --------------------------------------------------------------------
* AC97C
* -------------------------------------------------------------------- */
&hmatrix_clk,
&ebi_clk,
&hramc_clk,
+ &sdramc_clk,
&smc0_pclk,
&smc0_mck,
&pdc_hclk,
&pdc_pclk,
- &dmaca0_hclk,
+ &dw_dmac0_hclk,
&pico_clk,
&pio0_mck,
&pio1_mck,
&pio4_mck,
&at32_tcb0_t0_clk,
&at32_tcb1_t0_clk,
+ &atmel_psif0_pclk,
+ &atmel_psif1_pclk,
&atmel_usart0_usart,
&atmel_usart1_usart,
&atmel_usart2_usart,
};
unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
- void __init at32_portmux_init(void)
- {
- at32_init_pio(&pio0_device);
- at32_init_pio(&pio1_device);
- at32_init_pio(&pio2_device);
- at32_init_pio(&pio3_device);
- at32_init_pio(&pio4_device);
- }
-
- void __init at32_clock_init(void)
+ void __init setup_platform(void)
{
u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
int i;
pm_writel(HSB_MASK, hsb_mask);
pm_writel(PBA_MASK, pba_mask);
pm_writel(PBB_MASK, pbb_mask);
+
+ /* Initialize the port muxes */
+ at32_init_pio(&pio0_device);
+ at32_init_pio(&pio1_device);
+ at32_init_pio(&pio2_device);
+ at32_init_pio(&pio3_device);
+ at32_init_pio(&pio4_device);
+ }
+
+ struct gen_pool *sram_pool;
+
+ static int __init sram_init(void)
+ {
+ struct gen_pool *pool;
+
+ /* 1KiB granularity */
+ pool = gen_pool_create(10, -1);
+ if (!pool)
+ goto fail;
+
+ if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
+ goto err_pool_add;
+
+ sram_pool = pool;
+ return 0;
+
+ err_pool_add:
+ gen_pool_destroy(pool);
+ fail:
+ pr_err("Failed to create SRAM pool\n");
+ return -ENOMEM;
}
+ core_initcall(sram_init);
/*
- * $Id: block2mtd.c,v 1.30 2005/11/29 14:48:32 gleixner Exp $
- *
* block2mtd.c - create an mtd from a block device
*
* Copyright (C) 2001,2002 Simon Evans <spse@secret.org.uk>
#include <linux/mutex.h>
#include <linux/mount.h>
-#define VERSION "$Revision: 1.30 $"
-
-
#define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
#define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
{
struct block_device *bdev;
struct block2mtd_dev *dev;
+ char *name;
if (!devname)
return NULL;
/* Setup the MTD structure */
/* make the name contain the block device in */
- dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname),
+ name = kmalloc(sizeof("block2mtd: ") + strlen(devname) + 1,
GFP_KERNEL);
- if (!dev->mtd.name)
+ if (!name)
goto devinit_err;
- sprintf(dev->mtd.name, "block2mtd: %s", devname);
+ sprintf(name, "block2mtd: %s", devname);
+ dev->mtd.name = name;
dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
dev->mtd.erasesize = erase_size;
static int __init block2mtd_init(void)
{
int ret = 0;
- INFO("version " VERSION);
#ifndef MODULE
if (strlen(block2mtd_paramline))
/* This version ported to the Linux-MTD system by dwmw2@infradead.org
- * $Id: ftl.c,v 1.59 2005/11/29 14:48:31 gleixner Exp $
*
* Fixes: Arnaldo Carvalho de Melo <acme@conectiva.com.br>
* - fixes some leaks on failure in build_maps and ftl_notify_add, cleanups
u_int16_t DataUnits;
u_int32_t BlocksPerUnit;
erase_unit_header_t header;
- #if 0
- region_info_t region;
- memory_handle_t handle;
- #endif
} partition_t;
/* Partition state flags */
static int init_ftl(void)
{
- DEBUG(0, "$Id: ftl.c,v 1.59 2005/11/29 14:48:31 gleixner Exp $\n");
-
return register_mtd_blktrans(&ftl_tr);
}
# drivers/mtd/maps/Kconfig
-# $Id: Kconfig,v 1.61 2005/11/07 11:14:26 gleixner Exp $
menu "Mapping drivers for chip access"
depends on MTD!=n
help
Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards
- config MTD_MTX1
- tristate "4G Systems MTX-1 Flash device"
- depends on MIPS_MTX1 && MTD_CFI
- help
- Flash memory access on 4G Systems MTX-1 Board. If you have one of
- these boards and would like to use the flash chips on it, say 'Y'.
-
config MTD_DILNETPC
tristate "CFI Flash device mapped on DIL/Net PC"
depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT
If unsure, say N.
+config MTD_BFIN_ASYNC
+ tristate "Blackfin BF533-STAMP Flash Chip Support"
+ depends on BFIN533_STAMP && MTD_CFI
+ select MTD_PARTITIONS
+ default y
+ help
+ Map driver which allows for simultaneous utilization of
+ ethernet and CFI parallel flash.
+
+ If compiled as a module, it will be called bfin-async-flash.
+
config MTD_UCLINUX
tristate "Generic uClinux RAM/ROM filesystem support"
depends on MTD_PARTITIONS && !MMU
help
Map driver for Dy-4 SVME/DMV-182 board.
-config MTD_BAST
- tristate "Map driver for Simtec BAST (EB2410ITX) or Thorcom VR1000"
- depends on ARCH_BAST || MACH_VR1000
- select MTD_PARTITIONS
- select MTD_MAP_BANK_WIDTH_16
- select MTD_JEDECPROBE
- help
- Map driver for NOR flash on the Simtec BAST (EB2410ITX), or the
- Thorcom VR1000
-
- Note, this driver *cannot* over-ride the WP link on the
- board, or currently detect the state of the link.
-
-config MTD_BAST_MAXSIZE
- int "Maximum size for BAST flash area (MiB)"
- depends on MTD_BAST
- default "4"
-
config MTD_SHARP_SL
tristate "ROM mapped on Sharp SL Series"
depends on ARCH_PXA
#
# linux/drivers/maps/Makefile
#
-# $Id: Makefile.common,v 1.34 2005/11/07 11:14:26 gleixner Exp $
ifeq ($(CONFIG_MTD_COMPLEX_MAPPINGS),y)
obj-$(CONFIG_MTD) += map_funcs.o
# Chip mappings
obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
-obj-$(CONFIG_MTD_BAST) += bast-flash.o
obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
obj-$(CONFIG_MTD_DC21285) += dc21285.o
obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o
obj-$(CONFIG_MTD_SHARP_SL) += sharpsl-flash.o
obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o
obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
- obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o
+obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o
/*
- * $Id: pcmciamtd.c,v 1.55 2005/11/07 11:14:28 gleixner Exp $
- *
* pcmciamtd.c - MTD driver for PCMCIA flash memory cards
*
* Author: Simon Evans <spse@secret.org.uk>
#define DRIVER_DESC "PCMCIA Flash memory card driver"
-#define DRIVER_VERSION "$Revision: 1.55 $"
/* Size of the PCMCIA address space: 26 bits = 64 MB */
#define MAX_PCMCIA_ADDR 0x4000000
int i;
config_info_t t;
static char *probes[] = { "jedec_probe", "cfi_probe" };
- cisinfo_t cisinfo;
int new_name = 0;
DEBUG(3, "link=0x%p", link);
DEBUG(2, "Validating CIS");
- ret = pcmcia_validate_cis(link, &cisinfo);
+ ret = pcmcia_validate_cis(link, NULL);
if(ret != CS_SUCCESS) {
cs_error(link, GetTupleData, ret);
- } else {
- DEBUG(2, "ValidateCIS found %d chains", cisinfo.Chains);
}
card_settings(dev, link, &new_name);
DEBUG(1, "Allocated a window of %dKiB", dev->win_size >> 10);
/* Get write protect status */
- CS_CHECK(GetStatus, pcmcia_get_status(link, &status));
- DEBUG(2, "status value: 0x%x window handle = 0x%8.8lx",
- status.CardState, (unsigned long)link->win);
+ DEBUG(2, "window handle = 0x%8.8lx", (unsigned long)link->win);
dev->win_base = ioremap(req.Base, req.Size);
if(!dev->win_base) {
err("ioremap(%lu, %u) failed", req.Base, req.Size);
static int __init init_pcmciamtd(void)
{
- info(DRIVER_DESC " " DRIVER_VERSION);
+ info(DRIVER_DESC);
if(bankwidth && bankwidth != 1 && bankwidth != 2) {
info("bad bankwidth (%d), using default", bankwidth);
/*
- * $Id: mtdchar.c,v 1.76 2005/11/07 11:14:20 gleixner Exp $
- *
* Character-device access to raw MTD devices.
*
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/sched.h>
+ #include <linux/smp_lock.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/compatmac.h>
if (!mtd)
return;
- device_create(mtd_class, NULL, MKDEV(MTD_CHAR_MAJOR, mtd->index*2), "mtd%d", mtd->index);
+ device_create_drvdata(mtd_class, NULL,
+ MKDEV(MTD_CHAR_MAJOR, mtd->index*2),
+ NULL, "mtd%d", mtd->index);
- device_create(mtd_class, NULL,
- MKDEV(MTD_CHAR_MAJOR, mtd->index*2+1), "mtd%dro", mtd->index);
+ device_create_drvdata(mtd_class, NULL,
+ MKDEV(MTD_CHAR_MAJOR, mtd->index*2+1),
+ NULL, "mtd%dro", mtd->index);
}
static void mtd_notify_remove(struct mtd_info* mtd)
{
int minor = iminor(inode);
int devnum = minor >> 1;
+ int ret = 0;
struct mtd_info *mtd;
struct mtd_file_info *mfi;
if ((file->f_mode & 2) && (minor & 1))
return -EACCES;
+ lock_kernel();
mtd = get_mtd_device(NULL, devnum);
- if (IS_ERR(mtd))
- return PTR_ERR(mtd);
+ if (IS_ERR(mtd)) {
+ ret = PTR_ERR(mtd);
+ goto out;
+ }
if (MTD_ABSENT == mtd->type) {
put_mtd_device(mtd);
- return -ENODEV;
+ ret = -ENODEV;
+ goto out;
}
/* You can't open it RW if it's not a writeable device */
if ((file->f_mode & 2) && !(mtd->flags & MTD_WRITEABLE)) {
put_mtd_device(mtd);
- return -EACCES;
+ ret = -EACCES;
+ goto out;
}
mfi = kzalloc(sizeof(*mfi), GFP_KERNEL);
if (!mfi) {
put_mtd_device(mtd);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto out;
}
mfi->mtd = mtd;
file->private_data = mfi;
- return 0;
+ out:
+ unlock_kernel();
+ return ret;
} /* mtd_open */
/*====================================================================*/
{
struct mtd_oob_buf buf;
struct mtd_oob_ops ops;
+ struct mtd_oob_buf __user *user_buf = argp;
uint32_t retlen;
if(!(file->f_mode & 2))
if (ops.oobretlen > 0xFFFFFFFFU)
ret = -EOVERFLOW;
retlen = ops.oobretlen;
- if (copy_to_user(&((struct mtd_oob_buf *)argp)->length,
- &retlen, sizeof(buf.length)))
+ if (copy_to_user(&user_buf->length, &retlen, sizeof(buf.length)))
ret = -EFAULT;
kfree(ops.oobbuf);
case MEMLOCK:
{
- struct erase_info_user info;
+ struct erase_info_user einfo;
- if (copy_from_user(&info, argp, sizeof(info)))
+ if (copy_from_user(&einfo, argp, sizeof(einfo)))
return -EFAULT;
if (!mtd->lock)
ret = -EOPNOTSUPP;
else
- ret = mtd->lock(mtd, info.start, info.length);
+ ret = mtd->lock(mtd, einfo.start, einfo.length);
break;
}
case MEMUNLOCK:
{
- struct erase_info_user info;
+ struct erase_info_user einfo;
- if (copy_from_user(&info, argp, sizeof(info)))
+ if (copy_from_user(&einfo, argp, sizeof(einfo)))
return -EFAULT;
if (!mtd->unlock)
ret = -EOPNOTSUPP;
else
- ret = mtd->unlock(mtd, info.start, info.length);
+ ret = mtd->unlock(mtd, einfo.start, einfo.length);
break;
}
case OTPLOCK:
{
- struct otp_info info;
+ struct otp_info oinfo;
if (mfi->mode != MTD_MODE_OTP_USER)
return -EINVAL;
- if (copy_from_user(&info, argp, sizeof(info)))
+ if (copy_from_user(&oinfo, argp, sizeof(oinfo)))
return -EFAULT;
if (!mtd->lock_user_prot_reg)
return -EOPNOTSUPP;
- ret = mtd->lock_user_prot_reg(mtd, info.start, info.length);
+ ret = mtd->lock_user_prot_reg(mtd, oinfo.start, oinfo.length);
break;
}
#endif
#include <linux/i2c.h>
#include <linux/leds.h>
#include <linux/spi/spi.h>
+ #include <linux/usb/atmel_usba_udc.h>
/* USB Device */
struct at91_udc_data {
};
extern void __init at91_add_device_udc(struct at91_udc_data *data);
+ /* USB High Speed Device */
+ extern void __init at91_add_device_usba(struct usba_platform_data *data);
+
/* Compact Flash */
struct at91_cf_data {
u8 irq_pin; /* I/O IRQ */
};
extern void __init at91_add_device_eth(struct at91_eth_data *data);
- #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
+ #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
#define eth_platform_data at91_eth_data
#endif
extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
/* NAND / SmartMedia */
-struct at91_nand_data {
+struct atmel_nand_data {
u8 enable_pin; /* chip enable */
u8 det_pin; /* card detect */
u8 rdy_pin; /* ready/busy */
u8 bus_width_16; /* buswidth is 16 bit */
struct mtd_partition* (*partition_info)(int, int*);
};
-extern void __init at91_add_device_nand(struct at91_nand_data *data);
+extern void __init at91_add_device_nand(struct atmel_nand_data *data);
/* I2C*/
extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
#define GPIO_PIN_NONE (-1)
+ /*
+ * Clock rates for various on-board oscillators. The number of entries
+ * in this array is chip-dependent.
+ */
+ extern unsigned long at32_board_osc_rates[];
+
/* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
void at32_add_system_devices(void);
struct atmel_lcdfb_info;
struct platform_device *
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- unsigned long fbmem_start, unsigned long fbmem_len);
+ unsigned long fbmem_start, unsigned long fbmem_len,
+ unsigned int pin_config);
struct usba_platform_data;
struct platform_device *
struct platform_device *at32_add_device_twi(unsigned int id,
struct i2c_board_info *b,
unsigned int n);
- struct platform_device *at32_add_device_mci(unsigned int id);
+
+ struct mci_platform_data;
+ struct platform_device *
+ at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
+
struct platform_device *at32_add_device_ac97c(unsigned int id);
struct platform_device *at32_add_device_abdac(unsigned int id);
+ struct platform_device *at32_add_device_psif(unsigned int id);
struct cf_platform_data {
int detect_pin;
at32_add_device_cf(unsigned int id, unsigned int extint,
struct cf_platform_data *data);
+/* NAND / SmartMedia */
+struct atmel_nand_data {
+ int enable_pin; /* chip enable */
+ int det_pin; /* card detect */
+ int rdy_pin; /* ready/busy */
+ u8 ale; /* address line number connected to ALE */
+ u8 cle; /* address line number connected to CLE */
+ u8 bus_width_16; /* buswidth is 16 bit */
+ struct mtd_partition *(*partition_info)(int size, int *num_partitions);
+};
+struct platform_device *
+at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
+
#endif /* __ASM_ARCH_BOARD_H */
/* Overhauled routines for dealing with different mmap regions of flash */
-/* $Id: map.h,v 1.54 2005/11/07 11:14:54 gleixner Exp $ */
#ifndef __LINUX_MTD_MAP_H__
#define __LINUX_MTD_MAP_H__
*/
struct map_info {
- char *name;
+ const char *name;
unsigned long size;
resource_size_t phys;
#define NO_XIP (-1UL)
/*
- * $Id: mtd.h,v 1.61 2005/11/07 11:14:54 gleixner Exp $
- *
* Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al.
*
* Released under GPL
u_int32_t oobavail; // Available OOB bytes per block
// Kernel-only stuff starts here.
- char *name;
+ const char *name;
int index;
/* ecc layout structure pointer - read only ! */
projects / linux-2.6-omap-h63xx.git / commitdiff