]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/commitdiff
Merge branch 'linus' into x86/urgent
authorIngo Molnar <mingo@elte.hu>
Mon, 25 Aug 2008 12:39:12 +0000 (14:39 +0200)
committerIngo Molnar <mingo@elte.hu>
Mon, 25 Aug 2008 12:39:12 +0000 (14:39 +0200)
arch/x86/kernel/cpu/mcheck/mce_64.c
arch/x86/kernel/cpu/mcheck/mce_amd_64.c
arch/x86/kernel/tsc.c
arch/x86/pci/amd_bus.c
arch/x86/pci/i386.c
include/asm-x86/mce.h

index 65a339678ece817b3b27fa56afb5ee97aae8d027..726a5fcdf34113efe492ecdaa324308aa1a61fbd 100644 (file)
@@ -759,6 +759,7 @@ static struct sysdev_class mce_sysclass = {
 };
 
 DEFINE_PER_CPU(struct sys_device, device_mce);
+void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu) __cpuinitdata;
 
 /* Why are there no generic functions for this? */
 #define ACCESSOR(name, var, start) \
@@ -883,9 +884,13 @@ static int __cpuinit mce_cpu_callback(struct notifier_block *nfb,
        case CPU_ONLINE:
        case CPU_ONLINE_FROZEN:
                mce_create_device(cpu);
+               if (threshold_cpu_callback)
+                       threshold_cpu_callback(action, cpu);
                break;
        case CPU_DEAD:
        case CPU_DEAD_FROZEN:
+               if (threshold_cpu_callback)
+                       threshold_cpu_callback(action, cpu);
                mce_remove_device(cpu);
                break;
        }
index 88736cadbaa62d02e5e36671b06cfa512df7e683..5eb390a4b2e9159d980fcfcbc68f8d1d4f42c258 100644 (file)
@@ -628,6 +628,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
        deallocate_threshold_block(cpu, bank);
 
 free_out:
+       kobject_del(b->kobj);
        kobject_put(b->kobj);
        kfree(b);
        per_cpu(threshold_banks, cpu)[bank] = NULL;
@@ -645,14 +646,11 @@ static void threshold_remove_device(unsigned int cpu)
 }
 
 /* get notified when a cpu comes on/off */
-static int __cpuinit threshold_cpu_callback(struct notifier_block *nfb,
-                                           unsigned long action, void *hcpu)
+static void __cpuinit amd_64_threshold_cpu_callback(unsigned long action,
+                                                    unsigned int cpu)
 {
-       /* cpu was unsigned int to begin with */
-       unsigned int cpu = (unsigned long)hcpu;
-
        if (cpu >= NR_CPUS)
-               goto out;
+               return;
 
        switch (action) {
        case CPU_ONLINE:
@@ -666,14 +664,8 @@ static int __cpuinit threshold_cpu_callback(struct notifier_block *nfb,
        default:
                break;
        }
-      out:
-       return NOTIFY_OK;
 }
 
-static struct notifier_block threshold_cpu_notifier __cpuinitdata = {
-       .notifier_call = threshold_cpu_callback,
-};
-
 static __init int threshold_init_device(void)
 {
        unsigned lcpu = 0;
@@ -684,7 +676,7 @@ static __init int threshold_init_device(void)
                if (err)
                        return err;
        }
-       register_hotcpu_notifier(&threshold_cpu_notifier);
+       threshold_cpu_callback = amd_64_threshold_cpu_callback;
        return 0;
 }
 
index 46af71676738e4ec49640fdcaacd20a85c034bc8..9bed5cae4bdcc31671c36b09393d854ac3327b14 100644 (file)
@@ -325,6 +325,10 @@ static struct notifier_block time_cpufreq_notifier_block = {
 
 static int __init cpufreq_tsc(void)
 {
+       if (!cpu_has_tsc)
+               return 0;
+       if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
+               return 0;
        cpufreq_register_notifier(&time_cpufreq_notifier_block,
                                CPUFREQ_TRANSITION_NOTIFIER);
        return 0;
index dbf5323697110709fb365c534e5a26ad1c3ec5f5..6a0fca78c36236aeedb3579a3b306f01426e15e7 100644 (file)
@@ -1,6 +1,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/topology.h>
+#include <linux/cpu.h>
 #include "pci.h"
 
 #ifdef CONFIG_X86_64
@@ -555,15 +556,17 @@ static int __init early_fill_mp_bus_info(void)
        return 0;
 }
 
-postcore_initcall(early_fill_mp_bus_info);
+#else  /* !CONFIG_X86_64 */
 
-#endif
+static int __init early_fill_mp_bus_info(void) { return 0; }
+
+#endif /* !CONFIG_X86_64 */
 
 /* common 32/64 bit code */
 
 #define ENABLE_CF8_EXT_CFG      (1ULL << 46)
 
-static void enable_pci_io_ecs_per_cpu(void *unused)
+static void enable_pci_io_ecs(void *unused)
 {
        u64 reg;
        rdmsrl(MSR_AMD64_NB_CFG, reg);
@@ -573,14 +576,51 @@ static void enable_pci_io_ecs_per_cpu(void *unused)
        }
 }
 
-static int __init enable_pci_io_ecs(void)
+static int __cpuinit amd_cpu_notify(struct notifier_block *self,
+                                   unsigned long action, void *hcpu)
 {
+       int cpu = (long)hcpu;
+       switch(action) {
+       case CPU_ONLINE:
+       case CPU_ONLINE_FROZEN:
+               smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
+               break;
+       default:
+               break;
+       }
+       return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata amd_cpu_notifier = {
+       .notifier_call  = amd_cpu_notify,
+};
+
+static int __init pci_io_ecs_init(void)
+{
+       int cpu;
+
        /* assume all cpus from fam10h have IO ECS */
         if (boot_cpu_data.x86 < 0x10)
                return 0;
-       on_each_cpu(enable_pci_io_ecs_per_cpu, NULL, 1);
+
+       register_cpu_notifier(&amd_cpu_notifier);
+       for_each_online_cpu(cpu)
+               amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
+                              (void *)(long)cpu);
        pci_probe |= PCI_HAS_IO_ECS;
+
+       return 0;
+}
+
+static int __init amd_postcore_init(void)
+{
+       if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+               return 0;
+
+       early_fill_mp_bus_info();
+       pci_io_ecs_init();
+
        return 0;
 }
 
-postcore_initcall(enable_pci_io_ecs);
+postcore_initcall(amd_postcore_init);
index 5807d1bc73f74639c81cf4dec9255ec26e076c73..d765da9138428209207718d169d81e539237b0d6 100644 (file)
 #include <linux/ioport.h>
 #include <linux/errno.h>
 #include <linux/bootmem.h>
+#include <linux/acpi.h>
 
 #include <asm/pat.h>
+#include <asm/hpet.h>
+#include <asm/io_apic.h>
 
 #include "pci.h"
 
@@ -77,6 +80,77 @@ pcibios_align_resource(void *data, struct resource *res,
 }
 EXPORT_SYMBOL(pcibios_align_resource);
 
+static int check_res_with_valid(struct pci_dev *dev, struct resource *res)
+{
+       unsigned long base;
+       unsigned long size;
+       int i;
+
+       base = res->start;
+       size = (res->start == 0 && res->end == res->start) ? 0 :
+                (res->end - res->start + 1);
+
+       if (!base || !size)
+               return 0;
+
+#ifdef CONFIG_HPET_TIMER
+       /* for hpet */
+       if (base == hpet_address && (res->flags & IORESOURCE_MEM)) {
+               dev_info(&dev->dev, "BAR has HPET at %08lx-%08lx\n",
+                                base, base + size - 1);
+               return 1;
+       }
+#endif
+
+#ifdef CONFIG_X86_IO_APIC
+       for (i = 0; i < nr_ioapics; i++) {
+               unsigned long ioapic_phys = mp_ioapics[i].mp_apicaddr;
+
+               if (base == ioapic_phys && (res->flags & IORESOURCE_MEM)) {
+                       dev_info(&dev->dev, "BAR has ioapic at %08lx-%08lx\n",
+                                        base, base + size - 1);
+                       return 1;
+               }
+       }
+#endif
+
+#ifdef CONFIG_PCI_MMCONFIG
+       for (i = 0; i < pci_mmcfg_config_num; i++) {
+               unsigned long addr;
+
+               addr = pci_mmcfg_config[i].address;
+               if (base == addr && (res->flags & IORESOURCE_MEM)) {
+                       dev_info(&dev->dev, "BAR has MMCONFIG at %08lx-%08lx\n",
+                                        base, base + size - 1);
+                       return 1;
+               }
+       }
+#endif
+
+       return 0;
+}
+
+static int check_platform(struct pci_dev *dev, struct resource *res)
+{
+       struct resource *root = NULL;
+
+       /*
+        * forcibly insert it into the
+        * resource tree
+        */
+       if (res->flags & IORESOURCE_MEM)
+               root = &iomem_resource;
+       else if (res->flags & IORESOURCE_IO)
+               root = &ioport_resource;
+
+       if (root && check_res_with_valid(dev, res)) {
+               insert_resource(root, res);
+
+               return 1;
+       }
+
+       return 0;
+}
 /*
  *  Handle resources of PCI devices.  If the world were perfect, we could
  *  just allocate all the resource regions and do nothing more.  It isn't.
@@ -128,6 +202,8 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
                                pr = pci_find_parent_resource(dev, r);
                                if (!r->start || !pr ||
                                    request_resource(pr, r) < 0) {
+                                       if (check_platform(dev, r))
+                                               continue;
                                        dev_err(&dev->dev, "BAR %d: can't "
                                                "allocate resource\n", idx);
                                        /*
@@ -171,6 +247,8 @@ static void __init pcibios_allocate_resources(int pass)
                                        r->flags, disabled, pass);
                                pr = pci_find_parent_resource(dev, r);
                                if (!pr || request_resource(pr, r) < 0) {
+                                       if (check_platform(dev, r))
+                                               continue;
                                        dev_err(&dev->dev, "BAR %d: can't "
                                                "allocate resource\n", idx);
                                        /* We'll assign a new address later */
index 94f1fd79e22a9512511b9660363290b535e7424e..531eaa587455a90c2274ef5f5491e8214dd51ccf 100644 (file)
@@ -92,6 +92,7 @@ extern int mce_disabled;
 
 void mce_log(struct mce *m);
 DECLARE_PER_CPU(struct sys_device, device_mce);
+extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 
 #ifdef CONFIG_X86_MCE_INTEL
 void mce_intel_feature_init(struct cpuinfo_x86 *c);