*     saved at this time.
         */
        isolate_state = SPU_STATUS_ISOLATED_STATE |
-           SPU_STATUS_ISOLATED_LOAD_STAUTUS | SPU_STATUS_ISOLATED_EXIT_STAUTUS;
+           SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
        return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
 }
 
         */
        if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
                if (in_be32(&prob->spu_status_R) &
-                   SPU_STATUS_ISOLATED_EXIT_STAUTUS) {
+                   SPU_STATUS_ISOLATED_EXIT_STATUS) {
                        POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
                                        SPU_STATUS_RUNNING);
                }
                if ((in_be32(&prob->spu_status_R) &
-                    SPU_STATUS_ISOLATED_LOAD_STAUTUS)
+                    SPU_STATUS_ISOLATED_LOAD_STATUS)
                    || (in_be32(&prob->spu_status_R) &
                        SPU_STATUS_ISOLATED_STATE)) {
                        out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
         */
        if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
                if (in_be32(&prob->spu_status_R) &
-                   SPU_STATUS_ISOLATED_EXIT_STAUTUS) {
+                   SPU_STATUS_ISOLATED_EXIT_STATUS) {
                        spu_mfc_sr1_set(spu,
                                        MFC_STATE1_MASTER_RUN_CONTROL_MASK);
                        eieio();
                                        SPU_STATUS_RUNNING);
                }
                if ((in_be32(&prob->spu_status_R) &
-                    SPU_STATUS_ISOLATED_LOAD_STAUTUS)
+                    SPU_STATUS_ISOLATED_LOAD_STATUS)
                    || (in_be32(&prob->spu_status_R) &
                        SPU_STATUS_ISOLATED_STATE)) {
                        spu_mfc_sr1_set(spu,
 
 #define SPU_STATUS_INVALID_INSTR        0x20
 #define SPU_STATUS_INVALID_CH           0x40
 #define SPU_STATUS_ISOLATED_STATE       0x80
-#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
-#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
+#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
+#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
        u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
        u32 spu_spe_R;                                          /* 0x402c */
        u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */