Merge commit 'origin/master' into next

diff --combined arch/powerpc/sysdev/ppc4xx_pci.c
index ef0fafcbfbcb9364d2d3de442152fac8a878ef4c,5558d932b4d5c87b84f5a3826577607fa5220514..6a2d473c345a35595a58e5a2a4b1dd637b3dbb84
--- 1/arch/powerpc/sysdev/ppc4xx_pci.c
--- 2/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@@ -204,6 -204,23 +204,23 @@@ static int __init ppc4xx_setup_one_pci_
  {
        u32 ma, pcila, pciha;
  
+       /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
+        * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
+        * address are actually hard wired to a value that appears to depend
+        * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
+        *
+        * The trick here is we just crop those top bits and ignore them when
+        * programming the chip. That means the device-tree has to be right
+        * for the specific part used (we don't print a warning if it's wrong
+        * but on the other hand, you'll crash quickly enough), but at least
+        * this code should work whatever the hard coded value is
+        */
+       plb_addr &= 0xffffffffull;
+ 
+       /* Note: Due to the above hack, the test below doesn't actually test
+        * if you address is above 4G, but it tests that address and
+        * (address + size) are both contained in the same 4G
+        */
        if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
            size < 0x1000 || (plb_addr & (size - 1)) != 0) {
                printk(KERN_WARNING "%s: Resource out of range\n",
@@@ -1822,8 -1839,6 +1839,8 @@@ static int __init ppc4xx_pci_find_bridg
  {
        struct device_node *np;
  
 +      ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
 +
  #ifdef CONFIG_PPC4xx_PCI_EXPRESS
        for_each_compatible_node(np, NULL, "ibm,plb-pciex")
                ppc4xx_probe_pciex_bridge(np);

diff --combined include/linux/pci_ids.h
index 807f1ad8b76043e83f571cc27932dc88a678c0a7,aca8c458aa8a7a23e87198ce8a9cb9eba8f3d87b..f37fe506105e55091bbcfd9684d54812b125edbb
--- 1/include/linux/pci_ids.h
--- 2/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@@ -1445,6 -1445,7 +1445,7 @@@
  #define PCI_DEVICE_ID_DIGI_DF_M_E     0x0071
  #define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A        0x0072
  #define PCI_DEVICE_ID_DIGI_DF_M_A     0x0073
+ #define PCI_DEVICE_ID_DIGI_NEO_8      0x00B1
  #define PCI_DEVICE_ID_NEO_2DB9          0x00C8
  #define PCI_DEVICE_ID_NEO_2DB9PRI       0x00C9
  #define PCI_DEVICE_ID_NEO_2RJ45         0x00CA
@@@ -2218,14 -2219,6 +2219,14 @@@
  #define PCI_DEVICE_ID_TDI_EHCI          0x0101
  
  #define PCI_VENDOR_ID_FREESCALE               0x1957
 +#define PCI_DEVICE_ID_MPC8315E                0x00b4
 +#define PCI_DEVICE_ID_MPC8315         0x00b5
 +#define PCI_DEVICE_ID_MPC8314E                0x00b6
 +#define PCI_DEVICE_ID_MPC8314         0x00b7
 +#define PCI_DEVICE_ID_MPC8378E                0x00c4
 +#define PCI_DEVICE_ID_MPC8378         0x00c5
 +#define PCI_DEVICE_ID_MPC8377E                0x00c6
 +#define PCI_DEVICE_ID_MPC8377         0x00c7
  #define PCI_DEVICE_ID_MPC8548E                0x0012
  #define PCI_DEVICE_ID_MPC8548         0x0013
  #define PCI_DEVICE_ID_MPC8543E                0x0014
@@@ -2330,6 -2323,9 +2331,9 @@@
  #define PCI_DEVICE_ID_INTEL_82378     0x0484
  #define PCI_DEVICE_ID_INTEL_I960      0x0960
  #define PCI_DEVICE_ID_INTEL_I960RM    0x0962
+ #define PCI_DEVICE_ID_INTEL_8257X_SOL 0x1062
+ #define PCI_DEVICE_ID_INTEL_82573E_SOL        0x1085
+ #define PCI_DEVICE_ID_INTEL_82573L_SOL        0x108F
  #define PCI_DEVICE_ID_INTEL_82815_MC  0x1130
  #define PCI_DEVICE_ID_INTEL_82815_CGC 0x1132
  #define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221