]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/commitdiff
[PATCH] i386: Prevent early access to TSC to avoid crash on TSCless systems
authorThomas Gleixner <tglx@linutronix.de>
Sat, 24 Mar 2007 22:02:49 +0000 (23:02 +0100)
committerLinus Torvalds <torvalds@woody.linux-foundation.org>
Sat, 24 Mar 2007 22:45:53 +0000 (15:45 -0700)
commit f9690982b8c2f9a2c65acdc113e758ec356676a3 removed the check for
cpu_khz from sched_clock(), which prevented early access to the TSC by
non obvious magic.

This is harmless as long as the CPU has a TSC. On TSCless systems this
results in an illegal instruction trap.

Replace tsc_disabled and tsc_unstable by tsc_enabled, which is only set
when the tsc is available and not unstable.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
arch/i386/kernel/tsc.c

index 0e65f7ab63a204081d908507eb35baddc157dde8..6cb8f53367324c46fc5efcdc070afb5f02c01add 100644 (file)
@@ -18,6 +18,8 @@
 
 #include "mach_timer.h"
 
+static int tsc_enabled;
+
 /*
  * On some systems the TSC frequency does not
  * change with the cpu frequency. So we need
@@ -105,7 +107,7 @@ unsigned long long sched_clock(void)
        /*
         * Fall back to jiffies if there's no TSC available:
         */
-       if (tsc_unstable || unlikely(tsc_disable))
+       if (unlikely(!tsc_enabled))
                /* No locking but a rare wrong value is not a big deal: */
                return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
 
@@ -283,6 +285,7 @@ void mark_tsc_unstable(void)
 {
        if (!tsc_unstable) {
                tsc_unstable = 1;
+               tsc_enabled = 0;
                /* Can be called before registration */
                if (clocksource_tsc.mult)
                        clocksource_change_rating(&clocksource_tsc, 0);
@@ -383,7 +386,9 @@ void __init tsc_init(void)
        if (check_tsc_unstable()) {
                clocksource_tsc.rating = 0;
                clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
-       }
+       } else
+               tsc_enabled = 1;
+
        clocksource_register(&clocksource_tsc);
 
        return;